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Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next
This commit is contained in:
David S. Miller
@@ -129,7 +129,6 @@
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!Finclude/net/cfg80211.h cfg80211_pmksa
|
||||
!Finclude/net/cfg80211.h cfg80211_send_rx_auth
|
||||
!Finclude/net/cfg80211.h cfg80211_send_auth_timeout
|
||||
!Finclude/net/cfg80211.h __cfg80211_auth_canceled
|
||||
!Finclude/net/cfg80211.h cfg80211_send_rx_assoc
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||||
!Finclude/net/cfg80211.h cfg80211_send_assoc_timeout
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!Finclude/net/cfg80211.h cfg80211_send_deauth
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@@ -4914,8 +4914,6 @@ F: fs/ocfs2/
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||||
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ORINOCO DRIVER
|
||||
L: linux-wireless@vger.kernel.org
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||||
L: orinoco-users@lists.sourceforge.net
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||||
L: orinoco-devel@lists.sourceforge.net
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W: http://linuxwireless.org/en/users/Drivers/orinoco
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W: http://www.nongnu.org/orinoco/
|
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S: Orphan
|
||||
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||||
@@ -25,6 +25,7 @@
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/ssb/ssb.h>
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#include <linux/bcma/bcma.h>
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#include <bcm47xx.h>
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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@@ -32,15 +33,12 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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return 0;
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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#ifdef CONFIG_BCM47XX_SSB
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static int bcm47xx_pcibios_plat_dev_init_ssb(struct pci_dev *dev)
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{
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int res;
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u8 slot, pin;
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if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB)
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return 0;
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res = ssb_pcibios_plat_dev_init(dev);
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if (res < 0) {
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printk(KERN_ALERT "PCI: Failed to init device %s\n",
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@@ -60,6 +58,47 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
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}
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dev->irq = res;
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev)
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{
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int res;
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res = bcma_core_pci_plat_dev_init(dev);
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if (res < 0) {
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printk(KERN_ALERT "PCI: Failed to init device %s\n",
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pci_name(dev));
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return res;
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}
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res = bcma_core_pci_pcibios_map_irq(dev);
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/* IRQ-0 and IRQ-1 are software interrupts. */
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if (res < 2) {
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printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n",
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pci_name(dev));
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return res;
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}
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dev->irq = res;
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return 0;
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}
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#endif
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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#ifdef CONFIG_BCM47XX_SSB
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if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_SSB)
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return bcm47xx_pcibios_plat_dev_init_ssb(dev);
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else
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA)
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return bcm47xx_pcibios_plat_dev_init_bcma(dev);
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else
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#endif
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return 0;
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}
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@@ -13,7 +13,7 @@
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struct bcma_bus;
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||||
/* main.c */
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int bcma_bus_register(struct bcma_bus *bus);
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int __devinit bcma_bus_register(struct bcma_bus *bus);
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void bcma_bus_unregister(struct bcma_bus *bus);
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int __init bcma_bus_early_register(struct bcma_bus *bus,
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struct bcma_device *core_cc,
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@@ -48,8 +48,12 @@ extern int __init bcma_host_pci_init(void);
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extern void __exit bcma_host_pci_exit(void);
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#endif /* CONFIG_BCMA_HOST_PCI */
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/* driver_pci.c */
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u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
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bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
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void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
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#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
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#endif
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+78
-90
@@ -2,8 +2,9 @@
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* Broadcom specific AMBA
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||||
* PCI Core
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2005, 2011, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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@@ -16,40 +17,41 @@
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* R/W ops.
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**************************************************/
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static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
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u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
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{
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pcicore_write32(pc, 0x130, address);
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pcicore_read32(pc, 0x130);
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return pcicore_read32(pc, 0x134);
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
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pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
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return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
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}
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#if 0
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static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
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{
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pcicore_write32(pc, 0x130, address);
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pcicore_read32(pc, 0x130);
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pcicore_write32(pc, 0x134, data);
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
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pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
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}
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#endif
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static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
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{
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const u16 mdio_control = 0x128;
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const u16 mdio_data = 0x12C;
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u32 v;
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int i;
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v = (1 << 30); /* Start of Transaction */
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v |= (1 << 28); /* Write Transaction */
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v |= (1 << 17); /* Turnaround */
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v |= (0x1F << 18);
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_WRITE;
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v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
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BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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v |= (phy << 4);
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pcicore_write32(pc, mdio_data, v);
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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udelay(10);
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for (i = 0; i < 200; i++) {
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v = pcicore_read32(pc, mdio_control);
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if (v & 0x100 /* Trans complete */)
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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msleep(1);
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}
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@@ -57,79 +59,84 @@ static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
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static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
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{
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const u16 mdio_control = 0x128;
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const u16 mdio_data = 0x12C;
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int max_retries = 10;
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u16 ret = 0;
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u32 v;
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int i;
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v = 0x80; /* Enable Preamble Sequence */
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v |= 0x2; /* MDIO Clock Divisor */
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pcicore_write32(pc, mdio_control, v);
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/* enable mdio access to SERDES */
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v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
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v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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} else {
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v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
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}
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v = (1 << 30); /* Start of Transaction */
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v |= (1 << 29); /* Read Transaction */
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v |= (1 << 17); /* Turnaround */
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if (pc->core->id.rev < 10)
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v |= (u32)device << 22;
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v |= (u32)address << 18;
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pcicore_write32(pc, mdio_data, v);
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_READ;
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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v = pcicore_read32(pc, mdio_control);
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if (v & 0x100 /* Trans complete */) {
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
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udelay(10);
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ret = pcicore_read32(pc, mdio_data);
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ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
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break;
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}
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msleep(1);
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}
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pcicore_write32(pc, mdio_control, 0);
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
|
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return ret;
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}
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static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
|
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u8 address, u16 data)
|
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{
|
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const u16 mdio_control = 0x128;
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const u16 mdio_data = 0x12C;
|
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int max_retries = 10;
|
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u32 v;
|
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int i;
|
||||
|
||||
v = 0x80; /* Enable Preamble Sequence */
|
||||
v |= 0x2; /* MDIO Clock Divisor */
|
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pcicore_write32(pc, mdio_control, v);
|
||||
/* enable mdio access to SERDES */
|
||||
v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
|
||||
v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
|
||||
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
|
||||
|
||||
if (pc->core->id.rev >= 10) {
|
||||
max_retries = 200;
|
||||
bcma_pcie_mdio_set_phy(pc, device);
|
||||
v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
|
||||
BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
|
||||
v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
|
||||
} else {
|
||||
v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
|
||||
v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
|
||||
}
|
||||
|
||||
v = (1 << 30); /* Start of Transaction */
|
||||
v |= (1 << 28); /* Write Transaction */
|
||||
v |= (1 << 17); /* Turnaround */
|
||||
if (pc->core->id.rev < 10)
|
||||
v |= (u32)device << 22;
|
||||
v |= (u32)address << 18;
|
||||
v = BCMA_CORE_PCI_MDIODATA_START;
|
||||
v |= BCMA_CORE_PCI_MDIODATA_WRITE;
|
||||
v |= BCMA_CORE_PCI_MDIODATA_TA;
|
||||
v |= data;
|
||||
pcicore_write32(pc, mdio_data, v);
|
||||
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
|
||||
/* Wait for the device to complete the transaction */
|
||||
udelay(10);
|
||||
for (i = 0; i < max_retries; i++) {
|
||||
v = pcicore_read32(pc, mdio_control);
|
||||
if (v & 0x100 /* Trans complete */)
|
||||
v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
|
||||
if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
|
||||
break;
|
||||
msleep(1);
|
||||
}
|
||||
pcicore_write32(pc, mdio_control, 0);
|
||||
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
|
||||
}
|
||||
|
||||
/**************************************************
|
||||
@@ -138,72 +145,53 @@ static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
|
||||
|
||||
static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
|
||||
{
|
||||
return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
|
||||
u32 tmp;
|
||||
|
||||
tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
|
||||
if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
|
||||
return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
|
||||
BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
|
||||
else
|
||||
return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
|
||||
}
|
||||
|
||||
static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
|
||||
{
|
||||
const u8 serdes_pll_device = 0x1D;
|
||||
const u8 serdes_rx_device = 0x1F;
|
||||
u16 tmp;
|
||||
|
||||
bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
|
||||
bcma_pcicore_polarity_workaround(pc));
|
||||
tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
|
||||
if (tmp & 0x4000)
|
||||
bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
|
||||
bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
|
||||
BCMA_CORE_PCI_SERDES_RX_CTRL,
|
||||
bcma_pcicore_polarity_workaround(pc));
|
||||
tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
|
||||
BCMA_CORE_PCI_SERDES_PLL_CTRL);
|
||||
if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
|
||||
bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
|
||||
BCMA_CORE_PCI_SERDES_PLL_CTRL,
|
||||
tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
|
||||
}
|
||||
|
||||
/**************************************************
|
||||
* Init.
|
||||
**************************************************/
|
||||
|
||||
static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
|
||||
static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
|
||||
{
|
||||
bcma_pcicore_serdes_workaround(pc);
|
||||
}
|
||||
|
||||
static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
|
||||
{
|
||||
struct bcma_bus *bus = pc->core->bus;
|
||||
u16 chipid_top;
|
||||
|
||||
chipid_top = (bus->chipinfo.id & 0xFF00);
|
||||
if (chipid_top != 0x4700 &&
|
||||
chipid_top != 0x5300)
|
||||
return false;
|
||||
|
||||
#ifdef CONFIG_SSB_DRIVER_PCICORE
|
||||
if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
|
||||
return false;
|
||||
#endif /* CONFIG_SSB_DRIVER_PCICORE */
|
||||
|
||||
#if 0
|
||||
/* TODO: on BCMA we use address from EROM instead of magic formula */
|
||||
u32 tmp;
|
||||
return !mips_busprobe32(tmp, (bus->mmio +
|
||||
(pc->core->core_index * BCMA_CORE_SIZE)));
|
||||
#endif
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void bcma_core_pci_init(struct bcma_drv_pci *pc)
|
||||
void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
|
||||
{
|
||||
if (pc->setup_done)
|
||||
return;
|
||||
|
||||
if (bcma_core_pci_is_in_hostmode(pc)) {
|
||||
#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
|
||||
pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
|
||||
if (pc->hostmode)
|
||||
bcma_core_pci_hostmode_init(pc);
|
||||
#else
|
||||
pr_err("Driver compiled without support for hostmode PCI\n");
|
||||
#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
|
||||
} else {
|
||||
bcma_core_pci_clientmode_init(pc);
|
||||
}
|
||||
|
||||
pc->setup_done = true;
|
||||
if (!pc->hostmode)
|
||||
bcma_core_pci_clientmode_init(pc);
|
||||
}
|
||||
|
||||
int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -154,8 +154,8 @@ const struct bcma_host_ops bcma_host_pci_ops = {
|
||||
.awrite32 = bcma_host_pci_awrite32,
|
||||
};
|
||||
|
||||
static int bcma_host_pci_probe(struct pci_dev *dev,
|
||||
const struct pci_device_id *id)
|
||||
static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
|
||||
const struct pci_device_id *id)
|
||||
{
|
||||
struct bcma_bus *bus;
|
||||
int err = -ENOMEM;
|
||||
|
||||
+12
-2
@@ -13,6 +13,12 @@
|
||||
MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
/* contains the number the next bus should get. */
|
||||
static unsigned int bcma_bus_next_num = 0;
|
||||
|
||||
/* bcma_buses_mutex locks the bcma_bus_next_num */
|
||||
static DEFINE_MUTEX(bcma_buses_mutex);
|
||||
|
||||
static int bcma_bus_match(struct device *dev, struct device_driver *drv);
|
||||
static int bcma_device_probe(struct device *dev);
|
||||
static int bcma_device_remove(struct device *dev);
|
||||
@@ -93,7 +99,7 @@ static int bcma_register_cores(struct bcma_bus *bus)
|
||||
|
||||
core->dev.release = bcma_release_core_dev;
|
||||
core->dev.bus = &bcma_bus_type;
|
||||
dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
|
||||
dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
|
||||
|
||||
switch (bus->hosttype) {
|
||||
case BCMA_HOSTTYPE_PCI:
|
||||
@@ -132,11 +138,15 @@ static void bcma_unregister_cores(struct bcma_bus *bus)
|
||||
}
|
||||
}
|
||||
|
||||
int bcma_bus_register(struct bcma_bus *bus)
|
||||
int __devinit bcma_bus_register(struct bcma_bus *bus)
|
||||
{
|
||||
int err;
|
||||
struct bcma_device *core;
|
||||
|
||||
mutex_lock(&bcma_buses_mutex);
|
||||
bus->num = bcma_bus_next_num++;
|
||||
mutex_unlock(&bcma_buses_mutex);
|
||||
|
||||
/* Scan for devices (cores) */
|
||||
err = bcma_bus_scan(bus);
|
||||
if (err) {
|
||||
|
||||
+21
-3
@@ -212,6 +212,17 @@ static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
|
||||
{
|
||||
struct bcma_device *core;
|
||||
|
||||
list_for_each_entry_reverse(core, &bus->cores, list) {
|
||||
if (core->id.id == coreid)
|
||||
return core;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
|
||||
struct bcma_device_id *match, int core_num,
|
||||
struct bcma_device *core)
|
||||
@@ -353,6 +364,7 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
|
||||
void bcma_init_bus(struct bcma_bus *bus)
|
||||
{
|
||||
s32 tmp;
|
||||
struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
|
||||
|
||||
if (bus->init_done)
|
||||
return;
|
||||
@@ -363,9 +375,12 @@ void bcma_init_bus(struct bcma_bus *bus)
|
||||
bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
|
||||
|
||||
tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
|
||||
bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
|
||||
bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
|
||||
bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
|
||||
chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
|
||||
chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
|
||||
chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
|
||||
pr_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
|
||||
chipinfo->id, chipinfo->rev, chipinfo->pkg);
|
||||
|
||||
bus->init_done = true;
|
||||
}
|
||||
|
||||
@@ -392,6 +407,7 @@ int bcma_bus_scan(struct bcma_bus *bus)
|
||||
bcma_scan_switch_core(bus, erombase);
|
||||
|
||||
while (eromptr < eromend) {
|
||||
struct bcma_device *other_core;
|
||||
struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
|
||||
if (!core)
|
||||
return -ENOMEM;
|
||||
@@ -414,6 +430,8 @@ int bcma_bus_scan(struct bcma_bus *bus)
|
||||
|
||||
core->core_index = core_num++;
|
||||
bus->nr_cores++;
|
||||
other_core = bcma_find_core_reverse(bus, core->id.id);
|
||||
core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
|
||||
|
||||
pr_info("Core %d found: %s "
|
||||
"(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
|
||||
|
||||
@@ -250,6 +250,7 @@ int bcma_sprom_get(struct bcma_bus *bus)
|
||||
{
|
||||
u16 offset;
|
||||
u16 *sprom;
|
||||
u32 sromctrl;
|
||||
int err = 0;
|
||||
|
||||
if (!bus->drv_cc.core)
|
||||
@@ -258,6 +259,12 @@ int bcma_sprom_get(struct bcma_bus *bus)
|
||||
if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
|
||||
return -ENOENT;
|
||||
|
||||
if (bus->drv_cc.core->id.rev >= 32) {
|
||||
sromctrl = bcma_read32(bus->drv_cc.core, BCMA_CC_SROM_CONTROL);
|
||||
if (!(sromctrl & BCMA_CC_SROM_CONTROL_PRESENT))
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
|
||||
GFP_KERNEL);
|
||||
if (!sprom)
|
||||
|
||||
@@ -102,6 +102,7 @@ static struct usb_device_id btusb_table[] = {
|
||||
|
||||
/* Broadcom BCM20702A0 */
|
||||
{ USB_DEVICE(0x0a5c, 0x21e3) },
|
||||
{ USB_DEVICE(0x0a5c, 0x21f3) },
|
||||
{ USB_DEVICE(0x413c, 0x8197) },
|
||||
|
||||
{ } /* Terminating entry */
|
||||
@@ -726,9 +727,6 @@ static int btusb_send_frame(struct sk_buff *skb)
|
||||
usb_fill_bulk_urb(urb, data->udev, pipe,
|
||||
skb->data, skb->len, btusb_tx_complete, skb);
|
||||
|
||||
if (skb->priority >= HCI_PRIO_MAX - 1)
|
||||
urb->transfer_flags = URB_ISO_ASAP;
|
||||
|
||||
hdev->stat.acl_tx++;
|
||||
break;
|
||||
|
||||
|
||||
@@ -1,12 +1,29 @@
|
||||
config ATH6KL
|
||||
tristate "Atheros ath6kl support"
|
||||
tristate "Atheros mobile chipsets support"
|
||||
|
||||
config ATH6KL_SDIO
|
||||
tristate "Atheros ath6kl SDIO support"
|
||||
depends on ATH6KL
|
||||
depends on MMC
|
||||
depends on CFG80211
|
||||
---help---
|
||||
This module adds support for wireless adapters based on
|
||||
Atheros AR6003 chipset running over SDIO. If you choose to
|
||||
build it as a module, it will be called ath6kl. Pls note
|
||||
that AR6002 and AR6001 are not supported by this driver.
|
||||
Atheros AR6003 and AR6004 chipsets running over SDIO. If you
|
||||
choose to build it as a module, it will be called ath6kl_sdio.
|
||||
Please note that AR6002 and AR6001 are not supported by this
|
||||
driver.
|
||||
|
||||
config ATH6KL_USB
|
||||
tristate "Atheros ath6kl USB support"
|
||||
depends on ATH6KL
|
||||
depends on USB
|
||||
depends on CFG80211
|
||||
depends on EXPERIMENTAL
|
||||
---help---
|
||||
This module adds support for wireless adapters based on
|
||||
Atheros AR6004 chipset running over USB. This is still under
|
||||
implementation and it isn't functional. If you choose to
|
||||
build it as a module, it will be called ath6kl_usb.
|
||||
|
||||
config ATH6KL_DEBUG
|
||||
bool "Atheros ath6kl debugging"
|
||||
|
||||
@@ -21,17 +21,21 @@
|
||||
# Author(s): ="Atheros"
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
obj-$(CONFIG_ATH6KL) := ath6kl.o
|
||||
ath6kl-y += debug.o
|
||||
ath6kl-y += hif.o
|
||||
ath6kl-y += htc.o
|
||||
ath6kl-y += bmi.o
|
||||
ath6kl-y += cfg80211.o
|
||||
ath6kl-y += init.o
|
||||
ath6kl-y += main.o
|
||||
ath6kl-y += txrx.o
|
||||
ath6kl-y += wmi.o
|
||||
ath6kl-y += sdio.o
|
||||
ath6kl-$(CONFIG_NL80211_TESTMODE) += testmode.o
|
||||
obj-$(CONFIG_ATH6KL) += ath6kl_core.o
|
||||
ath6kl_core-y += debug.o
|
||||
ath6kl_core-y += hif.o
|
||||
ath6kl_core-y += htc.o
|
||||
ath6kl_core-y += bmi.o
|
||||
ath6kl_core-y += cfg80211.o
|
||||
ath6kl_core-y += init.o
|
||||
ath6kl_core-y += main.o
|
||||
ath6kl_core-y += txrx.o
|
||||
ath6kl_core-y += wmi.o
|
||||
ath6kl_core-y += core.o
|
||||
ath6kl_core-$(CONFIG_NL80211_TESTMODE) += testmode.o
|
||||
|
||||
ccflags-y += -D__CHECK_ENDIAN__
|
||||
obj-$(CONFIG_ATH6KL_SDIO) += ath6kl_sdio.o
|
||||
ath6kl_sdio-y += sdio.o
|
||||
|
||||
obj-$(CONFIG_ATH6KL_USB) += ath6kl_usb.o
|
||||
ath6kl_usb-y += usb.o
|
||||
|
||||
@@ -57,8 +57,14 @@ int ath6kl_bmi_get_target_info(struct ath6kl *ar,
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = ath6kl_hif_bmi_read(ar, (u8 *)&targ_info->version,
|
||||
sizeof(targ_info->version));
|
||||
if (ar->hif_type == ATH6KL_HIF_TYPE_USB) {
|
||||
ret = ath6kl_hif_bmi_read(ar, (u8 *)targ_info,
|
||||
sizeof(*targ_info));
|
||||
} else {
|
||||
ret = ath6kl_hif_bmi_read(ar, (u8 *)&targ_info->version,
|
||||
sizeof(targ_info->version));
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
ath6kl_err("Unable to recv target info: %d\n", ret);
|
||||
return ret;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -27,10 +27,6 @@ enum ath6kl_cfg_suspend_mode {
|
||||
struct net_device *ath6kl_interface_add(struct ath6kl *ar, char *name,
|
||||
enum nl80211_iftype type,
|
||||
u8 fw_vif_idx, u8 nw_type);
|
||||
int ath6kl_register_ieee80211_hw(struct ath6kl *ar);
|
||||
struct ath6kl *ath6kl_core_alloc(struct device *dev);
|
||||
void ath6kl_deinit_ieee80211_hw(struct ath6kl *ar);
|
||||
|
||||
void ath6kl_cfg80211_scan_complete_event(struct ath6kl_vif *vif, bool aborted);
|
||||
|
||||
void ath6kl_cfg80211_connect_event(struct ath6kl_vif *vif, u16 channel,
|
||||
@@ -53,7 +49,15 @@ int ath6kl_cfg80211_suspend(struct ath6kl *ar,
|
||||
|
||||
int ath6kl_cfg80211_resume(struct ath6kl *ar);
|
||||
|
||||
void ath6kl_cfg80211_vif_cleanup(struct ath6kl_vif *vif);
|
||||
|
||||
void ath6kl_cfg80211_stop(struct ath6kl_vif *vif);
|
||||
void ath6kl_cfg80211_stop_all(struct ath6kl *ar);
|
||||
|
||||
int ath6kl_cfg80211_init(struct ath6kl *ar);
|
||||
void ath6kl_cfg80211_cleanup(struct ath6kl *ar);
|
||||
|
||||
struct ath6kl *ath6kl_cfg80211_create(void);
|
||||
void ath6kl_cfg80211_destroy(struct ath6kl *ar);
|
||||
|
||||
#endif /* ATH6KL_CFG80211_H */
|
||||
|
||||
@@ -79,8 +79,5 @@ struct ath6kl;
|
||||
enum htc_credit_dist_reason;
|
||||
struct ath6kl_htc_credit_info;
|
||||
|
||||
struct ath6kl *ath6kl_core_alloc(struct device *sdev);
|
||||
int ath6kl_core_init(struct ath6kl *ar);
|
||||
void ath6kl_core_cleanup(struct ath6kl *ar);
|
||||
struct sk_buff *ath6kl_buf_alloc(int size);
|
||||
#endif /* COMMON_H */
|
||||
|
||||
@@ -0,0 +1,316 @@
|
||||
/*
|
||||
* Copyright (c) 2004-2011 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "core.h"
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
#include "debug.h"
|
||||
#include "hif-ops.h"
|
||||
#include "cfg80211.h"
|
||||
|
||||
unsigned int debug_mask;
|
||||
static unsigned int suspend_mode;
|
||||
static unsigned int uart_debug;
|
||||
static unsigned int ath6kl_p2p;
|
||||
static unsigned int testmode;
|
||||
|
||||
module_param(debug_mask, uint, 0644);
|
||||
module_param(suspend_mode, uint, 0644);
|
||||
module_param(uart_debug, uint, 0644);
|
||||
module_param(ath6kl_p2p, uint, 0644);
|
||||
module_param(testmode, uint, 0644);
|
||||
|
||||
int ath6kl_core_init(struct ath6kl *ar)
|
||||
{
|
||||
struct ath6kl_bmi_target_info targ_info;
|
||||
struct net_device *ndev;
|
||||
int ret = 0, i;
|
||||
|
||||
ar->ath6kl_wq = create_singlethread_workqueue("ath6kl");
|
||||
if (!ar->ath6kl_wq)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = ath6kl_bmi_init(ar);
|
||||
if (ret)
|
||||
goto err_wq;
|
||||
|
||||
/*
|
||||
* Turn on power to get hardware (target) version and leave power
|
||||
* on delibrately as we will boot the hardware anyway within few
|
||||
* seconds.
|
||||
*/
|
||||
ret = ath6kl_hif_power_on(ar);
|
||||
if (ret)
|
||||
goto err_bmi_cleanup;
|
||||
|
||||
ret = ath6kl_bmi_get_target_info(ar, &targ_info);
|
||||
if (ret)
|
||||
goto err_power_off;
|
||||
|
||||
ar->version.target_ver = le32_to_cpu(targ_info.version);
|
||||
ar->target_type = le32_to_cpu(targ_info.type);
|
||||
ar->wiphy->hw_version = le32_to_cpu(targ_info.version);
|
||||
|
||||
ret = ath6kl_init_hw_params(ar);
|
||||
if (ret)
|
||||
goto err_power_off;
|
||||
|
||||
ar->htc_target = ath6kl_htc_create(ar);
|
||||
|
||||
if (!ar->htc_target) {
|
||||
ret = -ENOMEM;
|
||||
goto err_power_off;
|
||||
}
|
||||
|
||||
ar->testmode = testmode;
|
||||
|
||||
ret = ath6kl_init_fetch_firmwares(ar);
|
||||
if (ret)
|
||||
goto err_htc_cleanup;
|
||||
|
||||
/* FIXME: we should free all firmwares in the error cases below */
|
||||
|
||||
/* Indicate that WMI is enabled (although not ready yet) */
|
||||
set_bit(WMI_ENABLED, &ar->flag);
|
||||
ar->wmi = ath6kl_wmi_init(ar);
|
||||
if (!ar->wmi) {
|
||||
ath6kl_err("failed to initialize wmi\n");
|
||||
ret = -EIO;
|
||||
goto err_htc_cleanup;
|
||||
}
|
||||
|
||||
ath6kl_dbg(ATH6KL_DBG_TRC, "%s: got wmi @ 0x%p.\n", __func__, ar->wmi);
|
||||
|
||||
ret = ath6kl_cfg80211_init(ar);
|
||||
if (ret)
|
||||
goto err_node_cleanup;
|
||||
|
||||
ret = ath6kl_debug_init(ar);
|
||||
if (ret) {
|
||||
wiphy_unregister(ar->wiphy);
|
||||
goto err_node_cleanup;
|
||||
}
|
||||
|
||||
for (i = 0; i < ar->vif_max; i++)
|
||||
ar->avail_idx_map |= BIT(i);
|
||||
|
||||
rtnl_lock();
|
||||
|
||||
/* Add an initial station interface */
|
||||
ndev = ath6kl_interface_add(ar, "wlan%d", NL80211_IFTYPE_STATION, 0,
|
||||
INFRA_NETWORK);
|
||||
|
||||
rtnl_unlock();
|
||||
|
||||
if (!ndev) {
|
||||
ath6kl_err("Failed to instantiate a network device\n");
|
||||
ret = -ENOMEM;
|
||||
wiphy_unregister(ar->wiphy);
|
||||
goto err_debug_init;
|
||||
}
|
||||
|
||||
|
||||
ath6kl_dbg(ATH6KL_DBG_TRC, "%s: name=%s dev=0x%p, ar=0x%p\n",
|
||||
__func__, ndev->name, ndev, ar);
|
||||
|
||||
/* setup access class priority mappings */
|
||||
ar->ac_stream_pri_map[WMM_AC_BK] = 0; /* lowest */
|
||||
ar->ac_stream_pri_map[WMM_AC_BE] = 1;
|
||||
ar->ac_stream_pri_map[WMM_AC_VI] = 2;
|
||||
ar->ac_stream_pri_map[WMM_AC_VO] = 3; /* highest */
|
||||
|
||||
/* give our connected endpoints some buffers */
|
||||
ath6kl_rx_refill(ar->htc_target, ar->ctrl_ep);
|
||||
ath6kl_rx_refill(ar->htc_target, ar->ac2ep_map[WMM_AC_BE]);
|
||||
|
||||
/* allocate some buffers that handle larger AMSDU frames */
|
||||
ath6kl_refill_amsdu_rxbufs(ar, ATH6KL_MAX_AMSDU_RX_BUFFERS);
|
||||
|
||||
ath6kl_cookie_init(ar);
|
||||
|
||||
ar->conf_flags = ATH6KL_CONF_IGNORE_ERP_BARKER |
|
||||
ATH6KL_CONF_ENABLE_11N | ATH6KL_CONF_ENABLE_TX_BURST;
|
||||
|
||||
if (suspend_mode &&
|
||||
suspend_mode >= WLAN_POWER_STATE_CUT_PWR &&
|
||||
suspend_mode <= WLAN_POWER_STATE_WOW)
|
||||
ar->suspend_mode = suspend_mode;
|
||||
else
|
||||
ar->suspend_mode = 0;
|
||||
|
||||
if (uart_debug)
|
||||
ar->conf_flags |= ATH6KL_CONF_UART_DEBUG;
|
||||
|
||||
ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM |
|
||||
WIPHY_FLAG_HAVE_AP_SME |
|
||||
WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
|
||||
WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD;
|
||||
|
||||
if (test_bit(ATH6KL_FW_CAPABILITY_SCHED_SCAN, ar->fw_capabilities))
|
||||
ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN;
|
||||
|
||||
ar->wiphy->probe_resp_offload =
|
||||
NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS |
|
||||
NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS2 |
|
||||
NL80211_PROBE_RESP_OFFLOAD_SUPPORT_P2P |
|
||||
NL80211_PROBE_RESP_OFFLOAD_SUPPORT_80211U;
|
||||
|
||||
set_bit(FIRST_BOOT, &ar->flag);
|
||||
|
||||
ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
|
||||
|
||||
ret = ath6kl_init_hw_start(ar);
|
||||
if (ret) {
|
||||
ath6kl_err("Failed to start hardware: %d\n", ret);
|
||||
goto err_rxbuf_cleanup;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set mac address which is received in ready event
|
||||
* FIXME: Move to ath6kl_interface_add()
|
||||
*/
|
||||
memcpy(ndev->dev_addr, ar->mac_addr, ETH_ALEN);
|
||||
|
||||
return ret;
|
||||
|
||||
err_rxbuf_cleanup:
|
||||
ath6kl_htc_flush_rx_buf(ar->htc_target);
|
||||
ath6kl_cleanup_amsdu_rxbufs(ar);
|
||||
rtnl_lock();
|
||||
ath6kl_cfg80211_vif_cleanup(netdev_priv(ndev));
|
||||
rtnl_unlock();
|
||||
wiphy_unregister(ar->wiphy);
|
||||
err_debug_init:
|
||||
ath6kl_debug_cleanup(ar);
|
||||
err_node_cleanup:
|
||||
ath6kl_wmi_shutdown(ar->wmi);
|
||||
clear_bit(WMI_ENABLED, &ar->flag);
|
||||
ar->wmi = NULL;
|
||||
err_htc_cleanup:
|
||||
ath6kl_htc_cleanup(ar->htc_target);
|
||||
err_power_off:
|
||||
ath6kl_hif_power_off(ar);
|
||||
err_bmi_cleanup:
|
||||
ath6kl_bmi_cleanup(ar);
|
||||
err_wq:
|
||||
destroy_workqueue(ar->ath6kl_wq);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(ath6kl_core_init);
|
||||
|
||||
struct ath6kl *ath6kl_core_create(struct device *dev)
|
||||
{
|
||||
struct ath6kl *ar;
|
||||
u8 ctr;
|
||||
|
||||
ar = ath6kl_cfg80211_create();
|
||||
if (!ar)
|
||||
return NULL;
|
||||
|
||||
ar->p2p = !!ath6kl_p2p;
|
||||
ar->dev = dev;
|
||||
|
||||
ar->vif_max = 1;
|
||||
|
||||
ar->max_norm_iface = 1;
|
||||
|
||||
spin_lock_init(&ar->lock);
|
||||
spin_lock_init(&ar->mcastpsq_lock);
|
||||
spin_lock_init(&ar->list_lock);
|
||||
|
||||
init_waitqueue_head(&ar->event_wq);
|
||||
sema_init(&ar->sem, 1);
|
||||
|
||||
INIT_LIST_HEAD(&ar->amsdu_rx_buffer_queue);
|
||||
INIT_LIST_HEAD(&ar->vif_list);
|
||||
|
||||
clear_bit(WMI_ENABLED, &ar->flag);
|
||||
clear_bit(SKIP_SCAN, &ar->flag);
|
||||
clear_bit(DESTROY_IN_PROGRESS, &ar->flag);
|
||||
|
||||
ar->listen_intvl_b = A_DEFAULT_LISTEN_INTERVAL;
|
||||
ar->tx_pwr = 0;
|
||||
|
||||
ar->intra_bss = 1;
|
||||
ar->lrssi_roam_threshold = DEF_LRSSI_ROAM_THRESHOLD;
|
||||
|
||||
ar->state = ATH6KL_STATE_OFF;
|
||||
|
||||
memset((u8 *)ar->sta_list, 0,
|
||||
AP_MAX_NUM_STA * sizeof(struct ath6kl_sta));
|
||||
|
||||
/* Init the PS queues */
|
||||
for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) {
|
||||
spin_lock_init(&ar->sta_list[ctr].psq_lock);
|
||||
skb_queue_head_init(&ar->sta_list[ctr].psq);
|
||||
skb_queue_head_init(&ar->sta_list[ctr].apsdq);
|
||||
ar->sta_list[ctr].aggr_conn =
|
||||
kzalloc(sizeof(struct aggr_info_conn), GFP_KERNEL);
|
||||
if (!ar->sta_list[ctr].aggr_conn) {
|
||||
ath6kl_err("Failed to allocate memory for sta aggregation information\n");
|
||||
ath6kl_core_destroy(ar);
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
skb_queue_head_init(&ar->mcastpsq);
|
||||
|
||||
memcpy(ar->ap_country_code, DEF_AP_COUNTRY_CODE, 3);
|
||||
|
||||
return ar;
|
||||
}
|
||||
EXPORT_SYMBOL(ath6kl_core_create);
|
||||
|
||||
void ath6kl_core_cleanup(struct ath6kl *ar)
|
||||
{
|
||||
ath6kl_hif_power_off(ar);
|
||||
|
||||
destroy_workqueue(ar->ath6kl_wq);
|
||||
|
||||
if (ar->htc_target)
|
||||
ath6kl_htc_cleanup(ar->htc_target);
|
||||
|
||||
ath6kl_cookie_cleanup(ar);
|
||||
|
||||
ath6kl_cleanup_amsdu_rxbufs(ar);
|
||||
|
||||
ath6kl_bmi_cleanup(ar);
|
||||
|
||||
ath6kl_debug_cleanup(ar);
|
||||
|
||||
kfree(ar->fw_board);
|
||||
kfree(ar->fw_otp);
|
||||
kfree(ar->fw);
|
||||
kfree(ar->fw_patch);
|
||||
kfree(ar->fw_testscript);
|
||||
|
||||
ath6kl_cfg80211_cleanup(ar);
|
||||
}
|
||||
EXPORT_SYMBOL(ath6kl_core_cleanup);
|
||||
|
||||
void ath6kl_core_destroy(struct ath6kl *ar)
|
||||
{
|
||||
ath6kl_cfg80211_destroy(ar);
|
||||
}
|
||||
EXPORT_SYMBOL(ath6kl_core_destroy);
|
||||
|
||||
MODULE_AUTHOR("Qualcomm Atheros");
|
||||
MODULE_DESCRIPTION("Core module for AR600x SDIO and USB devices.");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
@@ -44,6 +44,10 @@
|
||||
#define ATH6KL_MAX_ENDPOINTS 4
|
||||
#define MAX_NODE_NUM 15
|
||||
|
||||
#define ATH6KL_APSD_ALL_FRAME 0xFFFF
|
||||
#define ATH6KL_APSD_NUM_OF_AC 0x4
|
||||
#define ATH6KL_APSD_FRAME_MASK 0xF
|
||||
|
||||
/* Extra bytes for htc header alignment */
|
||||
#define ATH6KL_HTC_ALIGN_BYTES 3
|
||||
|
||||
@@ -55,7 +59,7 @@
|
||||
#define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
|
||||
|
||||
#define DISCON_TIMER_INTVAL 10000 /* in msec */
|
||||
#define A_DEFAULT_LISTEN_INTERVAL 100
|
||||
#define A_DEFAULT_LISTEN_INTERVAL 1 /* beacon intervals */
|
||||
#define A_MAX_WOW_LISTEN_INTERVAL 1000
|
||||
|
||||
/* includes also the null byte */
|
||||
@@ -97,45 +101,49 @@ struct ath6kl_fw_ie {
|
||||
u8 data[0];
|
||||
};
|
||||
|
||||
#define ATH6KL_FW_API2_FILE "fw-2.bin"
|
||||
#define ATH6KL_FW_API3_FILE "fw-3.bin"
|
||||
|
||||
/* AR6003 1.0 definitions */
|
||||
#define AR6003_HW_1_0_VERSION 0x300002ba
|
||||
|
||||
/* AR6003 2.0 definitions */
|
||||
#define AR6003_HW_2_0_VERSION 0x30000384
|
||||
#define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910
|
||||
#define AR6003_HW_2_0_OTP_FILE "ath6k/AR6003/hw2.0/otp.bin.z77"
|
||||
#define AR6003_HW_2_0_FIRMWARE_FILE "ath6k/AR6003/hw2.0/athwlan.bin.z77"
|
||||
#define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "ath6k/AR6003/hw2.0/athtcmd_ram.bin"
|
||||
#define AR6003_HW_2_0_PATCH_FILE "ath6k/AR6003/hw2.0/data.patch.bin"
|
||||
#define AR6003_HW_2_0_FIRMWARE_2_FILE "ath6k/AR6003/hw2.0/fw-2.bin"
|
||||
#define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0"
|
||||
#define AR6003_HW_2_0_OTP_FILE "otp.bin.z77"
|
||||
#define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77"
|
||||
#define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin"
|
||||
#define AR6003_HW_2_0_PATCH_FILE "data.patch.bin"
|
||||
#define AR6003_HW_2_0_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.bin"
|
||||
#define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
|
||||
"ath6k/AR6003/hw2.0/bdata.SD31.bin"
|
||||
|
||||
/* AR6003 3.0 definitions */
|
||||
#define AR6003_HW_2_1_1_VERSION 0x30000582
|
||||
#define AR6003_HW_2_1_1_OTP_FILE "ath6k/AR6003/hw2.1.1/otp.bin"
|
||||
#define AR6003_HW_2_1_1_FIRMWARE_FILE "ath6k/AR6003/hw2.1.1/athwlan.bin"
|
||||
#define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE \
|
||||
"ath6k/AR6003/hw2.1.1/athtcmd_ram.bin"
|
||||
#define AR6003_HW_2_1_1_PATCH_FILE "ath6k/AR6003/hw2.1.1/data.patch.bin"
|
||||
#define AR6003_HW_2_1_1_FIRMWARE_2_FILE "ath6k/AR6003/hw2.1.1/fw-2.bin"
|
||||
#define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1"
|
||||
#define AR6003_HW_2_1_1_OTP_FILE "otp.bin"
|
||||
#define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin"
|
||||
#define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin"
|
||||
#define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin"
|
||||
#define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin"
|
||||
#define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin"
|
||||
#define AR6003_HW_2_1_1_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.bin"
|
||||
#define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \
|
||||
"ath6k/AR6003/hw2.1.1/bdata.SD31.bin"
|
||||
|
||||
/* AR6004 1.0 definitions */
|
||||
#define AR6004_HW_1_0_VERSION 0x30000623
|
||||
#define AR6004_HW_1_0_FIRMWARE_2_FILE "ath6k/AR6004/hw1.0/fw-2.bin"
|
||||
#define AR6004_HW_1_0_FIRMWARE_FILE "ath6k/AR6004/hw1.0/fw.ram.bin"
|
||||
#define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0"
|
||||
#define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin"
|
||||
#define AR6004_HW_1_0_BOARD_DATA_FILE "ath6k/AR6004/hw1.0/bdata.bin"
|
||||
#define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
|
||||
"ath6k/AR6004/hw1.0/bdata.DB132.bin"
|
||||
|
||||
/* AR6004 1.1 definitions */
|
||||
#define AR6004_HW_1_1_VERSION 0x30000001
|
||||
#define AR6004_HW_1_1_FIRMWARE_2_FILE "ath6k/AR6004/hw1.1/fw-2.bin"
|
||||
#define AR6004_HW_1_1_FIRMWARE_FILE "ath6k/AR6004/hw1.1/fw.ram.bin"
|
||||
#define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1"
|
||||
#define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin"
|
||||
#define AR6004_HW_1_1_BOARD_DATA_FILE "ath6k/AR6004/hw1.1/bdata.bin"
|
||||
#define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
|
||||
"ath6k/AR6004/hw1.1/bdata.DB132.bin"
|
||||
@@ -144,6 +152,8 @@ struct ath6kl_fw_ie {
|
||||
#define STA_PS_AWAKE BIT(0)
|
||||
#define STA_PS_SLEEP BIT(1)
|
||||
#define STA_PS_POLLED BIT(2)
|
||||
#define STA_PS_APSD_TRIGGER BIT(3)
|
||||
#define STA_PS_APSD_EOSP BIT(4)
|
||||
|
||||
/* HTC TX packet tagging definitions */
|
||||
#define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED
|
||||
@@ -186,7 +196,7 @@ struct ath6kl_fw_ie {
|
||||
#define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1)
|
||||
#define ATH6KL_CONF_ENABLE_11N BIT(2)
|
||||
#define ATH6KL_CONF_ENABLE_TX_BURST BIT(3)
|
||||
#define ATH6KL_CONF_SUSPEND_CUTPOWER BIT(4)
|
||||
#define ATH6KL_CONF_UART_DEBUG BIT(4)
|
||||
|
||||
enum wlan_low_pwr_state {
|
||||
WLAN_POWER_STATE_ON,
|
||||
@@ -231,14 +241,19 @@ struct rxtid_stats {
|
||||
u32 num_bar;
|
||||
};
|
||||
|
||||
struct aggr_info {
|
||||
struct aggr_info_conn {
|
||||
u8 aggr_sz;
|
||||
u8 timer_scheduled;
|
||||
struct timer_list timer;
|
||||
struct net_device *dev;
|
||||
struct rxtid rx_tid[NUM_OF_TIDS];
|
||||
struct sk_buff_head free_q;
|
||||
struct rxtid_stats stat[NUM_OF_TIDS];
|
||||
struct aggr_info *aggr_info;
|
||||
};
|
||||
|
||||
struct aggr_info {
|
||||
struct aggr_info_conn *aggr_conn;
|
||||
struct sk_buff_head rx_amsdu_freeq;
|
||||
};
|
||||
|
||||
struct ath6kl_wep_key {
|
||||
@@ -280,6 +295,9 @@ struct ath6kl_sta {
|
||||
u8 wpa_ie[ATH6KL_MAX_IE];
|
||||
struct sk_buff_head psq;
|
||||
spinlock_t psq_lock;
|
||||
u8 apsd_info;
|
||||
struct sk_buff_head apsdq;
|
||||
struct aggr_info_conn *aggr_conn;
|
||||
};
|
||||
|
||||
struct ath6kl_version {
|
||||
@@ -408,6 +426,13 @@ enum ath6kl_hif_type {
|
||||
ATH6KL_HIF_TYPE_USB,
|
||||
};
|
||||
|
||||
/* Max number of filters that hw supports */
|
||||
#define ATH6K_MAX_MC_FILTERS_PER_LIST 7
|
||||
struct ath6kl_mc_filter {
|
||||
struct list_head list;
|
||||
char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
|
||||
};
|
||||
|
||||
/*
|
||||
* Driver's maximum limit, note that some firmwares support only one vif
|
||||
* and the runtime (current) limit must be checked from ar->vif_max.
|
||||
@@ -426,6 +451,7 @@ enum ath6kl_vif_state {
|
||||
DTIM_PERIOD_AVAIL,
|
||||
WLAN_ENABLED,
|
||||
STATS_UPDATE_PEND,
|
||||
HOST_SLEEP_MODE_CMD_PROCESSED,
|
||||
};
|
||||
|
||||
struct ath6kl_vif {
|
||||
@@ -471,6 +497,8 @@ struct ath6kl_vif {
|
||||
u8 assoc_bss_dtim_period;
|
||||
struct net_device_stats net_stats;
|
||||
struct target_stats target_stats;
|
||||
|
||||
struct list_head mc_filter;
|
||||
};
|
||||
|
||||
#define WOW_LIST_ID 0
|
||||
@@ -504,6 +532,7 @@ struct ath6kl {
|
||||
struct wiphy *wiphy;
|
||||
|
||||
enum ath6kl_state state;
|
||||
unsigned int testmode;
|
||||
|
||||
struct ath6kl_bmi bmi;
|
||||
const struct ath6kl_hif_ops *hif_ops;
|
||||
@@ -523,7 +552,6 @@ struct ath6kl {
|
||||
spinlock_t lock;
|
||||
struct semaphore sem;
|
||||
u16 listen_intvl_b;
|
||||
u16 listen_intvl_t;
|
||||
u8 lrssi_roam_threshold;
|
||||
struct ath6kl_version version;
|
||||
u32 target_type;
|
||||
@@ -574,17 +602,24 @@ struct ath6kl {
|
||||
u32 board_addr;
|
||||
u32 refclk_hz;
|
||||
u32 uarttx_pin;
|
||||
u32 testscript_addr;
|
||||
|
||||
struct ath6kl_hw_fw {
|
||||
const char *dir;
|
||||
const char *otp;
|
||||
const char *fw;
|
||||
const char *tcmd;
|
||||
const char *patch;
|
||||
const char *utf;
|
||||
const char *testscript;
|
||||
} fw;
|
||||
|
||||
const char *fw_otp;
|
||||
const char *fw;
|
||||
const char *fw_tcmd;
|
||||
const char *fw_patch;
|
||||
const char *fw_api2;
|
||||
const char *fw_board;
|
||||
const char *fw_default_board;
|
||||
} hw;
|
||||
|
||||
u16 conf_flags;
|
||||
u16 suspend_mode;
|
||||
wait_queue_head_t event_wq;
|
||||
struct ath6kl_mbox_info mbox_info;
|
||||
|
||||
@@ -603,6 +638,10 @@ struct ath6kl {
|
||||
u8 *fw_patch;
|
||||
size_t fw_patch_len;
|
||||
|
||||
u8 *fw_testscript;
|
||||
size_t fw_testscript_len;
|
||||
|
||||
unsigned int fw_api;
|
||||
unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
|
||||
|
||||
struct workqueue_struct *ath6kl_wq;
|
||||
@@ -676,7 +715,9 @@ struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
|
||||
void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
|
||||
int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
|
||||
|
||||
struct aggr_info *aggr_init(struct net_device *dev);
|
||||
struct aggr_info *aggr_init(struct ath6kl_vif *vif);
|
||||
void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
|
||||
struct aggr_info_conn *aggr_conn);
|
||||
void ath6kl_rx_refill(struct htc_target *target,
|
||||
enum htc_endpoint_id endpoint);
|
||||
void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
|
||||
@@ -684,7 +725,7 @@ struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
|
||||
enum htc_endpoint_id endpoint,
|
||||
int len);
|
||||
void aggr_module_destroy(struct aggr_info *aggr_info);
|
||||
void aggr_reset_state(struct aggr_info *aggr_info);
|
||||
void aggr_reset_state(struct aggr_info_conn *aggr_conn);
|
||||
|
||||
struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 * node_addr);
|
||||
struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
|
||||
@@ -700,7 +741,7 @@ void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
|
||||
void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
|
||||
void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
|
||||
u8 keymgmt, u8 ucipher, u8 auth,
|
||||
u8 assoc_req_len, u8 *assoc_info);
|
||||
u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
|
||||
void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
|
||||
u8 *bssid, u8 assoc_resp_len,
|
||||
u8 *assoc_info, u16 prot_reason_status);
|
||||
@@ -723,12 +764,18 @@ void ath6kl_wakeup_event(void *dev);
|
||||
void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
|
||||
bool wait_fot_compltn, bool cold_reset);
|
||||
void ath6kl_init_control_info(struct ath6kl_vif *vif);
|
||||
void ath6kl_deinit_if_data(struct ath6kl_vif *vif);
|
||||
void ath6kl_core_free(struct ath6kl *ar);
|
||||
struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
|
||||
void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
|
||||
int ath6kl_init_hw_start(struct ath6kl *ar);
|
||||
int ath6kl_init_hw_stop(struct ath6kl *ar);
|
||||
int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
|
||||
int ath6kl_init_hw_params(struct ath6kl *ar);
|
||||
|
||||
void ath6kl_check_wow_status(struct ath6kl *ar);
|
||||
|
||||
struct ath6kl *ath6kl_core_create(struct device *dev);
|
||||
int ath6kl_core_init(struct ath6kl *ar);
|
||||
void ath6kl_core_cleanup(struct ath6kl *ar);
|
||||
void ath6kl_core_destroy(struct ath6kl *ar);
|
||||
|
||||
#endif /* CORE_H */
|
||||
|
||||
@@ -54,9 +54,42 @@ int ath6kl_printk(const char *level, const char *fmt, ...)
|
||||
|
||||
return rtn;
|
||||
}
|
||||
EXPORT_SYMBOL(ath6kl_printk);
|
||||
|
||||
#ifdef CONFIG_ATH6KL_DEBUG
|
||||
|
||||
void ath6kl_dbg(enum ATH6K_DEBUG_MASK mask, const char *fmt, ...)
|
||||
{
|
||||
struct va_format vaf;
|
||||
va_list args;
|
||||
|
||||
if (!(debug_mask & mask))
|
||||
return;
|
||||
|
||||
va_start(args, fmt);
|
||||
|
||||
vaf.fmt = fmt;
|
||||
vaf.va = &args;
|
||||
|
||||
ath6kl_printk(KERN_DEBUG, "%pV", &vaf);
|
||||
|
||||
va_end(args);
|
||||
}
|
||||
EXPORT_SYMBOL(ath6kl_dbg);
|
||||
|
||||
void ath6kl_dbg_dump(enum ATH6K_DEBUG_MASK mask,
|
||||
const char *msg, const char *prefix,
|
||||
const void *buf, size_t len)
|
||||
{
|
||||
if (debug_mask & mask) {
|
||||
if (msg)
|
||||
ath6kl_dbg(mask, "%s\n", msg);
|
||||
|
||||
print_hex_dump_bytes(prefix, DUMP_PREFIX_OFFSET, buf, len);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(ath6kl_dbg_dump);
|
||||
|
||||
#define REG_OUTPUT_LEN_PER_LINE 25
|
||||
#define REGTYPE_STR_LEN 100
|
||||
|
||||
@@ -82,31 +115,31 @@ void ath6kl_dump_registers(struct ath6kl_device *dev,
|
||||
struct ath6kl_irq_enable_reg *irq_enable_reg)
|
||||
{
|
||||
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY, ("<------- Register Table -------->\n"));
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ, ("<------- Register Table -------->\n"));
|
||||
|
||||
if (irq_proc_reg != NULL) {
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"Host Int status: 0x%x\n",
|
||||
irq_proc_reg->host_int_status);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"CPU Int status: 0x%x\n",
|
||||
irq_proc_reg->cpu_int_status);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"Error Int status: 0x%x\n",
|
||||
irq_proc_reg->error_int_status);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"Counter Int status: 0x%x\n",
|
||||
irq_proc_reg->counter_int_status);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"Mbox Frame: 0x%x\n",
|
||||
irq_proc_reg->mbox_frame);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"Rx Lookahead Valid: 0x%x\n",
|
||||
irq_proc_reg->rx_lkahd_valid);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"Rx Lookahead 0: 0x%x\n",
|
||||
irq_proc_reg->rx_lkahd[0]);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"Rx Lookahead 1: 0x%x\n",
|
||||
irq_proc_reg->rx_lkahd[1]);
|
||||
|
||||
@@ -115,16 +148,16 @@ void ath6kl_dump_registers(struct ath6kl_device *dev,
|
||||
* If the target supports GMBOX hardware, dump some
|
||||
* additional state.
|
||||
*/
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"GMBOX Host Int status 2: 0x%x\n",
|
||||
irq_proc_reg->host_int_status2);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"GMBOX RX Avail: 0x%x\n",
|
||||
irq_proc_reg->gmbox_rx_avail);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"GMBOX lookahead alias 0: 0x%x\n",
|
||||
irq_proc_reg->rx_gmbox_lkahd_alias[0]);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"GMBOX lookahead alias 1: 0x%x\n",
|
||||
irq_proc_reg->rx_gmbox_lkahd_alias[1]);
|
||||
}
|
||||
@@ -132,13 +165,13 @@ void ath6kl_dump_registers(struct ath6kl_device *dev,
|
||||
}
|
||||
|
||||
if (irq_enable_reg != NULL) {
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY,
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ,
|
||||
"Int status Enable: 0x%x\n",
|
||||
irq_enable_reg->int_status_en);
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY, "Counter Int status Enable: 0x%x\n",
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ, "Counter Int status Enable: 0x%x\n",
|
||||
irq_enable_reg->cntr_int_status_en);
|
||||
}
|
||||
ath6kl_dbg(ATH6KL_DBG_ANY, "<------------------------------->\n");
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ, "<------------------------------->\n");
|
||||
}
|
||||
|
||||
static void dump_cred_dist(struct htc_endpoint_credit_dist *ep_dist)
|
||||
@@ -175,9 +208,6 @@ void dump_cred_dist_stats(struct htc_target *target)
|
||||
{
|
||||
struct htc_endpoint_credit_dist *ep_list;
|
||||
|
||||
if (!AR_DBG_LVL_CHECK(ATH6KL_DBG_CREDIT))
|
||||
return;
|
||||
|
||||
list_for_each_entry(ep_list, &target->cred_dist_list, list)
|
||||
dump_cred_dist(ep_list);
|
||||
|
||||
@@ -1411,6 +1441,8 @@ static ssize_t ath6kl_create_qos_write(struct file *file,
|
||||
return -EINVAL;
|
||||
pstream.medium_time = cpu_to_le32(val32);
|
||||
|
||||
pstream.nominal_phy = le32_to_cpu(pstream.min_phy_rate) / 1000000;
|
||||
|
||||
ath6kl_wmi_create_pstream_cmd(ar->wmi, vif->fw_vif_idx, &pstream);
|
||||
|
||||
return count;
|
||||
@@ -1505,57 +1537,46 @@ static const struct file_operations fops_bgscan_int = {
|
||||
};
|
||||
|
||||
static ssize_t ath6kl_listen_int_write(struct file *file,
|
||||
const char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
const char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ath6kl *ar = file->private_data;
|
||||
u16 listen_int_t, listen_int_b;
|
||||
struct ath6kl_vif *vif;
|
||||
u16 listen_interval;
|
||||
char buf[32];
|
||||
char *sptr, *token;
|
||||
ssize_t len;
|
||||
|
||||
vif = ath6kl_vif_first(ar);
|
||||
if (!vif)
|
||||
return -EIO;
|
||||
|
||||
len = min(count, sizeof(buf) - 1);
|
||||
if (copy_from_user(buf, user_buf, len))
|
||||
return -EFAULT;
|
||||
|
||||
buf[len] = '\0';
|
||||
sptr = buf;
|
||||
|
||||
token = strsep(&sptr, " ");
|
||||
if (!token)
|
||||
if (kstrtou16(buf, 0, &listen_interval))
|
||||
return -EINVAL;
|
||||
|
||||
if (kstrtou16(token, 0, &listen_int_t))
|
||||
if ((listen_interval < 1) || (listen_interval > 50))
|
||||
return -EINVAL;
|
||||
|
||||
if (kstrtou16(sptr, 0, &listen_int_b))
|
||||
return -EINVAL;
|
||||
|
||||
if ((listen_int_t < 15) || (listen_int_t > 5000))
|
||||
return -EINVAL;
|
||||
|
||||
if ((listen_int_b < 1) || (listen_int_b > 50))
|
||||
return -EINVAL;
|
||||
|
||||
ar->listen_intvl_t = listen_int_t;
|
||||
ar->listen_intvl_b = listen_int_b;
|
||||
|
||||
ath6kl_wmi_listeninterval_cmd(ar->wmi, 0, ar->listen_intvl_t,
|
||||
ar->listen_intvl_b = listen_interval;
|
||||
ath6kl_wmi_listeninterval_cmd(ar->wmi, vif->fw_vif_idx, 0,
|
||||
ar->listen_intvl_b);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t ath6kl_listen_int_read(struct file *file,
|
||||
char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ath6kl *ar = file->private_data;
|
||||
char buf[32];
|
||||
int len;
|
||||
|
||||
len = scnprintf(buf, sizeof(buf), "%u %u\n", ar->listen_intvl_t,
|
||||
ar->listen_intvl_b);
|
||||
len = scnprintf(buf, sizeof(buf), "%u\n", ar->listen_intvl_b);
|
||||
|
||||
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
|
||||
}
|
||||
@@ -1710,6 +1731,9 @@ int ath6kl_debug_init(struct ath6kl *ar)
|
||||
debugfs_create_file("bgscan_interval", S_IWUSR,
|
||||
ar->debugfs_phy, ar, &fops_bgscan_int);
|
||||
|
||||
debugfs_create_file("listen_interval", S_IRUSR | S_IWUSR,
|
||||
ar->debugfs_phy, ar, &fops_listen_int);
|
||||
|
||||
debugfs_create_file("power_params", S_IWUSR, ar->debugfs_phy, ar,
|
||||
&fops_power_params);
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user