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Merge branch 'x86-nuke-platforms-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Browse Source 
Pull x86 old platform removal from Peter Anvin:
 "This patchset removes support for several completely obsolete
  platforms, where the maintainers either have completely vanished or
  acked the removal.  For some of them it is questionable if there even
  exists functional specimens of the hardware"

Geert Uytterhoeven apparently thought this was a April Fool's pull request ;)

* 'x86-nuke-platforms-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, platforms: Remove NUMAQ
  x86, platforms: Remove SGI Visual Workstation
  x86, apic: Remove support for IBM Summit/EXA chipset
  x86, apic: Remove support for ia32-based Unisys ES7000
This commit is contained in:
Linus Torvalds
2014-04-02 13:15:58 -07:00
parent 7125764c5d b5660ba76b
commit 467cbd207a
47 changed files with 15 additions and 8806 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/00-INDEX
-2
View File
@@ -413,8 +413,6 @@ serial-console.txt
- how to set up Linux with a serial line console as the default.
sgi-ioc4.txt
- description of the SGI IOC4 PCI (multi function) device.
sgi-visws.txt
- short blurb on the SGI Visual Workstations.
sh/
- directory with info on porting Linux to a new architecture.
smsc_ece1099.txt
Documentation/sgi-visws.txt
-13
View File
@@ -1,13 +0,0 @@
The SGI Visual Workstations (models 320 and 540) are based around
the Cobalt, Lithium, and Arsenic ASICs. The Cobalt ASIC is the
main system ASIC which interfaces the 1-4 IA32 cpus, the memory
system, and the I/O system in the Lithium ASIC. The Cobalt ASIC
also contains the 3D gfx rendering engine which renders to main
system memory -- part of which is used as the frame buffer which
is DMA'ed to a video connector using the Arsenic ASIC. A PIIX4
chip and NS87307 are used to provide legacy device support (IDE,
serial, floppy, and parallel).
The Visual Workstation chipset largely conforms to the PC architecture
with some notable exceptions such as interrupt handling.
Documentation/sound/oss/vwsnd
-293
View File
@@ -1,293 +0,0 @@
vwsnd - Sound driver for the Silicon Graphics 320 and 540 Visual
Workstations' onboard audio.
Copyright 1999 Silicon Graphics, Inc. All rights reserved.
At the time of this writing, March 1999, there are two models of
Visual Workstation, the 320 and the 540. This document only describes
those models. Future Visual Workstation models may have different
sound capabilities, and this driver will probably not work on those
boxes.
The Visual Workstation has an Analog Devices AD1843 "SoundComm" audio
codec chip. The AD1843 is accessed through the Cobalt I/O ASIC, also
known as Lithium. This driver programs both chips.
==============================================================================
QUICK CONFIGURATION
# insmod soundcore
# insmod vwsnd
==============================================================================
I/O CONNECTIONS
On the Visual Workstation, only three of the AD1843 inputs are hooked
up. The analog line in jacks are connected to the AD1843's AUX1
input. The CD audio lines are connected to the AD1843's AUX2 input.
The microphone jack is connected to the AD1843's MIC input. The mic
jack is mono, but the signal is delivered to both the left and right
MIC inputs. You can record in stereo from the mic input, but you will
get the same signal on both channels (within the limits of A/D
accuracy). Full scale on the Line input is +/- 2.0 V. Full scale on
the MIC input is 20 dB less, or +/- 0.2 V.
The AD1843's LOUT1 outputs are connected to the Line Out jacks. The
AD1843's HPOUT outputs are connected to the speaker/headphone jack.
LOUT2 is not connected. Line out's maximum level is +/- 2.0 V peak to
peak. The speaker/headphone out's maximum is +/- 4.0 V peak to peak.
The AD1843's PCM input channel and one of its output channels (DAC1)
are connected to Lithium. The other output channel (DAC2) is not
connected.
==============================================================================
CAPABILITIES
The AD1843 has PCM input and output (Pulse Code Modulation, also known
as wavetable). PCM input and output can be mono or stereo in any of
four formats. The formats are 16 bit signed and 8 bit unsigned,
u-Law, and A-Law format. Any sample rate from 4 KHz to 49 KHz is
available, in 1 Hz increments.
The AD1843 includes an analog mixer that can mix all three input
signals (line, mic and CD) into the analog outputs. The mixer has a
separate gain control and mute switch for each input.
There are two outputs, line out and speaker/headphone out. They
always produce the same signal, and the speaker always has 3 dB more
gain than the line out. The speaker/headphone output can be muted,
but this driver does not export that function.
The hardware can sync audio to the video clock, but this driver does
not have a way to specify syncing to video.
==============================================================================
PROGRAMMING
This section explains the API supported by the driver. Also see the
Open Sound Programming Guide at http://www.opensound.com/pguide/ .
This section assumes familiarity with that document.
The driver has two interfaces, an I/O interface and a mixer interface.
There is no MIDI or sequencer capability.
==============================================================================
PROGRAMMING PCM I/O
The I/O interface is usually accessed as /dev/audio or /dev/dsp.
Using the standard Open Sound System (OSS) ioctl calls, the sample
rate, number of channels, and sample format may be set within the
limitations described above. The driver supports triggering. It also
supports getting the input and output pointers with one-sample
accuracy.
The SNDCTL_DSP_GETCAP ioctl returns these capabilities.
DSP_CAP_DUPLEX - driver supports full duplex.
DSP_CAP_TRIGGER - driver supports triggering.
DSP_CAP_REALTIME - values returned by SNDCTL_DSP_GETIPTR
and SNDCTL_DSP_GETOPTR are accurate to a few samples.
Memory mapping (mmap) is not implemented.
The driver permits subdivided fragment sizes from 64 to 4096 bytes.
The number of fragments can be anything from 3 fragments to however
many fragments fit into 124 kilobytes. It is up to the user to
determine how few/small fragments can be used without introducing
glitches with a given workload. Linux is not realtime, so we can't
promise anything. (sigh...)
When this driver is switched into or out of mu-Law or A-Law mode on
output, it may produce an audible click. This is unavoidable. To
prevent clicking, use signed 16-bit mode instead, and convert from
mu-Law or A-Law format in software.
==============================================================================
PROGRAMMING THE MIXER INTERFACE
The mixer interface is usually accessed as /dev/mixer. It is accessed
through ioctls. The mixer allows the application to control gain or
mute several audio signal paths, and also allows selection of the
recording source.
Each of the constants described here can be read using the
MIXER_READ(SOUND_MIXER_xxx) ioctl. Those that are not read-only can
also be written using the MIXER_WRITE(SOUND_MIXER_xxx) ioctl. In most
cases, <sys/soundcard.h> defines constants SOUND_MIXER_READ_xxx and
SOUND_MIXER_WRITE_xxx which work just as well.
SOUND_MIXER_CAPS Read-only
This is a mask of optional driver capabilities that are implemented.
This driver's only capability is SOUND_CAP_EXCL_INPUT, which means
that only one recording source can be active at a time.
SOUND_MIXER_DEVMASK Read-only
This is a mask of the sound channels. This driver's channels are PCM,
LINE, MIC, CD, and RECLEV.
SOUND_MIXER_STEREODEVS Read-only
This is a mask of which sound channels are capable of stereo. All
channels are capable of stereo. (But see caveat on MIC input in I/O
CONNECTIONS section above).
SOUND_MIXER_OUTMASK Read-only
This is a mask of channels that route inputs through to outputs.
Those are LINE, MIC, and CD.
SOUND_MIXER_RECMASK Read-only
This is a mask of channels that can be recording sources. Those are
PCM, LINE, MIC, CD.
SOUND_MIXER_PCM Default: 0x5757 (0 dB)
This is the gain control for PCM output. The left and right channel
gain are controlled independently. This gain control has 64 levels,
which range from -82.5 dB to +12.0 dB in 1.5 dB steps. Those 64
levels are mapped onto 100 levels at the ioctl, see below.
SOUND_MIXER_LINE Default: 0x4a4a (0 dB)
This is the gain control for mixing the Line In source into the
outputs. The left and right channel gain are controlled
independently. This gain control has 32 levels, which range from
-34.5 dB to +12.0 dB in 1.5 dB steps. Those 32 levels are mapped onto
100 levels at the ioctl, see below.
SOUND_MIXER_MIC Default: 0x4a4a (0 dB)
This is the gain control for mixing the MIC source into the outputs.
The left and right channel gain are controlled independently. This
gain control has 32 levels, which range from -34.5 dB to +12.0 dB in
1.5 dB steps. Those 32 levels are mapped onto 100 levels at the
ioctl, see below.
SOUND_MIXER_CD Default: 0x4a4a (0 dB)
This is the gain control for mixing the CD audio source into the
outputs. The left and right channel gain are controlled
independently. This gain control has 32 levels, which range from
-34.5 dB to +12.0 dB in 1.5 dB steps. Those 32 levels are mapped onto
100 levels at the ioctl, see below.
SOUND_MIXER_RECLEV Default: 0 (0 dB)
This is the gain control for PCM input (RECording LEVel). The left
and right channel gain are controlled independently. This gain
control has 16 levels, which range from 0 dB to +22.5 dB in 1.5 dB
steps. Those 16 levels are mapped onto 100 levels at the ioctl, see
below.
SOUND_MIXER_RECSRC Default: SOUND_MASK_LINE
This is a mask of currently selected PCM input sources (RECording
SouRCes). Because the AD1843 can only have a single recording source
at a time, only one bit at a time can be set in this mask. The
allowable values are SOUND_MASK_PCM, SOUND_MASK_LINE, SOUND_MASK_MIC,
or SOUND_MASK_CD. Selecting SOUND_MASK_PCM sets up internal
resampling which is useful for loopback testing and for hardware
sample rate conversion. But software sample rate conversion is
probably faster, so I don't know how useful that is.
SOUND_MIXER_OUTSRC DEFAULT: SOUND_MASK_LINE|SOUND_MASK_MIC|SOUND_MASK_CD
This is a mask of sources that are currently passed through to the
outputs. Those sources whose bits are not set are muted.
==============================================================================
GAIN CONTROL
There are five gain controls listed above. Each has 16, 32, or 64
steps. Each control has 1.5 dB of gain per step. Each control is
stereo.
The OSS defines the argument to a channel gain ioctl as having two
components, left and right, each of which ranges from 0 to 100. The
two components are packed into the same word, with the left side gain
in the least significant byte, and the right side gain in the second
least significant byte. In C, we would say this.
#include <assert.h>
...
assert(leftgain >= 0 && leftgain <= 100);
assert(rightgain >= 0 && rightgain <= 100);
arg = leftgain | rightgain << 8;
So each OSS gain control has 101 steps. But the hardware has 16, 32,
or 64 steps. The hardware steps are spread across the 101 OSS steps
nearly evenly. The conversion formulas are like this, given N equals
16, 32, or 64.
int round = N/2 - 1;
OSS_gain_steps = (hw_gain_steps * 100 + round) / (N - 1);
hw_gain_steps = (OSS_gain_steps * (N - 1) + round) / 100;
Here is a snippet of C code that will return the left and right gain
of any channel in dB. Pass it one of the predefined gain_desc_t
structures to access any of the five channels' gains.
typedef struct gain_desc {
float min_gain;
float gain_step;
int nbits;
int chan;
} gain_desc_t;
const gain_desc_t gain_pcm = { -82.5, 1.5, 6, SOUND_MIXER_PCM };
const gain_desc_t gain_line = { -34.5, 1.5, 5, SOUND_MIXER_LINE };
const gain_desc_t gain_mic = { -34.5, 1.5, 5, SOUND_MIXER_MIC };
const gain_desc_t gain_cd = { -34.5, 1.5, 5, SOUND_MIXER_CD };
const gain_desc_t gain_reclev = { 0.0, 1.5, 4, SOUND_MIXER_RECLEV };
int get_gain_dB(int fd, const gain_desc_t *gp,
float *left, float *right)
{
int word;
int lg, rg;
int mask = (1 << gp->nbits) - 1;
if (ioctl(fd, MIXER_READ(gp->chan), &word) != 0)
return -1; /* fail */
lg = word & 0xFF;
rg = word >> 8 & 0xFF;
lg = (lg * mask + mask / 2) / 100;
rg = (rg * mask + mask / 2) / 100;
*left = gp->min_gain + gp->gain_step * lg;
*right = gp->min_gain + gp->gain_step * rg;
return 0;
}
And here is the corresponding routine to set a channel's gain in dB.
int set_gain_dB(int fd, const gain_desc_t *gp, float left, float right)
{
float max_gain =
gp->min_gain + (1 << gp->nbits) * gp->gain_step;
float round = gp->gain_step / 2;
int mask = (1 << gp->nbits) - 1;
int word;
int lg, rg;
if (left < gp->min_gain || right < gp->min_gain)
return EINVAL;
lg = (left - gp->min_gain + round) / gp->gain_step;
rg = (right - gp->min_gain + round) / gp->gain_step;
if (lg >= (1 << gp->nbits) || rg >= (1 << gp->nbits))
return EINVAL;
lg = (100 * lg + mask / 2) / mask;
rg = (100 * rg + mask / 2) / mask;
word = lg | rg << 8;
return ioctl(fd, MIXER_WRITE(gp->chan), &word);
}
MAINTAINERS
-7
View File
@@ -7840,13 +7840,6 @@ F: Documentation/ia64/serial.txt
F: drivers/tty/serial/ioc?_serial.c
F: include/linux/ioc?.h
SGI VISUAL WORKSTATION 320 AND 540
M: Andrey Panin <pazke@donpac.ru>
L: linux-visws-devel@lists.sf.net
W: http://linux-visws.sf.net
S: Maintained for 2.6.
F: Documentation/sgi-visws.txt
SGI XP/XPC/XPNET DRIVER
M: Cliff Whickman <cpw@sgi.com>
M: Robin Holt <robinmholt@gmail.com>
arch/x86/Kconfig
+9 -73
View File
@@ -344,12 +344,9 @@ config X86_EXTENDED_PLATFORM
for the following (non-PC) 32 bit x86 platforms:
Goldfish (Android emulator)
AMD Elan
NUMAQ (IBM/Sequent)
RDC R-321x SoC
SGI 320/540 (Visual Workstation)
STA2X11-based (e.g. Northville)
Summit/EXA (IBM x440)
Unisys ES7000 IA32 series
Moorestown MID devices
If you have one of these systems, or if you want to build a
@@ -487,49 +484,22 @@ config X86_32_NON_STANDARD
depends on X86_32 && SMP
depends on X86_EXTENDED_PLATFORM
---help---
This option compiles in the NUMAQ, Summit, bigsmp, ES7000,
STA2X11, default subarchitectures. It is intended for a generic
binary kernel. If you select them all, kernel will probe it
one by one and will fallback to default.
This option compiles in the bigsmp and STA2X11 default
subarchitectures. It is intended for a generic binary
kernel. If you select them all, kernel will probe it one by
one and will fallback to default.
# Alphabetically sorted list of Non standard 32 bit platforms
config X86_NUMAQ
bool "NUMAQ (IBM/Sequent)"
depends on X86_32_NON_STANDARD
depends on PCI
select NUMA
select X86_MPPARSE
---help---
This option is used for getting Linux to run on a NUMAQ (IBM/Sequent)
NUMA multiquad box. This changes the way that processors are
bootstrapped, and uses Clustered Logical APIC addressing mode instead
of Flat Logical. You will need a new lynxer.elf file to flash your
firmware with - send email to <Martin.Bligh@us.ibm.com>.
config X86_SUPPORTS_MEMORY_FAILURE
def_bool y
# MCE code calls memory_failure():
depends on X86_MCE
# On 32-bit this adds too big of NODES_SHIFT and we run out of page flags:
depends on !X86_NUMAQ
# On 32-bit SPARSEMEM adds too big of SECTIONS_WIDTH:
depends on X86_64 || !SPARSEMEM
select ARCH_SUPPORTS_MEMORY_FAILURE
config X86_VISWS
bool "SGI 320/540 (Visual Workstation)"
depends on X86_32 && PCI && X86_MPPARSE && PCI_GODIRECT
depends on X86_32_NON_STANDARD
---help---
The SGI Visual Workstation series is an IA32-based workstation
based on SGI systems chips with some legacy PC hardware attached.
Say Y here to create a kernel to run on the SGI 320 or 540.
A kernel compiled for the Visual Workstation will run on general
PCs as well. See <file:Documentation/sgi-visws.txt> for details.
config STA2X11
bool "STA2X11 Companion Chip Support"
depends on X86_32_NON_STANDARD && PCI
@@ -546,20 +516,6 @@ config STA2X11
option is selected the kernel will still be able to boot on
standard PC machines.
config X86_SUMMIT
bool "Summit/EXA (IBM x440)"
depends on X86_32_NON_STANDARD
---help---
This option is needed for IBM systems that use the Summit/EXA chipset.
In particular, it is needed for the x440.
config X86_ES7000
bool "Unisys ES7000 IA32 series"
depends on X86_32_NON_STANDARD && X86_BIGSMP
---help---
Support for Unisys ES7000 systems. Say 'Y' here if this kernel is
supposed to run on an IA32-based Unisys ES7000 system.
config X86_32_IRIS
tristate "Eurobraille/Iris poweroff module"
depends on X86_32
@@ -682,14 +638,6 @@ config MEMTEST
memtest=4, mean do 4 test patterns.
If you are unsure how to answer this question, answer N.
config X86_SUMMIT_NUMA
def_bool y
depends on X86_32 && NUMA && X86_32_NON_STANDARD
config X86_CYCLONE_TIMER
def_bool y
depends on X86_SUMMIT
source "arch/x86/Kconfig.cpu"
config HPET_TIMER
@@ -818,7 +766,7 @@ config NR_CPUS
range 2 8192 if SMP && !MAXSMP && CPUMASK_OFFSTACK && X86_64
default "1" if !SMP
default "8192" if MAXSMP
default "32" if SMP && (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP || X86_ES7000)
default "32" if SMP && X86_BIGSMP
default "8" if SMP
---help---
This allows you to specify the maximum number of CPUs which this
@@ -882,10 +830,6 @@ config X86_IO_APIC
def_bool y
depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC || PCI_MSI
config X86_VISWS_APIC
def_bool y
depends on X86_32 && X86_VISWS
config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
bool "Reroute for broken boot IRQs"
depends on X86_IO_APIC
@@ -1103,13 +1047,11 @@ config X86_CPUID
choice
prompt "High Memory Support"
default HIGHMEM64G if X86_NUMAQ
default HIGHMEM4G
depends on X86_32
config NOHIGHMEM
bool "off"
depends on !X86_NUMAQ
---help---
Linux can use up to 64 Gigabytes of physical memory on x86 systems.
However, the address space of 32-bit x86 processors is only 4
@@ -1146,7 +1088,6 @@ config NOHIGHMEM
config HIGHMEM4G
bool "4GB"
depends on !X86_NUMAQ
---help---
Select this if you have a 32-bit processor and between 1 and 4
gigabytes of physical RAM.
@@ -1238,8 +1179,8 @@ config DIRECT_GBPAGES
config NUMA
bool "Numa Memory Allocation and Scheduler Support"
depends on SMP
depends on X86_64 || (X86_32 && HIGHMEM64G && (X86_NUMAQ || X86_BIGSMP || X86_SUMMIT && ACPI))
default y if (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP)
depends on X86_64 || (X86_32 && HIGHMEM64G && X86_BIGSMP)
default y if X86_BIGSMP
---help---
Enable NUMA (Non Uniform Memory Access) support.
@@ -1250,15 +1191,11 @@ config NUMA
For 64-bit this is recommended if the system is Intel Core i7
(or later), AMD Opteron, or EM64T NUMA.
For 32-bit this is only needed on (rare) 32-bit-only platforms
that support NUMA topologies, such as NUMAQ / Summit, or if you
boot a 32-bit kernel on a 64-bit NUMA platform.
For 32-bit this is only needed if you boot a 32-bit
kernel on a 64-bit NUMA platform.
Otherwise, you should say N.
comment "NUMA (Summit) requires SMP, 64GB highmem support, ACPI"
depends on X86_32 && X86_SUMMIT && (!HIGHMEM64G || !ACPI)
config AMD_NUMA
def_bool y
prompt "Old style AMD Opteron NUMA detection"
@@ -1300,7 +1237,6 @@ config NODES_SHIFT
range 1 10
default "10" if MAXSMP
default "6" if X86_64
default "4" if X86_NUMAQ
default "3"
depends on NEED_MULTIPLE_NODES
---help---
arch/x86/Kconfig.cpu
+1 -1
View File
@@ -359,7 +359,7 @@ config X86_P6_NOP
config X86_TSC
def_bool y
depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) && !X86_NUMAQ) || X86_64
depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
config X86_CMPXCHG64
def_bool y
arch/x86/include/asm/fixmap.h
-6
View File
@@ -89,12 +89,6 @@ enum fixed_addresses {
#ifdef CONFIG_X86_IO_APIC
FIX_IO_APIC_BASE_0,
FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1,
#endif
#ifdef CONFIG_X86_VISWS_APIC
FIX_CO_CPU, /* Cobalt timer */
FIX_CO_APIC, /* Cobalt APIC Redirection Table */
FIX_LI_PCIA, /* Lithium PCI Bridge A */
FIX_LI_PCIB, /* Lithium PCI Bridge B */
#endif
FIX_RO_IDT, /* Virtual mapping for read-only IDT */
#ifdef CONFIG_X86_32
arch/x86/include/asm/hw_irq.h
-1
View File
@@ -98,7 +98,6 @@ extern void trace_call_function_single_interrupt(void);
#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs))
extern unsigned long io_apic_irqs;
extern void init_VISWS_APIC_irqs(void);
extern void setup_IO_APIC(void);
extern void disable_IO_APIC(void);
arch/x86/include/asm/mmzone_32.h
-3
View File
@@ -11,9 +11,6 @@
#ifdef CONFIG_NUMA
extern struct pglist_data *node_data[];
#define NODE_DATA(nid) (node_data[nid])
#include <asm/numaq.h>
#endif /* CONFIG_NUMA */
#ifdef CONFIG_DISCONTIGMEM
arch/x86/include/asm/mpspec.h
-6
View File
@@ -25,12 +25,6 @@ extern int pic_mode;
extern unsigned int def_to_bigsmp;
#ifdef CONFIG_X86_NUMAQ
extern int mp_bus_id_to_node[MAX_MP_BUSSES];
extern int mp_bus_id_to_local[MAX_MP_BUSSES];
extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
#endif
#else /* CONFIG_X86_64: */
#define MAX_MP_BUSSES 256
arch/x86/include/asm/numaq.h
-171
View File
@@ -1,171 +0,0 @@
/*
* Written by: Patricia Gaughen, IBM Corporation
*
* Copyright (C) 2002, IBM Corp.
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Send feedback to <gone@us.ibm.com>
*/
#ifndef _ASM_X86_NUMAQ_H
#define _ASM_X86_NUMAQ_H
#ifdef CONFIG_X86_NUMAQ
extern int found_numaq;
extern int numaq_numa_init(void);
extern int pci_numaq_init(void);
extern void *xquad_portio;
#define XQUAD_PORTIO_BASE 0xfe400000
#define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */
#define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
/*
* SYS_CFG_DATA_PRIV_ADDR, struct eachquadmem, and struct sys_cfg_data are the
*/
#define SYS_CFG_DATA_PRIV_ADDR 0x0009d000 /* place for scd in private
quad space */
/*
* Communication area for each processor on lynxer-processor tests.
*
* NOTE: If you change the size of this eachproc structure you need
* to change the definition for EACH_QUAD_SIZE.
*/
struct eachquadmem {
unsigned int priv_mem_start; /* Starting address of this */
/* quad's private memory. */
/* This is always 0. */
/* In MB. */
unsigned int priv_mem_size; /* Size of this quad's */
/* private memory. */
/* In MB. */
unsigned int low_shrd_mem_strp_start;/* Starting address of this */
/* quad's low shared block */
/* (untranslated). */
/* In MB. */
unsigned int low_shrd_mem_start; /* Starting address of this */
/* quad's low shared memory */
/* (untranslated). */
/* In MB. */
unsigned int low_shrd_mem_size; /* Size of this quad's low */
/* shared memory. */
/* In MB. */
unsigned int lmmio_copb_start; /* Starting address of this */
/* quad's local memory */
/* mapped I/O in the */
/* compatibility OPB. */
/* In MB. */
unsigned int lmmio_copb_size; /* Size of this quad's local */
/* memory mapped I/O in the */
/* compatibility OPB. */
/* In MB. */
unsigned int lmmio_nopb_start; /* Starting address of this */
/* quad's local memory */
/* mapped I/O in the */
/* non-compatibility OPB. */
/* In MB. */
unsigned int lmmio_nopb_size; /* Size of this quad's local */
/* memory mapped I/O in the */
/* non-compatibility OPB. */
/* In MB. */
unsigned int io_apic_0_start; /* Starting address of I/O */
/* APIC 0. */
unsigned int io_apic_0_sz; /* Size I/O APIC 0. */
unsigned int io_apic_1_start; /* Starting address of I/O */
/* APIC 1. */
unsigned int io_apic_1_sz; /* Size I/O APIC 1. */
unsigned int hi_shrd_mem_start; /* Starting address of this */
/* quad's high shared memory.*/
/* In MB. */
unsigned int hi_shrd_mem_size; /* Size of this quad's high */
/* shared memory. */
/* In MB. */
unsigned int mps_table_addr; /* Address of this quad's */
/* MPS tables from BIOS, */
/* in system space.*/
unsigned int lcl_MDC_pio_addr; /* Port-I/O address for */
/* local access of MDC. */
unsigned int rmt_MDC_mmpio_addr; /* MM-Port-I/O address for */
/* remote access of MDC. */
unsigned int mm_port_io_start; /* Starting address of this */
/* quad's memory mapped Port */
/* I/O space. */
unsigned int mm_port_io_size; /* Size of this quad's memory*/
/* mapped Port I/O space. */
unsigned int mm_rmt_io_apic_start; /* Starting address of this */
/* quad's memory mapped */
/* remote I/O APIC space. */
unsigned int mm_rmt_io_apic_size; /* Size of this quad's memory*/
/* mapped remote I/O APIC */
/* space. */
unsigned int mm_isa_start; /* Starting address of this */
/* quad's memory mapped ISA */
/* space (contains MDC */
/* memory space). */
unsigned int mm_isa_size; /* Size of this quad's memory*/
/* mapped ISA space (contains*/
/* MDC memory space). */
unsigned int rmt_qmi_addr; /* Remote addr to access QMI.*/
unsigned int lcl_qmi_addr; /* Local addr to access QMI. */
};
/*
* Note: This structure must be NOT be changed unless the multiproc and
* OS are changed to reflect the new structure.
*/
struct sys_cfg_data {
unsigned int quad_id;
unsigned int bsp_proc_id; /* Boot Strap Processor in this quad. */
unsigned int scd_version; /* Version number of this table. */
unsigned int first_quad_id;
unsigned int quads_present31_0; /* 1 bit for each quad */
unsigned int quads_present63_32; /* 1 bit for each quad */
unsigned int config_flags;
unsigned int boot_flags;
unsigned int csr_start_addr; /* Absolute value (not in MB) */
unsigned int csr_size; /* Absolute value (not in MB) */
unsigned int lcl_apic_start_addr; /* Absolute value (not in MB) */
unsigned int lcl_apic_size; /* Absolute value (not in MB) */
unsigned int low_shrd_mem_base; /* 0 or 512MB or 1GB */
unsigned int low_shrd_mem_quad_offset; /* 0,128M,256M,512M,1G */
/* may not be totally populated */
unsigned int split_mem_enbl; /* 0 for no low shared memory */
unsigned int mmio_sz; /* Size of total system memory mapped I/O */
/* (in MB). */
unsigned int quad_spin_lock; /* Spare location used for quad */
/* bringup. */
unsigned int nonzero55; /* For checksumming. */
unsigned int nonzeroaa; /* For checksumming. */
unsigned int scd_magic_number;
unsigned int system_type;
unsigned int checksum;
/*
* memory configuration area for each quad
*/
struct eachquadmem eq[MAX_NUMNODES]; /* indexed by quad id */
};
void numaq_tsc_disable(void);
#endif /* CONFIG_X86_NUMAQ */
#endif /* _ASM_X86_NUMAQ_H */
arch/x86/include/asm/setup.h
-6
View File
@@ -39,12 +39,6 @@ static inline void vsmp_init(void) { }
void setup_bios_corruption_check(void);
#ifdef CONFIG_X86_VISWS
extern void visws_early_detect(void);
#else
static inline void visws_early_detect(void) { }
#endif
extern unsigned long saved_video_mode;
extern void reserve_standard_io_resources(void);
arch/x86/include/asm/visws/cobalt.h
-127
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@@ -1,127 +0,0 @@
#ifndef _ASM_X86_VISWS_COBALT_H
#define _ASM_X86_VISWS_COBALT_H
#include <asm/fixmap.h>
/*
* Cobalt SGI Visual Workstation system ASIC
*/
#define CO_CPU_NUM_PHYS 0x1e00
#define CO_CPU_TAB_PHYS (CO_CPU_NUM_PHYS + 2)
#define CO_CPU_MAX 4
#define CO_CPU_PHYS 0xc2000000
#define CO_APIC_PHYS 0xc4000000
/* see set_fixmap() and asm/fixmap.h */
#define CO_CPU_VADDR (fix_to_virt(FIX_CO_CPU))
#define CO_APIC_VADDR (fix_to_virt(FIX_CO_APIC))
/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */
#define CO_CPU_REV 0x08
#define CO_CPU_CTRL 0x10
#define CO_CPU_STAT 0x20
#define CO_CPU_TIMEVAL 0x30
/* CO_CPU_CTRL bits */
#define CO_CTRL_TIMERUN 0x04 /* 0 == disabled */
#define CO_CTRL_TIMEMASK 0x08 /* 0 == unmasked */
/* CO_CPU_STATUS bits */
#define CO_STAT_TIMEINTR 0x02 /* (r) 1 == int pend, (w) 0 == clear */
/* CO_CPU_TIMEVAL value */
#define CO_TIME_HZ 100000000 /* Cobalt core rate */
/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */
#define CO_APIC_HI(n) (((n) * 0x10) + 4)
#define CO_APIC_LO(n) ((n) * 0x10)
#define CO_APIC_ID 0x0ffc
/* CO_APIC_ID bits */
#define CO_APIC_ENABLE 0x00000100
/* CO_APIC_LO bits */
#define CO_APIC_MASK 0x00010000 /* 0 = enabled */
#define CO_APIC_LEVEL 0x00008000 /* 0 = edge */
/*
* Where things are physically wired to Cobalt
* #defines with no board _<type>_<rev>_ are common to all (thus far)
*/
#define CO_APIC_IDE0 4
#define CO_APIC_IDE1 2 /* Only on 320 */
#define CO_APIC_8259 12 /* serial, floppy, par-l-l */
/* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */
#define CO_APIC_PCIA_BASE0 0 /* and 1 */ /* slot 0, line 0 */
#define CO_APIC_PCIA_BASE123 5 /* and 6 */ /* slot 0, line 1 */
#define CO_APIC_PIIX4_USB 7 /* this one is weird */
/* Lithium PCI Bridge B -- "the one with PIIX4" */
#define CO_APIC_PCIB_BASE0 8 /* and 9-12 *//* slot 0, line 0 */
#define CO_APIC_PCIB_BASE123 13 /* 14.15 */ /* slot 0, line 1 */
#define CO_APIC_VIDOUT0 16
#define CO_APIC_VIDOUT1 17
#define CO_APIC_VIDIN0 18
#define CO_APIC_VIDIN1 19
#define CO_APIC_LI_AUDIO 22
#define CO_APIC_AS 24
#define CO_APIC_RE 25
#define CO_APIC_CPU 28 /* Timer and Cache interrupt */
#define CO_APIC_NMI 29
#define CO_APIC_LAST CO_APIC_NMI
/*
* This is how irqs are assigned on the Visual Workstation.
* Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU).
* All other devices (including PCI) go to Cobalt and are irq's 16 on up.
*/
#define CO_IRQ_APIC0 16 /* irq of apic entry 0 */
#define IS_CO_APIC(irq) ((irq) >= CO_IRQ_APIC0)
#define CO_IRQ(apic) (CO_IRQ_APIC0 + (apic)) /* apic ent to irq */
#define CO_APIC(irq) ((irq) - CO_IRQ_APIC0) /* irq to apic ent */
#define CO_IRQ_IDE0 14 /* knowledge of... */
#define CO_IRQ_IDE1 15 /* ... ide driver defaults! */
#define CO_IRQ_8259 CO_IRQ(CO_APIC_8259)
#ifdef CONFIG_X86_VISWS_APIC
static inline void co_cpu_write(unsigned long reg, unsigned long v)
{
*((volatile unsigned long *)(CO_CPU_VADDR+reg))=v;
}
static inline unsigned long co_cpu_read(unsigned long reg)
{
return *((volatile unsigned long *)(CO_CPU_VADDR+reg));
}
static inline void co_apic_write(unsigned long reg, unsigned long v)
{
*((volatile unsigned long *)(CO_APIC_VADDR+reg))=v;
}
static inline unsigned long co_apic_read(unsigned long reg)
{
return *((volatile unsigned long *)(CO_APIC_VADDR+reg));
}
#endif
extern char visws_board_type;
#define VISWS_320 0
#define VISWS_540 1
extern char visws_board_rev;
extern int pci_visws_init(void);
#endif /* _ASM_X86_VISWS_COBALT_H */
arch/x86/include/asm/visws/lithium.h
-53
View File
@@ -1,53 +0,0 @@
#ifndef _ASM_X86_VISWS_LITHIUM_H
#define _ASM_X86_VISWS_LITHIUM_H
#include <asm/fixmap.h>
/*
* Lithium is the SGI Visual Workstation I/O ASIC
*/
#define LI_PCI_A_PHYS 0xfc000000 /* Enet is dev 3 */
#define LI_PCI_B_PHYS 0xfd000000 /* PIIX4 is here */
/* see set_fixmap() and asm/fixmap.h */
#define LI_PCIA_VADDR (fix_to_virt(FIX_LI_PCIA))
#define LI_PCIB_VADDR (fix_to_virt(FIX_LI_PCIB))
/* Not a standard PCI? (not in linux/pci.h) */
#define LI_PCI_BUSNUM 0x44 /* lo8: primary, hi8: sub */
#define LI_PCI_INTEN 0x46
/* LI_PCI_INTENT bits */
#define LI_INTA_0 0x0001
#define LI_INTA_1 0x0002
#define LI_INTA_2 0x0004
#define LI_INTA_3 0x0008
#define LI_INTA_4 0x0010
#define LI_INTB 0x0020
#define LI_INTC 0x0040
#define LI_INTD 0x0080
/* More special purpose macros... */
static inline void li_pcia_write16(unsigned long reg, unsigned short v)
{
*((volatile unsigned short *)(LI_PCIA_VADDR+reg))=v;
}
static inline unsigned short li_pcia_read16(unsigned long reg)
{
return *((volatile unsigned short *)(LI_PCIA_VADDR+reg));
}
static inline void li_pcib_write16(unsigned long reg, unsigned short v)
{
*((volatile unsigned short *)(LI_PCIB_VADDR+reg))=v;
}
static inline unsigned short li_pcib_read16(unsigned long reg)
{
return *((volatile unsigned short *)(LI_PCIB_VADDR+reg));
}
#endif /* _ASM_X86_VISWS_LITHIUM_H */
arch/x86/include/asm/visws/piix4.h
-107
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@@ -1,107 +0,0 @@
#ifndef _ASM_X86_VISWS_PIIX4_H
#define _ASM_X86_VISWS_PIIX4_H
/*
* PIIX4 as used on SGI Visual Workstations
*/
#define PIIX_PM_START 0x0F80
#define SIO_GPIO_START 0x0FC0
#define SIO_PM_START 0x0FC8
#define PMBASE PIIX_PM_START
#define GPIREG0 (PMBASE+0x30)
#define GPIREG(x) (GPIREG0+((x)/8))
#define GPIBIT(x) (1 << ((x)%8))
#define PIIX_GPI_BD_ID1 18
#define PIIX_GPI_BD_ID2 19
#define PIIX_GPI_BD_ID3 20
#define PIIX_GPI_BD_ID4 21
#define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1)
#define PIIX_GPI_BD_MASK (GPIBIT(PIIX_GPI_BD_ID1) | \
GPIBIT(PIIX_GPI_BD_ID2) | \
GPIBIT(PIIX_GPI_BD_ID3) | \
GPIBIT(PIIX_GPI_BD_ID4) )
#define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8)
#define SIO_INDEX 0x2e
#define SIO_DATA 0x2f
#define SIO_DEV_SEL 0x7
#define SIO_DEV_ENB 0x30
#define SIO_DEV_MSB 0x60
#define SIO_DEV_LSB 0x61
#define SIO_GP_DEV 0x7
#define SIO_GP_BASE SIO_GPIO_START
#define SIO_GP_MSB (SIO_GP_BASE>>8)
#define SIO_GP_LSB (SIO_GP_BASE&0xff)
#define SIO_GP_DATA1 (SIO_GP_BASE+0)
#define SIO_PM_DEV 0x8
#define SIO_PM_BASE SIO_PM_START
#define SIO_PM_MSB (SIO_PM_BASE>>8)
#define SIO_PM_LSB (SIO_PM_BASE&0xff)
#define SIO_PM_INDEX (SIO_PM_BASE+0)
#define SIO_PM_DATA (SIO_PM_BASE+1)
#define SIO_PM_FER2 0x1
#define SIO_PM_GP_EN 0x80
/*
* This is the dev/reg where generating a config cycle will
* result in a PCI special cycle.
*/
#define SPECIAL_DEV 0xff
#define SPECIAL_REG 0x00
/*
* PIIX4 needs to see a special cycle with the following data
* to be convinced the processor has gone into the stop grant
* state. PIIX4 insists on seeing this before it will power
* down a system.
*/
#define PIIX_SPECIAL_STOP 0x00120002
#define PIIX4_RESET_PORT 0xcf9
#define PIIX4_RESET_VAL 0x6
#define PMSTS_PORT 0xf80 // 2 bytes PM Status
#define PMEN_PORT 0xf82 // 2 bytes PM Enable
#define PMCNTRL_PORT 0xf84 // 2 bytes PM Control
#define PM_SUSPEND_ENABLE 0x2000 // start sequence to suspend state
/*
* PMSTS and PMEN I/O bit definitions.
* (Bits are the same in both registers)
*/
#define PM_STS_RSM (1<<15) // Resume Status
#define PM_STS_PWRBTNOR (1<<11) // Power Button Override
#define PM_STS_RTC (1<<10) // RTC status
#define PM_STS_PWRBTN (1<<8) // Power Button Pressed?
#define PM_STS_GBL (1<<5) // Global Status
#define PM_STS_BM (1<<4) // Bus Master Status
#define PM_STS_TMROF (1<<0) // Timer Overflow Status.
/*
* Stop clock GPI register
*/
#define PIIX_GPIREG0 (0xf80 + 0x30)
/*
* Stop clock GPI bit in GPIREG0
*/
#define PIIX_GPI_STPCLK 0x4 // STPCLK signal routed back in
#endif /* _ASM_X86_VISWS_PIIX4_H */
arch/x86/include/asm/visws/sgivw.h
-5
View File
@@ -1,5 +0,0 @@
/*
* Frame buffer position and size:
*/
extern unsigned long sgivwfb_mem_phys;
extern unsigned long sgivwfb_mem_size;
arch/x86/kernel/acpi/boot.c
-12
View File
@@ -903,10 +903,6 @@ static int __init acpi_parse_madt_lapic_entries(void)
#ifdef CONFIG_X86_IO_APIC
#define MP_ISA_BUS 0
#ifdef CONFIG_X86_ES7000
extern int es7000_plat;
#endif
void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
{
int ioapic;
@@ -956,14 +952,6 @@ void __init mp_config_acpi_legacy_irqs(void)
set_bit(MP_ISA_BUS, mp_bus_not_pci);
pr_debug("Bus #%d is ISA\n", MP_ISA_BUS);
#ifdef CONFIG_X86_ES7000
/*
* Older generations of ES7000 have no legacy identity mappings
*/
if (es7000_plat == 1)
return;
#endif
/*
* Use the default configuration for the IRQs 0-15. Unless
* overridden by (MADT) interrupt source override entries.
arch/x86/kernel/apic/Makefile
-3
View File
@@ -18,10 +18,7 @@ obj-y += apic_flat_64.o
endif
# APIC probe will depend on the listing order here
obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
obj-$(CONFIG_X86_SUMMIT) += summit_32.o
obj-$(CONFIG_X86_BIGSMP) += bigsmp_32.o
obj-$(CONFIG_X86_ES7000) += es7000_32.o
# For 32bit, probe_32 need to be listed last
obj-$(CONFIG_X86_LOCAL_APIC) += probe_$(BITS).o
arch/x86/kernel/apic/apic.c
-1
View File
@@ -2136,7 +2136,6 @@ int generic_processor_info(int apicid, int version)
*
* - arch/x86/kernel/mpparse.c: MP_processor_info()
* - arch/x86/mm/amdtopology.c: amd_numa_init()
* - arch/x86/platform/visws/visws_quirks.c: MP_processor_info()
*
* This function is executed with the modified
* boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
arch/x86/kernel/apic/es7000_32.c
-738
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