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Merge tag 'wireless-drivers-next-for-davem-2015-04-01' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next
Kalle Valo says: ==================== Major changes: ath9k: * add Active Interference Cancellation, a method implemented in the HW to counter WLAN RX > sensitivity degradation when BT is transmitting at the same time. This feature is supported by cards like WB222 based on AR9462. iwlwifi: * Location Aware Regulatory was added by Arik * 8000 device family work * update to the BT Coex firmware API brmcfmac: * add new BCM43455 and BCM43457 SDIO device support * add new BCM43430 SDIO device support wil6210: * take care of AP bridging * fix NAPI behavior * found approach to achieve 4*n+2 alignment of Rx frames rt2x00: * add new rt2800usb device DWA 130 rtlwifi: * add USB ID for D-Link DWA-131 * add USB ID ASUS N10 WiFi dongle mwifiex: * throughput enhancements ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
@@ -1,6 +1,6 @@
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config BCMA_POSSIBLE
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bool
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depends on HAS_IOMEM && HAS_DMA && PCI
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depends on HAS_IOMEM && HAS_DMA
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default y
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menu "Broadcom specific AMBA"
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@@ -45,9 +45,9 @@ config BCMA_HOST_SOC
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If unsure, say N
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# TODO: make it depend on PCI when ready
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config BCMA_DRIVER_PCI
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bool
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bool "BCMA Broadcom PCI core driver"
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depends on BCMA && PCI
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default y
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help
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BCMA bus may have many versions of PCIe core. This driver
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@@ -106,15 +106,35 @@ static inline void __exit bcma_host_soc_unregister_driver(void)
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#endif /* CONFIG_BCMA_HOST_SOC && CONFIG_OF */
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/* driver_pci.c */
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#ifdef CONFIG_BCMA_DRIVER_PCI
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u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
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void bcma_core_pci_early_init(struct bcma_drv_pci *pc);
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void bcma_core_pci_init(struct bcma_drv_pci *pc);
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void bcma_core_pci_up(struct bcma_drv_pci *pc);
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void bcma_core_pci_down(struct bcma_drv_pci *pc);
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#else
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static inline void bcma_core_pci_early_init(struct bcma_drv_pci *pc)
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{
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WARN_ON(pc->core->bus->hosttype == BCMA_HOSTTYPE_PCI);
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}
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static inline void bcma_core_pci_init(struct bcma_drv_pci *pc)
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{
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/* Initialization is required for PCI hosted bus */
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WARN_ON(pc->core->bus->hosttype == BCMA_HOSTTYPE_PCI);
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}
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#endif
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/* driver_pcie2.c */
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#ifdef CONFIG_BCMA_DRIVER_PCI
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void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
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void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2);
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#else
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static inline void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
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{
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/* Initialization is required for PCI hosted bus */
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WARN_ON(pcie2->core->bus->hosttype == BCMA_HOSTTYPE_PCI);
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}
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#endif
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extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
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@@ -17,6 +17,8 @@
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#include "bcma_private.h"
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#define BCMA_GPIO_MAX_PINS 32
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static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
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{
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return container_of(chip, struct bcma_drv_cc, gpio);
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@@ -204,6 +206,7 @@ static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
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int bcma_gpio_init(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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struct gpio_chip *chip = &cc->gpio;
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int err;
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@@ -222,7 +225,7 @@ int bcma_gpio_init(struct bcma_drv_cc *cc)
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if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
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chip->of_node = cc->core->dev.of_node;
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#endif
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switch (cc->core->bus->chipinfo.id) {
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM53572:
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chip->ngpio = 32;
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@@ -231,13 +234,17 @@ int bcma_gpio_init(struct bcma_drv_cc *cc)
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chip->ngpio = 16;
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}
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/* There is just one SoC in one device and its GPIO addresses should be
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* deterministic to address them more easily. The other buses could get
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* a random base number. */
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if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
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chip->base = 0;
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else
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chip->base = -1;
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/*
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* On MIPS we register GPIO devices (LEDs, buttons) using absolute GPIO
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* pin numbers. We don't have Device Tree there and we can't really use
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* relative (per chip) numbers.
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* So let's use predictable base for BCM47XX and "random" for all other.
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*/
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#if IS_BUILTIN(CONFIG_BCM47XX)
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chip->base = bus->num * BCMA_GPIO_MAX_PINS;
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#else
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chip->base = -1;
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#endif
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err = bcma_gpio_irq_domain_init(cc);
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if (err)
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@@ -282,39 +282,6 @@ void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
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int bcma_core_pci_irq_ctl(struct bcma_bus *bus, struct bcma_device *core,
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bool enable)
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{
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struct pci_dev *pdev;
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u32 coremask, tmp;
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int err = 0;
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if (bus->hosttype != BCMA_HOSTTYPE_PCI) {
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/* This bcma device is not on a PCI host-bus. So the IRQs are
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* not routed through the PCI core.
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* So we must not enable routing through the PCI core. */
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goto out;
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}
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pdev = bus->host_pci;
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err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
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if (err)
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goto out;
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coremask = BIT(core->core_index) << 8;
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if (enable)
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tmp |= coremask;
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else
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tmp &= ~coremask;
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err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
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out:
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return err;
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
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static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
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{
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u32 w;
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@@ -351,3 +351,37 @@ void bcma_host_pci_down(struct bcma_bus *bus)
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bcma_core_pci_down(&bus->drv_pci[0]);
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}
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EXPORT_SYMBOL_GPL(bcma_host_pci_down);
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/* See also si_pci_setup */
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int bcma_host_pci_irq_ctl(struct bcma_bus *bus, struct bcma_device *core,
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bool enable)
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{
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struct pci_dev *pdev;
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u32 coremask, tmp;
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int err = 0;
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if (bus->hosttype != BCMA_HOSTTYPE_PCI) {
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/* This bcma device is not on a PCI host-bus. So the IRQs are
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* not routed through the PCI core.
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* So we must not enable routing through the PCI core. */
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goto out;
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}
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pdev = bus->host_pci;
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err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
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if (err)
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goto out;
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coremask = BIT(core->core_index) << 8;
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if (enable)
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tmp |= coremask;
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else
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tmp &= ~coremask;
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err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
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out:
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return err;
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}
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EXPORT_SYMBOL_GPL(bcma_host_pci_irq_ctl);
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@@ -779,8 +779,6 @@ static void ar5523_tx(struct ieee80211_hw *hw,
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ieee80211_stop_queues(hw);
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}
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data->skb = skb;
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spin_lock_irqsave(&ar->tx_data_list_lock, flags);
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list_add_tail(&data->list, &ar->tx_queue_pending);
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spin_unlock_irqrestore(&ar->tx_data_list_lock, flags);
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@@ -817,10 +815,13 @@ static void ar5523_tx_work_locked(struct ar5523 *ar)
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if (!data)
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break;
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skb = data->skb;
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txi = container_of((void *)data, struct ieee80211_tx_info,
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driver_data);
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txqid = 0;
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txi = IEEE80211_SKB_CB(skb);
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skb = container_of((void *)txi, struct sk_buff, cb);
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paylen = skb->len;
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urb = usb_alloc_urb(0, GFP_KERNEL);
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if (!urb) {
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ar5523_err(ar, "Failed to allocate TX urb\n");
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@@ -74,7 +74,6 @@ struct ar5523_tx_cmd {
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struct ar5523_tx_data {
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struct list_head list;
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struct ar5523 *ar;
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struct sk_buff *skb;
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struct urb *urb;
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};
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@@ -131,6 +131,9 @@ struct ath_ops {
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void (*enable_write_buffer)(void *);
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void (*write_flush) (void *);
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u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
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void (*enable_rmw_buffer)(void *);
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void (*rmw_flush) (void *);
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};
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struct ath_common;
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@@ -1283,6 +1283,7 @@ struct ath5k_hw {
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#define ATH_STAT_PROMISC 1
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#define ATH_STAT_LEDSOFT 2 /* enable LED gpio status */
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#define ATH_STAT_STARTED 3 /* opened & irqs enabled */
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#define ATH_STAT_RESET 4 /* hw reset */
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unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
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unsigned int fif_filter_flags; /* Current FIF_* filter flags */
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@@ -1523,6 +1523,9 @@ ath5k_set_current_imask(struct ath5k_hw *ah)
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enum ath5k_int imask;
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unsigned long flags;
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if (test_bit(ATH_STAT_RESET, ah->status))
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return;
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spin_lock_irqsave(&ah->irqlock, flags);
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imask = ah->imask;
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if (ah->rx_pending)
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@@ -2858,10 +2861,12 @@ ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
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{
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struct ath_common *common = ath5k_hw_common(ah);
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int ret, ani_mode;
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bool fast;
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bool fast = chan && modparam_fastchanswitch ? 1 : 0;
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ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
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__set_bit(ATH_STAT_RESET, ah->status);
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ath5k_hw_set_imr(ah, 0);
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synchronize_irq(ah->irq);
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ath5k_stop_tasklets(ah);
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@@ -2876,11 +2881,29 @@ ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
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* so we should also free any remaining
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* tx buffers */
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ath5k_drain_tx_buffs(ah);
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/* Stop PCU */
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ath5k_hw_stop_rx_pcu(ah);
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/* Stop DMA
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*
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* Note: If DMA didn't stop continue
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* since only a reset will fix it.
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*/
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ret = ath5k_hw_dma_stop(ah);
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/* RF Bus grant won't work if we have pending
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* frames
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*/
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if (ret && fast) {
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ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
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"DMA didn't stop, falling back to normal reset\n");
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fast = false;
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}
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if (chan)
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ah->curchan = chan;
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fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
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ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
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if (ret) {
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||||
ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
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@@ -2934,6 +2957,8 @@ ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
|
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*/
|
||||
/* ath5k_chan_change(ah, c); */
|
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|
||||
__clear_bit(ATH_STAT_RESET, ah->status);
|
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||||
ath5k_beacon_config(ah);
|
||||
/* intrs are enabled by ath5k_beacon_config */
|
||||
|
||||
|
||||
@@ -1169,30 +1169,6 @@ ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
|
||||
if (ah->ah_version == AR5K_AR5212)
|
||||
ath5k_hw_set_sleep_clock(ah, false);
|
||||
|
||||
/*
|
||||
* Stop PCU
|
||||
*/
|
||||
ath5k_hw_stop_rx_pcu(ah);
|
||||
|
||||
/*
|
||||
* Stop DMA
|
||||
*
|
||||
* Note: If DMA didn't stop continue
|
||||
* since only a reset will fix it.
|
||||
*/
|
||||
ret = ath5k_hw_dma_stop(ah);
|
||||
|
||||
/* RF Bus grant won't work if we have pending
|
||||
* frames */
|
||||
if (ret && fast) {
|
||||
ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
|
||||
"DMA didn't stop, falling back to normal reset\n");
|
||||
fast = false;
|
||||
/* Non fatal, just continue with
|
||||
* normal reset */
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
mode = channel->hw_value;
|
||||
switch (mode) {
|
||||
case AR5K_MODE_11A:
|
||||
|
||||
@@ -46,7 +46,8 @@ ath9k_hw-y:= \
|
||||
ath9k_hw-$(CONFIG_ATH9K_WOW) += ar9003_wow.o
|
||||
|
||||
ath9k_hw-$(CONFIG_ATH9K_BTCOEX_SUPPORT) += btcoex.o \
|
||||
ar9003_mci.o
|
||||
ar9003_mci.o \
|
||||
ar9003_aic.o
|
||||
|
||||
ath9k_hw-$(CONFIG_ATH9K_PCOEM) += ar9003_rtt.o
|
||||
|
||||
|
||||
@@ -107,11 +107,21 @@ static const struct ani_cck_level_entry cck_level_table[] = {
|
||||
static void ath9k_hw_update_mibstats(struct ath_hw *ah,
|
||||
struct ath9k_mib_stats *stats)
|
||||
{
|
||||
stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
|
||||
stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
|
||||
stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
|
||||
stats->rts_good += REG_READ(ah, AR_RTS_OK);
|
||||
stats->beacons += REG_READ(ah, AR_BEACON_CNT);
|
||||
u32 addr[5] = {AR_RTS_OK, AR_RTS_FAIL, AR_ACK_FAIL,
|
||||
AR_FCS_FAIL, AR_BEACON_CNT};
|
||||
u32 data[5];
|
||||
|
||||
REG_READ_MULTI(ah, &addr[0], &data[0], 5);
|
||||
/* AR_RTS_OK */
|
||||
stats->rts_good += data[0];
|
||||
/* AR_RTS_FAIL */
|
||||
stats->rts_bad += data[1];
|
||||
/* AR_ACK_FAIL */
|
||||
stats->ackrcv_bad += data[2];
|
||||
/* AR_FCS_FAIL */
|
||||
stats->fcs_bad += data[3];
|
||||
/* AR_BEACON_CNT */
|
||||
stats->beacons += data[4];
|
||||
}
|
||||
|
||||
static void ath9k_ani_restart(struct ath_hw *ah)
|
||||
|
||||
@@ -681,12 +681,13 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
|
||||
phymode |= AR_PHY_FC_DYN2040_PRI_CH;
|
||||
|
||||
}
|
||||
ENABLE_REGWRITE_BUFFER(ah);
|
||||
REG_WRITE(ah, AR_PHY_TURBO, phymode);
|
||||
|
||||
/* This function do only REG_WRITE, so
|
||||
* we can include it to REGWRITE_BUFFER. */
|
||||
ath9k_hw_set11nmac2040(ah, chan);
|
||||
|
||||
ENABLE_REGWRITE_BUFFER(ah);
|
||||
|
||||
REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
|
||||
REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
|
||||
|
||||
|
||||
@@ -430,46 +430,43 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
|
||||
u32 regVal;
|
||||
unsigned int i;
|
||||
u32 regList[][2] = {
|
||||
{ 0x786c, 0 },
|
||||
{ 0x7854, 0 },
|
||||
{ 0x7820, 0 },
|
||||
{ 0x7824, 0 },
|
||||
{ 0x7868, 0 },
|
||||
{ 0x783c, 0 },
|
||||
{ 0x7838, 0 } ,
|
||||
{ 0x7828, 0 } ,
|
||||
{ AR9285_AN_TOP3, 0 },
|
||||
{ AR9285_AN_RXTXBB1, 0 },
|
||||
{ AR9285_AN_RF2G1, 0 },
|
||||
{ AR9285_AN_RF2G2, 0 },
|
||||
{ AR9285_AN_TOP2, 0 },
|
||||
{ AR9285_AN_RF2G8, 0 },
|
||||
{ AR9285_AN_RF2G7, 0 },
|
||||
{ AR9285_AN_RF2G3, 0 },
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(regList); i++)
|
||||
regList[i][1] = REG_READ(ah, regList[i][0]);
|
||||
|
||||
regVal = REG_READ(ah, 0x7834);
|
||||
regVal &= (~(0x1));
|
||||
REG_WRITE(ah, 0x7834, regVal);
|
||||
regVal = REG_READ(ah, 0x9808);
|
||||
regVal |= (0x1 << 27);
|
||||
REG_WRITE(ah, 0x9808, regVal);
|
||||
REG_READ_ARRAY(ah, regList, ARRAY_SIZE(regList));
|
||||
|
||||
ENABLE_REG_RMW_BUFFER(ah);
|
||||
/* 7834, b1=0 */
|
||||
REG_CLR_BIT(ah, AR9285_AN_RF2G6, 1 << 0);
|
||||
/* 9808, b27=1 */
|
||||
REG_SET_BIT(ah, 0x9808, 1 << 27);
|
||||
/* 786c,b23,1, pwddac=1 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
|
||||
REG_SET_BIT(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
|
||||
/* 7854, b5,1, pdrxtxbb=1 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
|
||||
REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
|
||||
/* 7854, b7,1, pdv2i=1 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
|
||||
REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
|
||||
/* 7854, b8,1, pddacinterface=1 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
|
||||
REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
|
||||
/* 7824,b12,0, offcal=0 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
|
||||
REG_CLR_BIT(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL);
|
||||
/* 7838, b1,0, pwddb=0 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
|
||||
REG_CLR_BIT(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB);
|
||||
/* 7820,b11,0, enpacal=0 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
|
||||
REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL);
|
||||
/* 7820,b25,1, pdpadrv1=0 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
|
||||
REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1);
|
||||
/* 7820,b24,0, pdpadrv2=0 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
|
||||
REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2);
|
||||
/* 7820,b23,0, pdpaout=0 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
|
||||
REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT);
|
||||
/* 783c,b14-16,7, padrvgn2tab_0=7 */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
|
||||
/*
|
||||
@@ -477,8 +474,9 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
|
||||
* does not matter since we turn it off
|
||||
*/
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
|
||||
|
||||
/* 7828, b0-11, ccom=fff */
|
||||
REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
|
||||
REG_RMW_BUFFER_FLUSH(ah);
|
||||
|
||||
/* Set:
|
||||
* localmode=1,bmode=1,bmoderxtx=1,synthon=1,
|
||||
@@ -490,15 +488,16 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
|
||||
|
||||
/* find off_6_1; */
|
||||
for (i = 6; i > 0; i--) {
|
||||
regVal = REG_READ(ah, 0x7834);
|
||||
regVal = REG_READ(ah, AR9285_AN_RF2G6);
|
||||
regVal |= (1 << (20 + i));
|
||||
REG_WRITE(ah, 0x7834, regVal);
|
||||
REG_WRITE(ah, AR9285_AN_RF2G6, regVal);
|
||||
udelay(1);
|
||||
/* regVal = REG_READ(ah, 0x7834); */
|
||||
regVal &= (~(0x1 << (20 + i)));
|
||||
regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
|
||||
regVal |= (MS(REG_READ(ah, AR9285_AN_RF2G9),
|
||||
AR9285_AN_RXTXBB1_SPARE9)
|
||||
<< (20 + i));
|
||||
REG_WRITE(ah, 0x7834, regVal);
|
||||
REG_WRITE(ah, AR9285_AN_RF2G6, regVal);
|
||||
}
|
||||
|
||||
regVal = (regVal >> 20) & 0x7f;
|
||||
@@ -515,15 +514,15 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
|
||||
ah->pacal_info.prev_offset = regVal;
|
||||
}
|
||||
|
||||
|
||||
ENABLE_REG_RMW_BUFFER(ah);
|
||||
/* 7834, b1=1 */
|
||||
REG_SET_BIT(ah, AR9285_AN_RF2G6, 1 << 0);
|
||||
/* 9808, b27=0 */
|
||||
REG_CLR_BIT(ah, 0x9808, 1 << 27);
|
||||
REG_RMW_BUFFER_FLUSH(ah);
|
||||
|
||||
ENABLE_REGWRITE_BUFFER(ah);
|
||||
|
||||
regVal = REG_READ(ah, 0x7834);
|
||||
regVal |= 0x1;
|
||||
REG_WRITE(ah, 0x7834, regVal);
|
||||
regVal = REG_READ(ah, 0x9808);
|
||||
regVal &= (~(0x1 << 27));
|
||||
REG_WRITE(ah, 0x9808, regVal);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(regList); i++)
|
||||
REG_WRITE(ah, regList[i][0], regList[i][1]);
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Qualcomm Atheros Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef AR9003_AIC_H
|
||||
#define AR9003_AIC_H
|
||||
|
||||
#define ATH_AIC_MAX_COM_ATT_DB_TABLE 6
|
||||
#define ATH_AIC_MAX_AIC_LIN_TABLE 69
|
||||
#define ATH_AIC_MIN_ROT_DIR_ATT_DB 0
|
||||
#define ATH_AIC_MIN_ROT_QUAD_ATT_DB 0
|
||||
#define ATH_AIC_MAX_ROT_DIR_ATT_DB 37
|
||||
#define ATH_AIC_MAX_ROT_QUAD_ATT_DB 37
|
||||
#define ATH_AIC_SRAM_AUTO_INCREMENT 0x80000000
|
||||
#define ATH_AIC_SRAM_GAIN_TABLE_OFFSET 0x280
|
||||
#define ATH_AIC_SRAM_CAL_OFFSET 0x140
|
||||
#define ATH_AIC_SRAM_OFFSET 0x00
|
||||
#define ATH_AIC_MEAS_MAG_THRESH 20
|
||||
#define ATH_AIC_BT_JUPITER_CTRL 0x66820
|
||||
#define ATH_AIC_BT_AIC_ENABLE 0x02
|
||||
|
||||
enum aic_cal_state {
|
||||
AIC_CAL_STATE_IDLE = 0,
|
||||
AIC_CAL_STATE_STARTED,
|
||||
AIC_CAL_STATE_DONE,
|
||||
AIC_CAL_STATE_ERROR
|
||||
};
|
||||
|
||||
struct ath_aic_sram_info {
|
||||
bool valid:1;
|
||||
bool vga_quad_sign:1;
|
||||
bool vga_dir_sign:1;
|
||||
u8 rot_quad_att_db;
|
||||
u8 rot_dir_att_db;
|
||||
u8 com_att_6db;
|
||||
};
|
||||
|
||||
struct ath_aic_out_info {
|
||||
int16_t dir_path_gain_lin;
|
||||
int16_t quad_path_gain_lin;
|
||||
struct ath_aic_sram_info sram;
|
||||
};
|
||||
|
||||
u8 ar9003_aic_calibration(struct ath_hw *ah);
|
||||
u8 ar9003_aic_start_normal(struct ath_hw *ah);
|
||||
u8 ar9003_aic_cal_reset(struct ath_hw *ah);
|
||||
u8 ar9003_aic_calibration_single(struct ath_hw *ah);
|
||||
|
||||
#endif /* AR9003_AIC_H */
|
||||
@@ -195,16 +195,16 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
|
||||
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
|
||||
ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
|
||||
|
||||
if (ah->config.no_pll_pwrsave) {
|
||||
if (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) {
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9485_1_1_pcie_phy_clkreq_disable_L1);
|
||||
ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9485_1_1_pcie_phy_clkreq_disable_L1);
|
||||
ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
|
||||
} else {
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
|
||||
ar9485_1_1_pcie_phy_clkreq_disable_L1);
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
|
||||
ar9485_1_1_pcie_phy_clkreq_disable_L1);
|
||||
}
|
||||
} else if (AR_SREV_9462_21(ah)) {
|
||||
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
|
||||
@@ -231,10 +231,20 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
|
||||
ar9462_2p1_modes_fast_clock);
|
||||
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
|
||||
ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9462_2p1_pciephy_clkreq_disable_L1);
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9462_2p1_pciephy_clkreq_disable_L1);
|
||||
|
||||
/* Awake -> Sleep Setting */
|
||||
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
|
||||
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9462_2p1_pciephy_clkreq_disable_L1);
|
||||
}
|
||||
|
||||
/* Sleep -> Awake Setting */
|
||||
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
|
||||
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9462_2p1_pciephy_clkreq_disable_L1);
|
||||
}
|
||||
} else if (AR_SREV_9462_20(ah)) {
|
||||
|
||||
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
|
||||
@@ -262,11 +272,18 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
|
||||
ar9462_2p0_common_rx_gain);
|
||||
|
||||
/* Awake -> Sleep Setting */
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9462_2p0_pciephy_clkreq_disable_L1);
|
||||
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
|
||||
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9462_2p0_pciephy_clkreq_disable_L1);
|
||||
}
|
||||
|
||||
/* Sleep -> Awake Setting */
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9462_2p0_pciephy_clkreq_disable_L1);
|
||||
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
|
||||
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9462_2p0_pciephy_clkreq_disable_L1);
|
||||
}
|
||||
|
||||
/* Fast clock modal settings */
|
||||
INIT_INI_ARRAY(&ah->iniModesFastClock,
|
||||
@@ -456,10 +473,19 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
|
||||
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
|
||||
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9565_1p1_pciephy_clkreq_disable_L1);
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9565_1p1_pciephy_clkreq_disable_L1);
|
||||
/* Awake -> Sleep Setting */
|
||||
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
|
||||
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9565_1p1_pciephy_clkreq_disable_L1);
|
||||
}
|
||||
|
||||
/* Sleep -> Awake Setting */
|
||||
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
|
||||
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9565_1p1_pciephy_clkreq_disable_L1);
|
||||
}
|
||||
|
||||
INIT_INI_ARRAY(&ah->iniModesFastClock,
|
||||
ar9565_1p1_modes_fast_clock);
|
||||
@@ -491,10 +517,19 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
|
||||
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
|
||||
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9565_1p0_pciephy_clkreq_disable_L1);
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9565_1p0_pciephy_clkreq_disable_L1);
|
||||
/* Awake -> Sleep Setting */
|
||||
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
|
||||
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9565_1p0_pciephy_clkreq_disable_L1);
|
||||
}
|
||||
|
||||
/* Sleep -> Awake Setting */
|
||||
if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
|
||||
(ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9565_1p0_pciephy_clkreq_disable_L1);
|
||||
}
|
||||
|
||||
INIT_INI_ARRAY(&ah->iniModesFastClock,
|
||||
ar9565_1p0_modes_fast_clock);
|
||||
@@ -1130,6 +1165,12 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
|
||||
struct ath_hw_ops *ops = ath9k_hw_ops(ah);
|
||||
|
||||
ar9003_hw_init_mode_regs(ah);
|
||||
|
||||
if (AR_SREV_9003_PCOEM(ah)) {
|
||||
WARN_ON(!ah->iniPcieSerdes.ia_array);
|
||||
WARN_ON(!ah->iniPcieSerdesLowPower.ia_array);
|
||||
}
|
||||
|
||||
priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
|
||||
priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;
|
||||
priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;
|
||||
@@ -1139,4 +1180,5 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
|
||||
ar9003_hw_attach_phy_ops(ah);
|
||||
ar9003_hw_attach_calib_ops(ah);
|
||||
ar9003_hw_attach_mac_ops(ah);
|
||||
ar9003_hw_attach_aic_ops(ah);
|
||||
}
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
#include "hw-ops.h"
|
||||
#include "ar9003_phy.h"
|
||||
#include "ar9003_mci.h"
|
||||
#include "ar9003_aic.h"
|
||||
|
||||
static void ar9003_mci_reset_req_wakeup(struct ath_hw *ah)
|
||||
{
|
||||
@@ -1016,6 +1017,9 @@ int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
|
||||
if (en_int)
|
||||
ar9003_mci_enable_interrupt(ah);
|
||||
|
||||
if (ath9k_hw_is_aic_enabled(ah))
|
||||
ar9003_aic_start_normal(ah);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1362,6 +1366,22 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type)
|
||||
value = (!mci->unhalt_bt_gpm && mci->need_flush_btinfo) ? 1 : 0;
|
||||
mci->need_flush_btinfo = false;
|
||||
break;
|
||||
case MCI_STATE_AIC_CAL:
|
||||
if (ath9k_hw_is_aic_enabled(ah))
|
||||
value = ar9003_aic_calibration(ah);
|
||||
break;
|
||||
case MCI_STATE_AIC_START:
|
||||
if (ath9k_hw_is_aic_enabled(ah))
|
||||
ar9003_aic_start_normal(ah);
|
||||
break;
|
||||
case MCI_STATE_AIC_CAL_RESET:
|
||||
if (ath9k_hw_is_aic_enabled(ah))
|
||||
value = ar9003_aic_cal_reset(ah);
|
||||
break;
|
||||
case MCI_STATE_AIC_CAL_SINGLE:
|
||||
if (ath9k_hw_is_aic_enabled(ah))
|
||||
value = ar9003_aic_calibration_single(ah);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -640,16 +640,6 @@
|
||||
#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00
|
||||
#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8
|
||||
|
||||
/* AIC Registers */
|
||||
#define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
|
||||
#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
|
||||
#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
|
||||
#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
|
||||
#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4))
|
||||
#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8))
|
||||
#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
|
||||
#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
|
||||
|
||||
#define AR_PHY_65NM_CH0_TXRF3 0x16048
|
||||
#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G 0x0000001e
|
||||
#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1
|
||||
@@ -989,21 +979,6 @@
|
||||
#define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)
|
||||
#define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM1_BASE + 0x450 + ((_i) << 2))
|
||||
|
||||
/* SM 1 AIC Registers */
|
||||
|
||||
#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
|
||||
#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
|
||||
#define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8)
|
||||
#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
|
||||
0x4c0 : 0x4c4))
|
||||
#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
|
||||
0x4c4 : 0x4c8))
|
||||
#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0)
|
||||
#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc)
|
||||
|
||||
#define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0)
|
||||
#define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4)
|
||||
|
||||
#define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + ((i) ? \
|
||||
AR_SM1_BASE : AR_SM_BASE))
|
||||
#define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + ((i) ? \
|
||||
|
||||
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Reference in New Issue
Block a user