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V4L/DVB (3809b): Added missing docs at kernel tree
Date: From: Mauro Carvalho Chehab <mchehab@infradead.org> There are some docs at V4L/DVB tree that were never included at kernel. This patch includes those docs. Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Mauro Carvalho Chehab
@@ -0,0 +1,69 @@
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This page describes how to make calls to the firmware api.
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How to call
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===========
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The preferred calling convention is known as the firmware mailbox. The
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mailboxes are basically a fixed length array that serves as the call-stack.
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Firmware mailboxes can be located by searching the encoder and decoder memory
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for a 16 byte signature. That signature will be located on a 256-byte boundary.
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Signature:
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0x78, 0x56, 0x34, 0x12, 0x12, 0x78, 0x56, 0x34,
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0x34, 0x12, 0x78, 0x56, 0x56, 0x34, 0x12, 0x78
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The firmware implements 20 mailboxes of 20 32-bit words. The first 10 are
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reserved for API calls. The second 10 are used by the firmware for event
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notification.
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Index Name
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----- ----
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0 Flags
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1 Command
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2 Return value
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3 Timeout
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4-19 Parameter/Result
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The flags are defined in the following table. The direction is from the
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perspective of the firmware.
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Bit Direction Purpose
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--- --------- -------
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2 O Firmware has processed the command.
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1 I Driver has finished setting the parameters.
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0 I Driver is using this mailbox.
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The command is a 32-bit enumerator. The API specifics may be found in the
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fw-*-api.txt documents.
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The return value is a 32-bit enumerator. Only two values are currently defined:
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0=success and -1=command undefined.
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There are 16 parameters/results 32-bit fields. The driver populates these fields
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with values for all the parameters required by the call. The driver overwrites
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these fields with result values returned by the call. The API specifics may be
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found in the fw-*-api.txt documents.
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The timeout value protects the card from a hung driver thread. If the driver
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doesn't handle the completed call within the timeout specified, the firmware
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will reset that mailbox.
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To make an API call, the driver iterates over each mailbox looking for the
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first one available (bit 0 has been cleared). The driver sets that bit, fills
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in the command enumerator, the timeout value and any required parameters. The
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driver then sets the parameter ready bit (bit 1). The firmware scans the
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mailboxes for pending commands, processes them, sets the result code, populates
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the result value array with that call's return values and sets the call
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complete bit (bit 2). Once bit 2 is set, the driver should retrieve the results
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and clear all the flags. If the driver does not perform this task within the
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time set in the timeout register, the firmware will reset that mailbox.
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Event notifications are sent from the firmware to the host. The host tells the
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firmware which events it is interested in via an API call. That call tells the
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firmware which notification mailbox to use. The firmware signals the host via
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an interrupt. Only the 16 Results fields are used, the Flags, Command, Return
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value and Timeout words are not used.
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@@ -0,0 +1,319 @@
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Decoder firmware API description
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================================
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Note: this API is part of the decoder firmware, so it's cx23415 only.
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_PING_FW
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Enum 0/0x00
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Description
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This API call does nothing. It may be used to check if the firmware
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is responding.
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_START_PLAYBACK
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Enum 1/0x01
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Description
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Begin or resume playback.
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Param[0]
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0 based frame number in GOP to begin playback from.
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Param[1]
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Specifies the number of muted audio frames to play before normal
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audio resumes.
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_STOP_PLAYBACK
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Enum 2/0x02
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Description
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Ends playback and clears all decoder buffers. If PTS is not zero,
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playback stops at specified PTS.
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Param[0]
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Display 0=last frame, 1=black
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Param[1]
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PTS low
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Param[2]
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PTS high
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SET_PLAYBACK_SPEED
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Enum 3/0x03
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Description
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Playback stream at speed other than normal. There are two modes of
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operation:
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Smooth: host transfers entire stream and firmware drops unused
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frames.
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Coarse: host drops frames based on indexing as required to achieve
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desired speed.
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Param[0]
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Bitmap:
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0:7 0 normal
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1 fast only "1.5 times"
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n nX fast, 1/nX slow
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30 Framedrop:
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'0' during 1.5 times play, every other B frame is dropped
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'1' during 1.5 times play, stream is unchanged (bitrate
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must not exceed 8mbps)
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31 Speed:
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'0' slow
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'1' fast
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Param[1]
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Direction: 0=forward, 1=reverse
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Param[2]
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Picture mask:
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1=I frames
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3=I, P frames
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7=I, P, B frames
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Param[3]
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B frames per GOP (for reverse play only)
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Param[4]
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Mute audio: 0=disable, 1=enable
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Param[5]
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Display 0=frame, 1=field
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Param[6]
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Specifies the number of muted audio frames to play before normal audio
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resumes.
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_STEP_VIDEO
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Enum 5/0x05
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Description
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Each call to this API steps the playback to the next unit defined below
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in the current playback direction.
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Param[0]
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0=frame, 1=top field, 2=bottom field
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SET_DMA_BLOCK_SIZE
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Enum 8/0x08
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Description
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Set DMA transfer block size. Counterpart to API 0xC9
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Param[0]
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DMA transfer block size in bytes. A different size may be specified
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when issuing the DMA transfer command.
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_GET_XFER_INFO
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Enum 9/0x09
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Description
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This API call may be used to detect an end of stream condtion.
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Result[0]
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Stream type
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Result[1]
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Address offset
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Result[2]
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Maximum bytes to transfer
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Result[3]
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Buffer fullness
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_GET_DMA_STATUS
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Enum 10/0x0A
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Description
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Status of the last DMA transfer
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Result[0]
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Bit 1 set means transfer complete
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Bit 2 set means DMA error
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Bit 3 set means linked list error
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Result[1]
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DMA type: 0=MPEG, 1=OSD, 2=YUV
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SCHED_DMA_FROM_HOST
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Enum 11/0x0B
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Description
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Setup DMA from host operation. Counterpart to API 0xCC
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Param[0]
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Memory address of link list
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Param[1]
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Total # of bytes to transfer
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Param[2]
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DMA type (0=MPEG, 1=OSD, 2=YUV)
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_PAUSE_PLAYBACK
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Enum 13/0x0D
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Description
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Freeze playback immediately. In this mode, when internal buffers are
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full, no more data will be accepted and data request IRQs will be
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masked.
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Param[0]
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Display: 0=last frame, 1=black
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_HALT_FW
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Enum 14/0x0E
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Description
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The firmware is halted and no further API calls are serviced until
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the firmware is uploaded again.
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SET_STANDARD
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Enum 16/0x10
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Description
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Selects display standard
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Param[0]
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0=NTSC, 1=PAL
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_GET_VERSION
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Enum 17/0x11
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Description
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Returns decoder firmware version information
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Result[0]
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Version bitmask:
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Bits 0:15 build
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Bits 16:23 minor
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Bits 24:31 major
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SET_STREAM_INPUT
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Enum 20/0x14
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Description
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Select decoder stream input port
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Param[0]
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0=memory (default), 1=streaming
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_GET_TIMING_INFO
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Enum 21/0x15
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Description
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Returns timing information from start of playback
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Result[0]
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Frame count by decode order
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Result[1]
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Video PTS bits 0:31 by display order
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Result[2]
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Video PTS bit 32 by display order
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Result[3]
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SCR bits 0:31 by display order
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Result[4]
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SCR bit 32 by display order
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SET_AUDIO_MODE
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Enum 22/0x16
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Description
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Select audio mode
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Param[0]
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Dual mono mode action
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Param[1]
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Stereo mode action:
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0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SET_EVENT_NOTIFICATION
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Enum 23/0x17
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Description
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Setup firmware to notify the host about a particular event.
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Counterpart to API 0xD5
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Param[0]
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Event: 0=Audio mode change between stereo and dual channel
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Param[1]
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Notification 0=disabled, 1=enabled
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Param[2]
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Interrupt bit
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Param[3]
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Mailbox slot, -1 if no mailbox required.
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SET_DISPLAY_BUFFERS
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Enum 24/0x18
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Description
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Number of display buffers. To decode all frames in reverse playback you
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must use nine buffers.
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Param[0]
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0=six buffers, 1=nine buffers
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_EXTRACT_VBI
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Enum 25/0x19
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Description
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Extracts VBI data
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Param[0]
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0=extract from extension & user data, 1=extract from private packets
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Result[0]
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VBI table location
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Result[1]
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VBI table size
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SET_DECODER_SOURCE
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Enum 26/0x1A
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Description
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Selects decoder source. Ensure that the parameters passed to this
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API match the encoder settings.
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Param[0]
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Mode: 0=MPEG from host, 1=YUV from encoder, 2=YUV from host
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Param[1]
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YUV picture width
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Param[2]
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YUV picture height
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Param[3]
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Bitmap: see Param[0] of API 0xBD
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SET_AUDIO_OUTPUT
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Enum 27/0x1B
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Description
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Select audio output format
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Param[0]
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Bitmask:
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0:1 Data size:
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'00' 16 bit
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'01' 20 bit
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'10' 24 bit
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2:7 Unused
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8:9 Mode:
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'00' 2 channels
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'01' 4 channels
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'10' 6 channels
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'11' 6 channels with one line data mode
|
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(for left justified MSB first mode, 20 bit only)
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10:11 Unused
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12:13 Channel format:
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'00' right justified MSB first mode
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'01' left justified MSB first mode
|
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'10' I2S mode
|
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14:15 Unused
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16:21 Right justify bit count
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22:31 Unused
|
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-------------------------------------------------------------------------------
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Name CX2341X_DEC_SET_AV_DELAY
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Enum 28/0x1C
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Description
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Set audio/video delay in 90Khz ticks
|
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Param[0]
|
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0=A/V in sync, negative=audio lags, positive=video lags
|
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-------------------------------------------------------------------------------
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|
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Name CX2341X_DEC_SET_PREBUFFERING
|
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Enum 30/0x1E
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Description
|
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Decoder prebuffering, when enabled up to 128KB are buffered for
|
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streams <8mpbs or 640KB for streams >8mbps
|
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Param[0]
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0=off, 1=on
|
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@@ -0,0 +1,94 @@
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This page describes the structures and procedures used by the cx2341x DMA
|
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engine.
|
||||
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Introduction
|
||||
============
|
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|
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The cx2341x PCI interface is busmaster capable. This means it has a DMA
|
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engine to efficiently transfer large volumes of data between the card and main
|
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memory without requiring help from a CPU. Like most hardware, it must operate
|
||||
on contiguous physical memory. This is difficult to come by in large quantities
|
||||
on virtual memory machines.
|
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|
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Therefore, it also supports a technique called "scatter-gather". The card can
|
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transfer multiple buffers in one operation. Instead of allocating one large
|
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contiguous buffer, the driver can allocate several smaller buffers.
|
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|
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In practice, I've seen the average transfer to be roughly 80K, but transfers
|
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above 128K were not uncommon, particularly at startup. The 128K figure is
|
||||
important, because that is the largest block that the kernel can normally
|
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allocate. Even still, 128K blocks are hard to come by, so the driver writer is
|
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urged to choose a smaller block size and learn the scatter-gather technique.
|
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|
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Mailbox #10 is reserved for DMA transfer information.
|
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|
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Flow
|
||||
====
|
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|
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This section describes, in general, the order of events when handling DMA
|
||||
transfers. Detailed information follows this section.
|
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|
||||
- The card raises the Encoder interrupt.
|
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- The driver reads the transfer type, offset and size from Mailbox #10.
|
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- The driver constructs the scatter-gather array from enough free dma buffers
|
||||
to cover the size.
|
||||
- The driver schedules the DMA transfer via the ScheduleDMAtoHost API call.
|
||||
- The card raises the DMA Complete interrupt.
|
||||
- The driver checks the DMA status register for any errors.
|
||||
- The driver post-processes the newly transferred buffers.
|
||||
|
||||
NOTE! It is possible that the Encoder and DMA Complete interrupts get raised
|
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simultaneously. (End of the last, start of the next, etc.)
|
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|
||||
Mailbox #10
|
||||
===========
|
||||
|
||||
The Flags, Command, Return Value and Timeout fields are ignored.
|
||||
|
||||
Name: Mailbox #10
|
||||
Results[0]: Type: 0: MPEG.
|
||||
Results[1]: Offset: The position relative to the card's memory space.
|
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Results[2]: Size: The exact number of bytes to transfer.
|
||||
|
||||
My speculation is that since the StartCapture API has a capture type of "RAW"
|
||||
available, that the type field will have other values that correspond to YUV
|
||||
and PCM data.
|
||||
|
||||
Scatter-Gather Array
|
||||
====================
|
||||
|
||||
The scatter-gather array is a contiguously allocated block of memory that
|
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tells the card the source and destination of each data-block to transfer.
|
||||
Card "addresses" are derived from the offset supplied by Mailbox #10. Host
|
||||
addresses are the physical memory location of the target DMA buffer.
|
||||
|
||||
Each S-G array element is a struct of three 32-bit words. The first word is
|
||||
the source address, the second is the destination address. Both take up the
|
||||
entire 32 bits. The lowest 16 bits of the third word is the transfer byte
|
||||
count. The high-bit of the third word is the "last" flag. The last-flag tells
|
||||
the card to raise the DMA_DONE interrupt. From hard personal experience, if
|
||||
you forget to set this bit, the card will still "work" but the stream will
|
||||
most likely get corrupted.
|
||||
|
||||
The transfer count must be a multiple of 256. Therefore, the driver will need
|
||||
to track how much data in the target buffer is valid and deal with it
|
||||
accordingly.
|
||||
|
||||
Array Element:
|
||||
|
||||
- 32-bit Source Address
|
||||
- 32-bit Destination Address
|
||||
- 16-bit reserved (high bit is the last flag)
|
||||
- 16-bit byte count
|
||||
|
||||
DMA Transfer Status
|
||||
===================
|
||||
|
||||
Register 0x0004 holds the DMA Transfer Status:
|
||||
|
||||
Bit
|
||||
4 Scatter-Gather array error
|
||||
3 DMA write error
|
||||
2 DMA read error
|
||||
1 write completed
|
||||
0 read completed
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,141 @@
|
||||
This document describes the cx2341x memory map and documents some of the register
|
||||
space.
|
||||
|
||||
Warning! This information was figured out from searching through the memory and
|
||||
registers, this information may not be correct and is certainly not complete, and
|
||||
was not derived from anything more than searching through the memory space with
|
||||
commands like:
|
||||
|
||||
ivtvctl -O min=0x02000000,max=0x020000ff
|
||||
|
||||
So take this as is, I'm always searching for more stuff, it's a large
|
||||
register space :-).
|
||||
|
||||
Memory Map
|
||||
==========
|
||||
|
||||
The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0
|
||||
(Base Address Register 0). The addresses here are offsets relative to the
|
||||
address held in BAR0.
|
||||
|
||||
0x00000000-0x00ffffff Encoder memory space
|
||||
0x00000000-0x0003ffff Encode.rom
|
||||
???-??? MPEG buffer(s)
|
||||
???-??? Raw video capture buffer(s)
|
||||
???-??? Raw audio capture buffer(s)
|
||||
???-??? Display buffers (6 or 9)
|
||||
|
||||
0x01000000-0x01ffffff Decoder memory space
|
||||
0x01000000-0x0103ffff Decode.rom
|
||||
???-??? MPEG buffers(s)
|
||||
0x0114b000-0x0115afff Audio.rom (deprecated?)
|
||||
|
||||
0x02000000-0x0200ffff Register Space
|
||||
|
||||
Registers
|
||||
=========
|
||||
|
||||
The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
|
||||
All of these registers are 32 bits wide.
|
||||
|
||||
DMA Registers 0x000-0xff:
|
||||
|
||||
0x00 - Control:
|
||||
0=reset/cancel, 1=read, 2=write, 4=stop
|
||||
0x04 - DMA status:
|
||||
1=read busy, 2=write busy, 4=read error, 8=write error, 16=link list error
|
||||
0x08 - pci DMA pointer for read link list
|
||||
0x0c - pci DMA pointer for write link list
|
||||
0x10 - read/write DMA enable:
|
||||
1=read enable, 2=write enable
|
||||
0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes
|
||||
0x18 - ??
|
||||
0x1c - always 0x20 or 32, smaller values slow down DMA transactions
|
||||
0x20 - always value of 0x780a010a
|
||||
0x24-0x3c - usually just random values???
|
||||
0x40 - Interrupt status
|
||||
0x44 - Write a bit here and shows up in Interrupt status 0x40
|
||||
0x48 - Interrupt Mask
|
||||
0x4C - always value of 0xfffdffff,
|
||||
if changed to 0xffffffff DMA write interrupts break.
|
||||
0x50 - always 0xffffffff
|
||||
0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are
|
||||
3 processors on chip, Java ones, VPU, SPU, APU, maybe these are the
|
||||
interrupt masks???).
|
||||
0x60-0x7C - random values
|
||||
0x80 - first write linked list reg, for Encoder Memory addr
|
||||
0x84 - first write linked list reg, for pci memory addr
|
||||
0x88 - first write linked list reg, for length of buffer in memory addr
|
||||
(|0x80000000 or this for last link)
|
||||
0x8c-0xcc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
|
||||
from linked list addr in reg 0x0c, firmware must push through or
|
||||
something.
|
||||
0xe0 - first (and only) read linked list reg, for pci memory addr
|
||||
0xe4 - first (and only) read linked list reg, for Decoder memory addr
|
||||
0xe8 - first (and only) read linked list reg, for length of buffer
|
||||
0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.
|
||||
|
||||
Memory locations for Encoder Buffers 0x700-0x7ff:
|
||||
|
||||
These registers show offsets of memory locations pertaining to each
|
||||
buffer area used for encoding, have to shift them by <<1 first.
|
||||
|
||||
0x07F8: Encoder SDRAM refresh
|
||||
0x07FC: Encoder SDRAM pre-charge
|
||||
|
||||
Memory locations for Decoder Buffers 0x800-0x8ff:
|
||||
|
||||
These registers show offsets of memory locations pertaining to each
|
||||
buffer area used for decoding, have to shift them by <<1 first.
|
||||
|
||||
0x08F8: Decoder SDRAM refresh
|
||||
0x08FC: Decoder SDRAM pre-charge
|
||||
|
||||
Other memory locations:
|
||||
|
||||
0x2800: Video Display Module control
|
||||
0x2D00: AO (audio output?) control
|
||||
0x2D24: Bytes Flushed
|
||||
0x7000: LSB I2C write clock bit (inverted)
|
||||
0x7004: LSB I2C write data bit (inverted)
|
||||
0x7008: LSB I2C read clock bit
|
||||
0x700c: LSB I2C read data bit
|
||||
0x9008: GPIO get input state
|
||||
0x900c: GPIO set output state
|
||||
0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)
|
||||
0x9050: SPU control
|
||||
0x9054: Reset HW blocks
|
||||
0x9058: VPU control
|
||||
0xA018: Bit6: interrupt pending?
|
||||
0xA064: APU command
|
||||
|
||||
|
||||
Interrupt Status Register
|
||||
=========================
|
||||
|
||||
The definition of the bits in the interrupt status register 0x0040, and the
|
||||
interrupt mask 0x0048. If a bit is cleared in the mask, then we want our ISR to
|
||||
execute.
|
||||
|
||||
Bit
|
||||
31 Encoder Start Capture
|
||||
30 Encoder EOS
|
||||
29 Encoder VBI capture
|
||||
28 Encoder Video Input Module reset event
|
||||
27 Encoder DMA complete
|
||||
26
|
||||
25 Decoder copy protect detection event
|
||||
24 Decoder audio mode change detection event
|
||||
23
|
||||
22 Decoder data request
|
||||
21 Decoder I-Frame? done
|
||||
20 Decoder DMA complete
|
||||
19 Decoder VBI re-insertion
|
||||
18 Decoder DMA err (linked-list bad)
|
||||
|
||||
Missing
|
||||
Encoder API call completed
|
||||
Decoder API call completed
|
||||
Encoder API post(?)
|
||||
Decoder API post(?)
|
||||
Decoder VTRACE event
|
||||
@@ -0,0 +1,342 @@
|
||||
OSD firmware API description
|
||||
============================
|
||||
|
||||
Note: this API is part of the decoder firmware, so it's cx23415 only.
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_GET_FRAMEBUFFER
|
||||
Enum 65/0x41
|
||||
Description
|
||||
Return base and length of contiguous OSD memory.
|
||||
Result[0]
|
||||
OSD base address
|
||||
Result[1]
|
||||
OSD length
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_GET_PIXEL_FORMAT
|
||||
Enum 66/0x42
|
||||
Description
|
||||
Query OSD format
|
||||
Result[0]
|
||||
0=8bit index, 4=AlphaRGB 8:8:8:8
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_SET_PIXEL_FORMAT
|
||||
Enum 67/0x43
|
||||
Description
|
||||
Assign pixel format
|
||||
Param[0]
|
||||
0=8bit index, 4=AlphaRGB 8:8:8:8
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_GET_STATE
|
||||
Enum 68/0x44
|
||||
Description
|
||||
Query OSD state
|
||||
Result[0]
|
||||
Bit 0 0=off, 1=on
|
||||
Bits 1:2 alpha control
|
||||
Bits 3:5 pixel format
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_SET_STATE
|
||||
Enum 69/0x45
|
||||
Description
|
||||
OSD switch
|
||||
Param[0]
|
||||
0=off, 1=on
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_GET_OSD_COORDS
|
||||
Enum 70/0x46
|
||||
Description
|
||||
Retrieve coordinates of OSD area blended with video
|
||||
Result[0]
|
||||
OSD buffer address
|
||||
Result[1]
|
||||
Stride in pixels
|
||||
Result[2]
|
||||
Lines in OSD buffer
|
||||
Result[3]
|
||||
Horizontal offset in buffer
|
||||
Result[4]
|
||||
Vertical offset in buffer
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_SET_OSD_COORDS
|
||||
Enum 71/0x47
|
||||
Description
|
||||
Assign the coordinates of the OSD area to blend with video
|
||||
Param[0]
|
||||
buffer address
|
||||
Param[1]
|
||||
buffer stride in pixels
|
||||
Param[2]
|
||||
lines in buffer
|
||||
Param[3]
|
||||
horizontal offset
|
||||
Param[4]
|
||||
vertical offset
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_GET_SCREEN_COORDS
|
||||
Enum 72/0x48
|
||||
Description
|
||||
Retrieve OSD screen area coordinates
|
||||
Result[0]
|
||||
top left horizontal offset
|
||||
Result[1]
|
||||
top left vertical offset
|
||||
Result[2]
|
||||
bottom right hotizontal offset
|
||||
Result[3]
|
||||
bottom right vertical offset
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_SET_SCREEN_COORDS
|
||||
Enum 73/0x49
|
||||
Description
|
||||
Assign the coordinates of the screen area to blend with video
|
||||
Param[0]
|
||||
top left horizontal offset
|
||||
Param[1]
|
||||
top left vertical offset
|
||||
Param[2]
|
||||
bottom left horizontal offset
|
||||
Param[3]
|
||||
bottom left vertical offset
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_GET_GLOBAL_ALPHA
|
||||
Enum 74/0x4A
|
||||
Description
|
||||
Retrieve OSD global alpha
|
||||
Result[0]
|
||||
global alpha: 0=off, 1=on
|
||||
Result[1]
|
||||
bits 0:7 global alpha
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_SET_GLOBAL_ALPHA
|
||||
Enum 75/0x4B
|
||||
Description
|
||||
Update global alpha
|
||||
Param[0]
|
||||
global alpha: 0=off, 1=on
|
||||
Param[1]
|
||||
global alpha (8 bits)
|
||||
Param[2]
|
||||
local alpha: 0=on, 1=off
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_SET_BLEND_COORDS
|
||||
Enum 78/0x4C
|
||||
Description
|
||||
Move start of blending area within display buffer
|
||||
Param[0]
|
||||
horizontal offset in buffer
|
||||
Param[1]
|
||||
vertical offset in buffer
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_GET_FLICKER_STATE
|
||||
Enum 79/0x4F
|
||||
Description
|
||||
Retrieve flicker reduction module state
|
||||
Result[0]
|
||||
flicker state: 0=off, 1=on
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_SET_FLICKER_STATE
|
||||
Enum 80/0x50
|
||||
Description
|
||||
Set flicker reduction module state
|
||||
Param[0]
|
||||
State: 0=off, 1=on
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_BLT_COPY
|
||||
Enum 82/0x52
|
||||
Description
|
||||
BLT copy
|
||||
Param[0]
|
||||
'0000' zero
|
||||
'0001' ~destination AND ~source
|
||||
'0010' ~destination AND source
|
||||
'0011' ~destination
|
||||
'0100' destination AND ~source
|
||||
'0101' ~source
|
||||
'0110' destination XOR source
|
||||
'0111' ~destination OR ~source
|
||||
'1000' ~destination AND ~source
|
||||
'1001' destination XNOR source
|
||||
'1010' source
|
||||
'1011' ~destination OR source
|
||||
'1100' destination
|
||||
'1101' destination OR ~source
|
||||
'1110' destination OR source
|
||||
'1111' one
|
||||
|
||||
Param[1]
|
||||
Resulting alpha blending
|
||||
'01' source_alpha
|
||||
'10' destination_alpha
|
||||
'11' source_alpha*destination_alpha+1
|
||||
(zero if both source and destination alpha are zero)
|
||||
Param[2]
|
||||
'00' output_pixel = source_pixel
|
||||
|
||||
'01' if source_alpha=0:
|
||||
output_pixel = destination_pixel
|
||||
if 256 > source_alpha > 1:
|
||||
output_pixel = ((source_alpha + 1)*source_pixel +
|
||||
(255 - source_alpha)*destination_pixel)/256
|
||||
|
||||
'10' if destination_alpha=0:
|
||||
output_pixel = source_pixel
|
||||
if 255 > destination_alpha > 0:
|
||||
output_pixel = ((255 - destination_alpha)*source_pixel +
|
||||
(destination_alpha + 1)*destination_pixel)/256
|
||||
|
||||
'11' if source_alpha=0:
|
||||
source_temp = 0
|
||||
if source_alpha=255:
|
||||
source_temp = source_pixel*256
|
||||
if 255 > source_alpha > 0:
|
||||
source_temp = source_pixel*(source_alpha + 1)
|
||||
if destination_alpha=0:
|
||||
destination_temp = 0
|
||||
if destination_alpha=255:
|
||||
destination_temp = destination_pixel*256
|
||||
if 255 > destination_alpha > 0:
|
||||
destination_temp = destination_pixel*(destination_alpha + 1)
|
||||
output_pixel = (source_temp + destination_temp)/256
|
||||
Param[3]
|
||||
width
|
||||
Param[4]
|
||||
height
|
||||
Param[5]
|
||||
destination pixel mask
|
||||
Param[6]
|
||||
destination rectangle start address
|
||||
Param[7]
|
||||
destination stride in dwords
|
||||
Param[8]
|
||||
source stride in dwords
|
||||
Param[9]
|
||||
source rectangle start address
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_BLT_FILL
|
||||
Enum 83/0x53
|
||||
Description
|
||||
BLT fill color
|
||||
Param[0]
|
||||
Same as Param[0] on API 0x52
|
||||
Param[1]
|
||||
Same as Param[1] on API 0x52
|
||||
Param[2]
|
||||
Same as Param[2] on API 0x52
|
||||
Param[3]
|
||||
width
|
||||
Param[4]
|
||||
height
|
||||
Param[5]
|
||||
destination pixel mask
|
||||
Param[6]
|
||||
destination rectangle start address
|
||||
Param[7]
|
||||
destination stride in dwords
|
||||
Param[8]
|
||||
color fill value
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_BLT_TEXT
|
||||
Enum 84/0x54
|
||||
Description
|
||||
BLT for 8 bit alpha text source
|
||||
Param[0]
|
||||
Same as Param[0] on API 0x52
|
||||
Param[1]
|
||||
Same as Param[1] on API 0x52
|
||||
Param[2]
|
||||
Same as Param[2] on API 0x52
|
||||
Param[3]
|
||||
width
|
||||
Param[4]
|
||||
height
|
||||
Param[5]
|
||||
destination pixel mask
|
||||
Param[6]
|
||||
destination rectangle start address
|
||||
Param[7]
|
||||
destination stride in dwords
|
||||
Param[8]
|
||||
source stride in dwords
|
||||
Param[9]
|
||||
source rectangle start address
|
||||
Param[10]
|
||||
color fill value
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_SET_FRAMEBUFFER_WINDOW
|
||||
Enum 86/0x56
|
||||
Description
|
||||
Positions the main output window on the screen. The coordinates must be
|
||||
such that the entire window fits on the screen.
|
||||
Param[0]
|
||||
window width
|
||||
Param[1]
|
||||
window height
|
||||
Param[2]
|
||||
top left window corner horizontal offset
|
||||
Param[3]
|
||||
top left window corner vertical offset
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_SET_CHROMA_KEY
|
||||
Enum 96/0x60
|
||||
Description
|
||||
Chroma key switch and color
|
||||
Param[0]
|
||||
state: 0=off, 1=on
|
||||
Param[1]
|
||||
color
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_GET_ALPHA_CONTENT_INDEX
|
||||
Enum 97/0x61
|
||||
Description
|
||||
Retrieve alpha content index
|
||||
Result[0]
|
||||
alpha content index, Range 0:15
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Name CX2341X_OSD_SET_ALPHA_CONTENT_INDEX
|
||||
Enum 98/0x62
|
||||
Description
|
||||
Assign alpha content index
|
||||
Param[0]
|
||||
alpha content index, range 0:15
|
||||
@@ -0,0 +1,49 @@
|
||||
This document describes how to upload the cx2341x firmware to the card.
|
||||
|
||||
How to find
|
||||
===========
|
||||
|
||||
See the web pages of the various projects that uses this chip for information
|
||||
on how to obtain the firmware.
|
||||
|
||||
The firmware stored in a Windows driver can be detected as follows:
|
||||
|
||||
- Each firmware image is 256k bytes.
|
||||
- The 1st 32-bit word of the Encoder image is 0x0000da7
|
||||
- The 1st 32-bit word of the Decoder image is 0x00003a7
|
||||
- The 2nd 32-bit word of both images is 0xaa55bb66
|
||||
|
||||
How to load
|
||||
===========
|
||||
|
||||
- Issue the FWapi command to stop the encoder if it is running. Wait for the
|
||||
command to complete.
|
||||
- Issue the FWapi command to stop the decoder if it is running. Wait for the
|
||||
command to complete.
|
||||
- Issue the I2C command to the digitizer to stop emitting VSYNC events.
|
||||
- Issue the FWapi command to halt the encoder's firmware.
|
||||
- Sleep for 10ms.
|
||||
- Issue the FWapi command to halt the decoder's firmware.
|
||||
- Sleep for 10ms.
|
||||
- Write 0x00000000 to register 0x2800 to stop the Video Display Module.
|
||||
- Write 0x00000005 to register 0x2D00 to stop the AO (audio output?).
|
||||
- Write 0x00000000 to register 0xA064 to ping? the APU.
|
||||
- Write 0xFFFFFFFE to register 0x9058 to stop the VPU.
|
||||
- Write 0xFFFFFFFF to register 0x9054 to reset the HW blocks.
|
||||
- Write 0x00000001 to register 0x9050 to stop the SPU.
|
||||
- Sleep for 10ms.
|
||||
- Write 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.
|
||||
- Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
|
||||
- Write 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.
|
||||
- Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
|
||||
- Sleep for 512ms. (600ms is recommended)
|
||||
- Transfer the encoder's firmware image to offset 0 in Encoder memory space.
|
||||
- Transfer the decoder's firmware image to offset 0 in Decoder memory space.
|
||||
- Use a read-modify-write operation to Clear bit 0 of register 0x9050 to
|
||||
re-enable the SPU.
|
||||
- Sleep for 1 second.
|
||||
- Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058
|
||||
to re-enable the VPU.
|
||||
- Sleep for 1 second.
|
||||
- Issue status API commands to both firmware images to verify.
|
||||
|
||||
@@ -0,0 +1,54 @@
|
||||
The controls for the mux are GPIO [0,1] for source, and GPIO 2 for muting.
|
||||
|
||||
GPIO0 GPIO1
|
||||
0 0 TV Audio
|
||||
1 0 FM radio
|
||||
0 1 Line-In
|
||||
1 1 Mono tuner bypass or CD passthru (tuner specific)
|
||||
|
||||
GPIO 16(i believe) is tied to the IR port (if present).
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
>From the data sheet:
|
||||
Register 24'h20004 PCI Interrupt Status
|
||||
bit [18] IR_SMP_INT Set when 32 input samples have been collected over
|
||||
gpio[16] pin into GP_SAMPLE register.
|
||||
|
||||
What's missing from the data sheet:
|
||||
|
||||
Setup 4KHz sampling rate (roughly 2x oversampled; good enough for our RC5
|
||||
compat remote)
|
||||
set register 0x35C050 to 0xa80a80
|
||||
|
||||
enable sampling
|
||||
set register 0x35C054 to 0x5
|
||||
|
||||
Of course, enable the IRQ bit 18 in the interrupt mask register .(and
|
||||
provide for a handler)
|
||||
|
||||
GP_SAMPLE register is at 0x35C058
|
||||
|
||||
Bits are then right shifted into the GP_SAMPLE register at the specified
|
||||
rate; you get an interrupt when a full DWORD is recieved.
|
||||
You need to recover the actual RC5 bits out of the (oversampled) IR sensor
|
||||
bits. (Hint: look for the 0/1and 1/0 crossings of the RC5 bi-phase data) An
|
||||
actual raw RC5 code will span 2-3 DWORDS, depending on the actual alignment.
|
||||
|
||||
I'm pretty sure when no IR signal is present the receiver is always in a
|
||||
marking state(1); but stray light, etc can cause intermittent noise values
|
||||
as well. Remember, this is a free running sample of the IR receiver state
|
||||
over time, so don't assume any sample starts at any particular place.
|
||||
|
||||
http://www.atmel.com/dyn/resources/prod_documents/doc2817.pdf
|
||||
This data sheet (google search) seems to have a lovely description of the
|
||||
RC5 basics
|
||||
|
||||
http://users.pandora.be/nenya/electronics/rc5/ and more data
|
||||
|
||||
http://www.ee.washington.edu/circuit_archive/text/ir_decode.txt
|
||||
and even a reference to how to decode a bi-phase data stream.
|
||||
|
||||
http://www.xs4all.nl/~sbp/knowledge/ir/rc5.htm
|
||||
still more info
|
||||
|
||||
Reference in New Issue
Block a user