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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs. A slew of changes this release cycle. The reset driver tree, that we merge through arm-soc for historical reasons, is also sizable this time around. Among the changes: - clps711x: Treewide changes to compatible strings, merged here for simplicity. - Qualcomm: SCM firmware driver cleanups, move to platform driver - ux500: Major cleanups, removal of old mach-specific infrastructure. - Atmel external bus memory driver - Move of brcmstb platform to the rest of bcm - PMC driver updates for tegra, various fixes and improvements - Samsung platform driver updates to support 64-bit Exynos platforms - Reset controller cleanups moving to devm_reset_controller_register() APIs - Reset controller driver for Amlogic Meson - Reset controller driver for Hisilicon hi6220 - ARM SCPI power domain support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (100 commits) ARM: ux500: consolidate base platform files ARM: ux500: move soc_id driver to drivers/soc ARM: ux500: call ux500_setup_id later ARM: ux500: consolidate soc_device code in id.c ARM: ux500: remove cpu_is_u* helpers ARM: ux500: use CLK_OF_DECLARE() ARM: ux500: move l2x0 init to .init_irq mfd: db8500 stop passing around platform data ASoC: ab8500-codec: remove platform data based probe ARM: ux500: move ab8500_regulator_plat_data into driver ARM: ux500: remove unused regulator data soc: raspberrypi-power: add CONFIG_OF dependency firmware: scpi: add CONFIG_OF dependency video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip pwm: clps711x: Changing the compatibility string to match with the smallest supported chip serial: clps711x: Changing the compatibility string to match with the smallest supported chip irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip clk: clps711x: Changing the compatibility string to match with the smallest supported chip ...
This commit is contained in:
Linus Torvalds
@@ -87,10 +87,33 @@ Required properties:
|
||||
implementation for the IDs to use. For Juno
|
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R0 and Juno R1 refer to [3].
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Power domain bindings for the power domains based on SCPI Message Protocol
|
||||
------------------------------------------------------------
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||||
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||||
This binding uses the generic power domain binding[4].
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||||
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||||
PM domain providers
|
||||
===================
|
||||
|
||||
Required properties:
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||||
- #power-domain-cells : Should be 1. Contains the device or the power
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domain ID value used by SCPI commands.
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- num-domains: Total number of power domains provided by SCPI. This is
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needed as the SCPI message protocol lacks a mechanism to
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query this information at runtime.
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PM domain consumers
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===================
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|
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Required properties:
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- power-domains : A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle.
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[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/thermal/thermal.txt
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[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
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[4] Documentation/devicetree/bindings/power/power_domain.txt
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Example:
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@@ -144,6 +167,12 @@ scpi_protocol: scpi@2e000000 {
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compatible = "arm,scpi-sensors";
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#thermal-sensor-cells = <1>;
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};
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scpi_devpd: scpi-power-domains {
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compatible = "arm,scpi-power-domains";
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num-domains = <2>;
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#power-domain-cells = <1>;
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};
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};
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cpu@0 {
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@@ -156,6 +185,7 @@ hdlcd@7ff60000 {
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...
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reg = <0 0x7ff60000 0 0x1000>;
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clocks = <&scpi_clk 4>;
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power-domains = <&scpi_devpd 1>;
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};
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thermal-zones {
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@@ -186,3 +216,7 @@ The thermal-sensors property in the soc_thermal node uses the
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temperature sensor provided by SCP firmware to setup a thermal
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zone. The ID "3" is the sensor identifier for the temperature sensor
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as used by the firmware.
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The num-domains property in scpi-power-domains domain specifies that
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SCPI provides 2 power domains. The hdlcd node uses the power domain with
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domain ID 1.
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@@ -0,0 +1,45 @@
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NVIDIA Tegra ACONNECT Bus
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The Tegra ACONNECT bus is an AXI switch which is used to connnect various
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components inside the Audio Processing Engine (APE). All CPU accesses to
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the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
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Required properties:
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- compatible: Must be "nvidia,tegra210-aconnect".
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- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
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and APE interface clock (TEGRA210_CLK_APB2APE).
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- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
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'clocks' entries.
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- power-domains: Must contain a phandle that points to the audio powergate
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(namely 'aud') for Tegra210.
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- #address-cells: The number of cells used to represent physical base addresses
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in the aconnect address space. Should be 1.
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- #size-cells: The number of cells used to represent the size of an address
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range in the aconnect address space. Should be 1.
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- ranges: Mapping of the aconnect address space to the CPU address space.
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All devices accessed via the ACONNNECT are described by child-nodes.
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Example:
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aconnect@702c0000 {
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compatible = "nvidia,tegra210-aconnect";
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clocks = <&tegra_car TEGRA210_CLK_APE>,
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<&tegra_car TEGRA210_CLK_APB2APE>;
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clock-names = "ape", "apb2ape";
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power-domains = <&pd_audio>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
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status = "disabled";
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child1 {
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...
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};
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child2 {
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...
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};
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||||
};
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@@ -1,7 +1,7 @@
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* Clock bindings for the Cirrus Logic CLPS711X CPUs
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Required properties:
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- compatible : Shall contain "cirrus,clps711x-clk".
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- compatible : Shall contain "cirrus,ep7209-clk".
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- reg : Address of the internal register set.
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- startup-frequency: Factory set CPU startup frequency in HZ.
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- #clock-cells : Should be <1>.
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@@ -13,7 +13,7 @@ for the full list of CLPS711X clock IDs.
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Example:
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clks: clks@80000000 {
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#clock-cells = <1>;
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compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
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compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
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reg = <0x80000000 0xc000>;
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startup-frequency = <73728000>;
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};
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@@ -1,7 +1,7 @@
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* Currus Logic CLPS711X Framebuffer
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Required properties:
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- compatible: Shall contain "cirrus,clps711x-fb".
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- compatible: Shall contain "cirrus,ep7209-fb".
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- reg : Physical base address and length of the controller's registers +
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location and size of the framebuffer memory.
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- clocks : phandle + clock specifier pair of the FB reference clock.
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@@ -18,7 +18,7 @@ Optional properties:
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||||
|
||||
Example:
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fb: fb@800002c0 {
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compatible = "cirrus,ep7312-fb", "cirrus,clps711x-fb";
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compatible = "cirrus,ep7312-fb", "cirrus,ep7209-fb";
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reg = <0x800002c0 0xd44>, <0x60000000 0xc000>;
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clocks = <&clks 2>;
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lcd-supply = <®5v0>;
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@@ -1,7 +1,7 @@
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* Cirrus Logic CLPS711X matrix keypad device tree bindings
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Required Properties:
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- compatible: Shall contain "cirrus,clps711x-keypad".
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- compatible: Shall contain "cirrus,ep7209-keypad".
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- row-gpios: List of GPIOs used as row lines.
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- poll-interval: Poll interval time in milliseconds.
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||||
- linux,keymap: The definition can be found at
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@@ -12,7 +12,7 @@ Optional Properties:
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|
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Example:
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keypad {
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compatible = "cirrus,ep7312-keypad", "cirrus,clps711x-keypad";
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compatible = "cirrus,ep7312-keypad", "cirrus,ep7209-keypad";
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autorepeat;
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poll-interval = <120>;
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row-gpios = <&porta 0 0>,
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|
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@@ -2,7 +2,7 @@ Cirrus Logic CLPS711X Interrupt Controller
|
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|
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Required properties:
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||||
|
||||
- compatible: Should be "cirrus,clps711x-intc".
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- compatible: Should be "cirrus,ep7209-intc".
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- reg: Specifies base physical address of the registers set.
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- interrupt-controller: Identifies the node as an interrupt controller.
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- #interrupt-cells: Specifies the number of cells needed to encode an
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@@ -34,7 +34,7 @@ ID Name Description
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||||
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Example:
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||||
intc: interrupt-controller {
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compatible = "cirrus,clps711x-intc";
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compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
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reg = <0x80000000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <1>;
|
||||
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||||
@@ -0,0 +1,20 @@
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||||
Device-Tree bindings for LIRC TX driver for Nokia N900(RX51)
|
||||
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Required properties:
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||||
- compatible: should be "nokia,n900-ir".
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- pwms: specifies PWM used for IR signal transmission.
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||||
Example node:
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pwm9: dmtimer-pwm@9 {
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compatible = "ti,omap-dmtimer-pwm";
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ti,timers = <&timer9>;
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ti,clock-source = <0x00>; /* timer_sys_ck */
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#pwm-cells = <3>;
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};
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ir: n900-ir {
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compatible = "nokia,n900-ir";
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pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
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};
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@@ -0,0 +1,136 @@
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* Device tree bindings for Atmel EBI
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The External Bus Interface (EBI) controller is a bus where you can connect
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asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs).
|
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The EBI provides a glue-less interface to asynchronous memories through the SMC
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(Static Memory Controller).
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|
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Required properties:
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- compatible: "atmel,at91sam9260-ebi"
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"atmel,at91sam9261-ebi"
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"atmel,at91sam9263-ebi0"
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"atmel,at91sam9263-ebi1"
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"atmel,at91sam9rl-ebi"
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"atmel,at91sam9g45-ebi"
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"atmel,at91sam9x5-ebi"
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"atmel,sama5d3-ebi"
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- reg: Contains offset/length value for EBI memory mapping.
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This property might contain several entries if the EBI
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memory range is not contiguous
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- #address-cells: Must be 2.
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The first cell encodes the CS.
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The second cell encode the offset into the CS memory
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range.
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- #size-cells: Must be set to 1.
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- ranges: Encodes CS to memory region association.
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- clocks: Clock feeding the EBI controller.
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See clock-bindings.txt
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Children device nodes are representing device connected to the EBI bus.
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Required device node properties:
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- reg: Contains the chip-select id, the offset and the length
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of the memory region requested by the device.
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EBI bus configuration will be defined directly in the device subnode.
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Optional EBI/SMC properties:
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- atmel,smc-bus-width: width of the asynchronous device's data bus
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8, 16 or 32.
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Default to 8 when undefined.
|
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- atmel,smc-byte-access-type "write" or "select" (see Atmel datasheet).
|
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Default to "select" when undefined.
|
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|
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- atmel,smc-read-mode "nrd" or "ncs".
|
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Default to "ncs" when undefined.
|
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|
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- atmel,smc-write-mode "nwe" or "ncs".
|
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Default to "ncs" when undefined.
|
||||
|
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- atmel,smc-exnw-mode "disabled", "frozen" or "ready".
|
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Default to "disabled" when undefined.
|
||||
|
||||
- atmel,smc-page-mode enable page mode if present. The provided value
|
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defines the page size (supported values: 4, 8,
|
||||
16 and 32).
|
||||
|
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- atmel,smc-tdf-mode: "normal" or "optimized". When set to
|
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"optimized" the data float time is optimized
|
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depending on the next device being accessed
|
||||
(next device setup time is subtracted to the
|
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current device data float time).
|
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Default to "normal" when undefined.
|
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|
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If at least one atmel,smc- property is defined the following SMC timing
|
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properties become mandatory. In the other hand, if none of the atmel,smc-
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properties are specified, we assume that the EBI bus configuration will be
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handled by the sub-device driver, and none of those properties should be
|
||||
defined.
|
||||
|
||||
All the timings are expressed in nanoseconds (see Atmel datasheet for a full
|
||||
description).
|
||||
|
||||
- atmel,smc-ncs-rd-setup-ns
|
||||
- atmel,smc-nrd-setup-ns
|
||||
- atmel,smc-ncs-wr-setup-ns
|
||||
- atmel,smc-nwe-setup-ns
|
||||
- atmel,smc-ncs-rd-pulse-ns
|
||||
- atmel,smc-nrd-pulse-ns
|
||||
- atmel,smc-ncs-wr-pulse-ns
|
||||
- atmel,smc-nwe-pulse-ns
|
||||
- atmel,smc-nwe-cycle-ns
|
||||
- atmel,smc-nrd-cycle-ns
|
||||
- atmel,smc-tdf-ns
|
||||
|
||||
Example:
|
||||
|
||||
ebi: ebi@10000000 {
|
||||
compatible = "atmel,sama5d3-ebi";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
atmel,smc = <&hsmc>;
|
||||
atmel,matrix = <&matrix>;
|
||||
reg = <0x10000000 0x10000000
|
||||
0x40000000 0x30000000>;
|
||||
ranges = <0x0 0x0 0x10000000 0x10000000
|
||||
0x1 0x0 0x40000000 0x10000000
|
||||
0x2 0x0 0x50000000 0x10000000
|
||||
0x3 0x0 0x60000000 0x10000000>;
|
||||
clocks = <&mck>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ebi_addr>;
|
||||
|
||||
nor: flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0x0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
|
||||
atmel,smc-read-mode = "nrd";
|
||||
atmel,smc-write-mode = "nwe";
|
||||
atmel,smc-bus-width = <16>;
|
||||
atmel,smc-ncs-rd-setup-ns = <0>;
|
||||
atmel,smc-ncs-wr-setup-ns = <0>;
|
||||
atmel,smc-nwe-setup-ns = <8>;
|
||||
atmel,smc-nrd-setup-ns = <16>;
|
||||
atmel,smc-ncs-rd-pulse-ns = <84>;
|
||||
atmel,smc-ncs-wr-pulse-ns = <84>;
|
||||
atmel,smc-nrd-pulse-ns = <76>;
|
||||
atmel,smc-nwe-pulse-ns = <76>;
|
||||
atmel,smc-nrd-cycle-ns = <107>;
|
||||
atmel,smc-nwe-cycle-ns = <84>;
|
||||
atmel,smc-tdf-ns = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -1,15 +1,14 @@
|
||||
* Cirris Logic CLPS711X PWM controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall contain "cirrus,clps711x-pwm".
|
||||
- compatible: Shall contain "cirrus,ep7209-pwm".
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- clocks: phandle + clock specifier pair of the PWM reference clock.
|
||||
- #pwm-cells: Should be 1. The cell specifies the index of the channel.
|
||||
|
||||
Example:
|
||||
pwm: pwm@80000400 {
|
||||
compatible = "cirrus,ep7312-pwm",
|
||||
"cirrus,clps711x-pwm";
|
||||
compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm";
|
||||
reg = <0x80000400 0x4>;
|
||||
clocks = <&clks 8>;
|
||||
#pwm-cells = <1>;
|
||||
|
||||
@@ -9,6 +9,10 @@ Required properties:
|
||||
|
||||
Optional properties:
|
||||
- ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
|
||||
- ti,clock-source: Set dmtimer parent clock, values between 0 and 2:
|
||||
- 0x00 - high-frequency system clock (timer_sys_ck)
|
||||
- 0x01 - 32-kHz always-on clock (timer_32k_ck)
|
||||
- 0x02 - external clock (timer_ext_ck, OMAP2 only)
|
||||
|
||||
Example:
|
||||
pwm9: dmtimer-pwm@9 {
|
||||
|
||||
@@ -0,0 +1,18 @@
|
||||
Amlogic Meson SoC Reset Controller
|
||||
=======================================
|
||||
|
||||
Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "amlogic,meson8b-reset" or "amlogic,meson-gxbb-reset"
|
||||
- reg: should contain the register address base
|
||||
- #reset-cells: 1, see below
|
||||
|
||||
example:
|
||||
|
||||
reset: reset-controller {
|
||||
compatible = "amlogic,meson-gxbb-reset";
|
||||
reg = <0x0 0x04404 0x0 0x20>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -8,7 +8,9 @@ The reset controller registers are part of the system-ctl block on
|
||||
hi6220 SoC.
|
||||
|
||||
Required properties:
|
||||
- compatible: may be "hisilicon,hi6220-sysctrl"
|
||||
- compatible: should be one of the following:
|
||||
- "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
|
||||
- "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- #reset-cells: 1, see below
|
||||
|
||||
@@ -0,0 +1,91 @@
|
||||
TI SysCon Reset Controller
|
||||
=======================
|
||||
|
||||
Almost all SoCs have hardware modules that require reset control in addition
|
||||
to clock and power control for their functionality. The reset control is
|
||||
typically provided by means of memory-mapped I/O registers. These registers are
|
||||
sometimes a part of a larger register space region implementing various
|
||||
functionalities. This register range is best represented as a syscon node to
|
||||
allow multiple entities to access their relevant registers in the common
|
||||
register space.
|
||||
|
||||
A SysCon Reset Controller node defines a device that uses a syscon node
|
||||
and provides reset management functionality for various hardware modules
|
||||
present on the SoC.
|
||||
|
||||
SysCon Reset Controller Node
|
||||
============================
|
||||
Each of the reset provider/controller nodes should be a child of a syscon
|
||||
node and have the following properties.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- compatible : Should be,
|
||||
"ti,k2e-pscrst"
|
||||
"ti,k2l-pscrst"
|
||||
"ti,k2hk-pscrst"
|
||||
"ti,syscon-reset"
|
||||
- #reset-cells : Should be 1. Please see the reset consumer node below
|
||||
for usage details
|
||||
- ti,reset-bits : Contains the reset control register information
|
||||
Should contain 7 cells for each reset exposed to
|
||||
consumers, defined as:
|
||||
Cell #1 : offset of the reset assert control
|
||||
register from the syscon register base
|
||||
Cell #2 : bit position of the reset in the reset
|
||||
assert control register
|
||||
Cell #3 : offset of the reset deassert control
|
||||
register from the syscon register base
|
||||
Cell #4 : bit position of the reset in the reset
|
||||
deassert control register
|
||||
Cell #5 : offset of the reset status register
|
||||
from the syscon register base
|
||||
Cell #6 : bit position of the reset in the
|
||||
reset status register
|
||||
Cell #7 : Flags used to control reset behavior,
|
||||
availible flags defined in the DT include
|
||||
file <dt-bindings/reset/ti-syscon.h>
|
||||
|
||||
SysCon Reset Consumer Nodes
|
||||
===========================
|
||||
Each of the reset consumer nodes should have the following properties,
|
||||
in addition to their own properties.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- resets : A phandle to the reset controller node and an index number
|
||||
to a reset specifier as defined above.
|
||||
|
||||
Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
|
||||
common reset controller usage by consumers.
|
||||
|
||||
Example:
|
||||
--------
|
||||
The following example demonstrates a syscon node, the reset controller node
|
||||
using the syscon node, and a consumer (a DSP device) on the TI Keystone 2
|
||||
Edison SoC.
|
||||
|
||||
/ {
|
||||
soc {
|
||||
psc: power-sleep-controller@02350000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x02350000 0x1000>;
|
||||
|
||||
pscrst: psc-reset {
|
||||
compatible = "ti,k2e-pscrst", "ti,syscon-reset";
|
||||
#reset-cells = <1>;
|
||||
|
||||
ti,reset-bits = <
|
||||
0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET) /* 0: pcrst-dsp0 */
|
||||
0xa40 5 0xa44 3 0 0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE) /* 1: pcrst-example */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
dsp0: dsp0 {
|
||||
...
|
||||
resets = <&pscrst 0>;
|
||||
...
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,7 +1,7 @@
|
||||
* Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "cirrus,clps711x-uart".
|
||||
- compatible: Should be "cirrus,ep7209-uart".
|
||||
- reg: Address and length of the register set for the device.
|
||||
- interrupts: Should contain UART TX and RX interrupt.
|
||||
- clocks: Should contain UART core clock number.
|
||||
@@ -20,7 +20,7 @@ Example:
|
||||
};
|
||||
|
||||
uart1: uart@80000480 {
|
||||
compatible = "cirrus,clps711x-uart";
|
||||
compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart";
|
||||
reg = <0x80000480 0x80>;
|
||||
interrupts = <12 13>;
|
||||
clocks = <&clks 11>;
|
||||
|
||||
@@ -68,7 +68,7 @@ important.
|
||||
Value type: <u32>
|
||||
Definition: must be 2 - denoting the bit in the entry and IRQ flags
|
||||
|
||||
- #qcom,state-cells:
|
||||
- #qcom,smem-state-cells:
|
||||
Usage: required for outgoing entries
|
||||
Value type: <u32>
|
||||
Definition: must be 1 - denoting the bit in the entry
|
||||
@@ -92,7 +92,7 @@ wcnss-smp2p {
|
||||
wcnss_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
|
||||
#qcom,state-cells = <1>;
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
wcnss_smp2p_in: slave-kernel {
|
||||
|
||||
@@ -51,7 +51,7 @@ important.
|
||||
Definition: specifies the offset, in words, of the first bit for this
|
||||
entry
|
||||
|
||||
- #qcom,state-cells:
|
||||
- #qcom,smem-state-cells:
|
||||
Usage: required for local entry
|
||||
Value type: <u32>
|
||||
Definition: must be 1 - denotes bit number
|
||||
@@ -91,7 +91,7 @@ smsm {
|
||||
apps_smsm: apps@0 {
|
||||
reg = <0>;
|
||||
|
||||
#qcom,state-cells = <1>;
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
wcnss_smsm: wcnss@7 {
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
* Cirrus Logic CLPS711X Timer Counter
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall contain "cirrus,clps711x-timer".
|
||||
- compatible: Shall contain "cirrus,ep7209-timer".
|
||||
- reg : Address and length of the register set.
|
||||
- interrupts: The interrupt number of the timer.
|
||||
- clocks : phandle of timer reference clock.
|
||||
@@ -15,14 +15,14 @@ Example:
|
||||
};
|
||||
|
||||
timer1: timer@80000300 {
|
||||
compatible = "cirrus,ep7312-timer", "cirrus,clps711x-timer";
|
||||
compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
|
||||
reg = <0x80000300 0x4>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks 5>;
|
||||
};
|
||||
|
||||
timer2: timer@80000340 {
|
||||
compatible = "cirrus,ep7312-timer", "cirrus,clps711x-timer";
|
||||
compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
|
||||
reg = <0x80000340 0x4>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clks 6>;
|
||||
|
||||
@@ -352,6 +352,10 @@ REGULATOR
|
||||
devm_regulator_put()
|
||||
devm_regulator_register()
|
||||
|
||||
RESET
|
||||
devm_reset_control_get()
|
||||
devm_reset_controller_register()
|
||||
|
||||
SLAVE DMA ENGINE
|
||||
devm_acpi_dma_controller_register()
|
||||
|
||||
|
||||
+1
-1
@@ -1536,6 +1536,7 @@ M: David Brown <david.brown@linaro.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
L: linux-soc@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/soc/qcom/
|
||||
F: arch/arm/boot/dts/qcom-*.dts
|
||||
F: arch/arm/boot/dts/qcom-*.dtsi
|
||||
F: arch/arm/mach-qcom/
|
||||
@@ -1841,7 +1842,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
T: git git://git.linaro.org/people/ulfh/clk.git
|
||||
S: Maintained
|
||||
F: drivers/clk/ux500/
|
||||
F: include/linux/platform_data/clk-ux500.h
|
||||
|
||||
ARM/VERSATILE EXPRESS PLATFORM
|
||||
M: Liviu Dudau <liviu.dudau@arm.com>
|
||||
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition.
|
||||
*
|
||||
* Copyright (c) 2016 Samsung Electronics Co., Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mfc_left: region@51000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
no-map;
|
||||
reg = <0x51000000 0x800000>;
|
||||
};
|
||||
|
||||
mfc_right: region@43000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
no-map;
|
||||
reg = <0x43000000 0x800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user