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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem
This commit is contained in:
+8
-2
@@ -4097,6 +4097,12 @@ S: Maintained
|
||||
F: drivers/net/mv643xx_eth.*
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||||
F: include/linux/mv643xx.h
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||||
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MARVELL MWIFIEX WIRELESS DRIVER
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M: Bing Zhao <bzhao@marvell.com>
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||||
L: linux-wireless@vger.kernel.org
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S: Maintained
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F: drivers/net/wireless/mwifiex/
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MARVELL MWL8K WIRELESS DRIVER
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M: Lennert Buytenhek <buytenh@wantstofly.org>
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L: linux-wireless@vger.kernel.org
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@@ -6938,9 +6944,9 @@ S: Maintained
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F: drivers/input/misc/wistron_btns.c
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WL1251 WIRELESS DRIVER
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M: Kalle Valo <kvalo@adurom.com>
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M: Luciano Coelho <coelho@ti.com>
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L: linux-wireless@vger.kernel.org
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W: http://wireless.kernel.org
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W: http://wireless.kernel.org/en/users/Drivers/wl1251
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git
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S: Maintained
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F: drivers/net/wireless/wl1251/*
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@@ -50,3 +50,75 @@ int bcma_core_enable(struct bcma_device *core, u32 flags)
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return 0;
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}
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EXPORT_SYMBOL_GPL(bcma_core_enable);
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void bcma_core_set_clockmode(struct bcma_device *core,
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enum bcma_clkmode clkmode)
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{
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u16 i;
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WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON &&
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core->id.id != BCMA_CORE_PCIE &&
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core->id.id != BCMA_CORE_80211);
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switch (clkmode) {
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case BCMA_CLKMODE_FAST:
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bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
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udelay(64);
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for (i = 0; i < 1500; i++) {
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if (bcma_read32(core, BCMA_CLKCTLST) &
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BCMA_CLKCTLST_HAVEHT) {
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i = 0;
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break;
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}
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udelay(10);
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}
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if (i)
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pr_err("HT force timeout\n");
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break;
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case BCMA_CLKMODE_DYNAMIC:
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pr_warn("Dynamic clockmode not supported yet!\n");
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break;
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}
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}
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EXPORT_SYMBOL_GPL(bcma_core_set_clockmode);
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void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on)
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{
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u16 i;
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WARN_ON(req & ~BCMA_CLKCTLST_EXTRESREQ);
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WARN_ON(status & ~BCMA_CLKCTLST_EXTRESST);
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if (on) {
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bcma_set32(core, BCMA_CLKCTLST, req);
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for (i = 0; i < 10000; i++) {
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if ((bcma_read32(core, BCMA_CLKCTLST) & status) ==
|
||||
status) {
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i = 0;
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break;
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}
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udelay(10);
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}
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if (i)
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pr_err("PLL enable timeout\n");
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} else {
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pr_warn("Disabling PLL not supported yet!\n");
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}
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}
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EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
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u32 bcma_core_dma_translation(struct bcma_device *core)
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{
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switch (core->bus->hosttype) {
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case BCMA_HOSTTYPE_PCI:
|
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if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64)
|
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return BCMA_DMA_TRANSLATION_DMA64_CMT;
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else
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return BCMA_DMA_TRANSLATION_DMA32_CMT;
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default:
|
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pr_err("DMA translation unknown for host %d\n",
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core->bus->hosttype);
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}
|
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return BCMA_DMA_TRANSLATION_NONE;
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}
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EXPORT_SYMBOL(bcma_core_dma_translation);
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@@ -23,6 +23,9 @@ static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
|
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|
||||
void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
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{
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u32 leddc_on = 10;
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u32 leddc_off = 90;
|
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|
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if (cc->core->id.rev >= 11)
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cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
|
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cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
|
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@@ -38,6 +41,17 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
|
||||
bcma_pmu_init(cc);
|
||||
if (cc->capabilities & BCMA_CC_CAP_PCTL)
|
||||
pr_err("Power control not implemented!\n");
|
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|
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if (cc->core->id.rev >= 16) {
|
||||
if (cc->core->bus->sprom.leddc_on_time &&
|
||||
cc->core->bus->sprom.leddc_off_time) {
|
||||
leddc_on = cc->core->bus->sprom.leddc_on_time;
|
||||
leddc_off = cc->core->bus->sprom.leddc_off_time;
|
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}
|
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bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
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((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
|
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(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
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||||
}
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||||
}
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||||
|
||||
/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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|
||||
@@ -172,8 +172,10 @@ static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
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chipid_top != 0x5300)
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return false;
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|
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#ifdef CONFIG_SSB_DRIVER_PCICORE
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if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
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return false;
|
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#endif /* CONFIG_SSB_DRIVER_PCICORE */
|
||||
|
||||
#if 0
|
||||
/* TODO: on BCMA we use address from EROM instead of magic formula */
|
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|
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+10
-4
@@ -20,12 +20,12 @@
|
||||
* R/W ops.
|
||||
**************************************************/
|
||||
|
||||
static void bcma_sprom_read(struct bcma_bus *bus, u16 *sprom)
|
||||
static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
|
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{
|
||||
int i;
|
||||
for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
|
||||
sprom[i] = bcma_read16(bus->drv_cc.core,
|
||||
BCMA_CC_SPROM + (i * 2));
|
||||
offset + (i * 2));
|
||||
}
|
||||
|
||||
/**************************************************
|
||||
@@ -112,7 +112,7 @@ static int bcma_sprom_valid(const u16 *sprom)
|
||||
return err;
|
||||
|
||||
revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
|
||||
if (revision != 8) {
|
||||
if (revision != 8 && revision != 9) {
|
||||
pr_err("Unsupported SPROM revision: %d\n", revision);
|
||||
return -ENOENT;
|
||||
}
|
||||
@@ -137,6 +137,7 @@ static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
|
||||
|
||||
int bcma_sprom_get(struct bcma_bus *bus)
|
||||
{
|
||||
u16 offset;
|
||||
u16 *sprom;
|
||||
int err = 0;
|
||||
|
||||
@@ -151,7 +152,12 @@ int bcma_sprom_get(struct bcma_bus *bus)
|
||||
if (!sprom)
|
||||
return -ENOMEM;
|
||||
|
||||
bcma_sprom_read(bus, sprom);
|
||||
/* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
|
||||
* According to brcm80211 this applies to cards with PCIe rev >= 6
|
||||
* TODO: understand this condition and use it */
|
||||
offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
|
||||
BCMA_CC_SPROM_PCIE6;
|
||||
bcma_sprom_read(bus, offset, sprom);
|
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|
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err = bcma_sprom_valid(sprom);
|
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if (err)
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@@ -35,8 +35,8 @@ static void ath5k_ahb_read_cachesize(struct ath_common *common, int *csz)
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static bool
|
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ath5k_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
|
||||
{
|
||||
struct ath5k_softc *sc = common->priv;
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struct platform_device *pdev = to_platform_device(sc->dev);
|
||||
struct ath5k_hw *ah = common->priv;
|
||||
struct platform_device *pdev = to_platform_device(ah->dev);
|
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struct ar231x_board_config *bcfg = pdev->dev.platform_data;
|
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u16 *eeprom, *eeprom_end;
|
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|
||||
@@ -56,8 +56,7 @@ ath5k_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
|
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|
||||
int ath5k_hw_read_srev(struct ath5k_hw *ah)
|
||||
{
|
||||
struct ath5k_softc *sc = ah->ah_sc;
|
||||
struct platform_device *pdev = to_platform_device(sc->dev);
|
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struct platform_device *pdev = to_platform_device(ah->dev);
|
||||
struct ar231x_board_config *bcfg = pdev->dev.platform_data;
|
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ah->ah_mac_srev = bcfg->devid;
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return 0;
|
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@@ -65,12 +64,11 @@ int ath5k_hw_read_srev(struct ath5k_hw *ah)
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|
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static int ath5k_ahb_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
|
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{
|
||||
struct ath5k_softc *sc = ah->ah_sc;
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struct platform_device *pdev = to_platform_device(sc->dev);
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struct platform_device *pdev = to_platform_device(ah->dev);
|
||||
struct ar231x_board_config *bcfg = pdev->dev.platform_data;
|
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u8 *cfg_mac;
|
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|
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if (to_platform_device(sc->dev)->id == 0)
|
||||
if (to_platform_device(ah->dev)->id == 0)
|
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cfg_mac = bcfg->config->wlan0_mac;
|
||||
else
|
||||
cfg_mac = bcfg->config->wlan1_mac;
|
||||
@@ -90,7 +88,7 @@ static const struct ath_bus_ops ath_ahb_bus_ops = {
|
||||
static int ath_ahb_probe(struct platform_device *pdev)
|
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{
|
||||
struct ar231x_board_config *bcfg = pdev->dev.platform_data;
|
||||
struct ath5k_softc *sc;
|
||||
struct ath5k_hw *ah;
|
||||
struct ieee80211_hw *hw;
|
||||
struct resource *res;
|
||||
void __iomem *mem;
|
||||
@@ -127,19 +125,19 @@ static int ath_ahb_probe(struct platform_device *pdev)
|
||||
|
||||
irq = res->start;
|
||||
|
||||
hw = ieee80211_alloc_hw(sizeof(struct ath5k_softc), &ath5k_hw_ops);
|
||||
hw = ieee80211_alloc_hw(sizeof(struct ath5k_hw), &ath5k_hw_ops);
|
||||
if (hw == NULL) {
|
||||
dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
|
||||
ret = -ENOMEM;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
sc = hw->priv;
|
||||
sc->hw = hw;
|
||||
sc->dev = &pdev->dev;
|
||||
sc->iobase = mem;
|
||||
sc->irq = irq;
|
||||
sc->devid = bcfg->devid;
|
||||
ah = hw->priv;
|
||||
ah->hw = hw;
|
||||
ah->dev = &pdev->dev;
|
||||
ah->iobase = mem;
|
||||
ah->irq = irq;
|
||||
ah->devid = bcfg->devid;
|
||||
|
||||
if (bcfg->devid >= AR5K_SREV_AR2315_R6) {
|
||||
/* Enable WMAC AHB arbitration */
|
||||
@@ -155,7 +153,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
|
||||
/* Enable WMAC DMA access (assuming 5312 or 231x*/
|
||||
/* TODO: check other platforms */
|
||||
reg = __raw_readl((void __iomem *) AR5K_AR5312_ENABLE);
|
||||
if (to_platform_device(sc->dev)->id == 0)
|
||||
if (to_platform_device(ah->dev)->id == 0)
|
||||
reg |= AR5K_AR5312_ENABLE_WLAN0;
|
||||
else
|
||||
reg |= AR5K_AR5312_ENABLE_WLAN1;
|
||||
@@ -166,13 +164,13 @@ static int ath_ahb_probe(struct platform_device *pdev)
|
||||
* used as pass-through. Disable 2 GHz support in the
|
||||
* driver for it
|
||||
*/
|
||||
if (to_platform_device(sc->dev)->id == 0 &&
|
||||
if (to_platform_device(ah->dev)->id == 0 &&
|
||||
(bcfg->config->flags & (BD_WLAN0 | BD_WLAN1)) ==
|
||||
(BD_WLAN1 | BD_WLAN0))
|
||||
__set_bit(ATH_STAT_2G_DISABLED, sc->status);
|
||||
__set_bit(ATH_STAT_2G_DISABLED, ah->status);
|
||||
}
|
||||
|
||||
ret = ath5k_init_softc(sc, &ath_ahb_bus_ops);
|
||||
ret = ath5k_init_softc(ah, &ath_ahb_bus_ops);
|
||||
if (ret != 0) {
|
||||
dev_err(&pdev->dev, "failed to attach device, err=%d\n", ret);
|
||||
ret = -ENODEV;
|
||||
@@ -194,13 +192,13 @@ static int ath_ahb_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct ar231x_board_config *bcfg = pdev->dev.platform_data;
|
||||
struct ieee80211_hw *hw = platform_get_drvdata(pdev);
|
||||
struct ath5k_softc *sc;
|
||||
struct ath5k_hw *ah;
|
||||
u32 reg;
|
||||
|
||||
if (!hw)
|
||||
return 0;
|
||||
|
||||
sc = hw->priv;
|
||||
ah = hw->priv;
|
||||
|
||||
if (bcfg->devid >= AR5K_SREV_AR2315_R6) {
|
||||
/* Disable WMAC AHB arbitration */
|
||||
@@ -210,14 +208,14 @@ static int ath_ahb_remove(struct platform_device *pdev)
|
||||
} else {
|
||||
/*Stop DMA access */
|
||||
reg = __raw_readl((void __iomem *) AR5K_AR5312_ENABLE);
|
||||
if (to_platform_device(sc->dev)->id == 0)
|
||||
if (to_platform_device(ah->dev)->id == 0)
|
||||
reg &= ~AR5K_AR5312_ENABLE_WLAN0;
|
||||
else
|
||||
reg &= ~AR5K_AR5312_ENABLE_WLAN1;
|
||||
__raw_writel(reg, (void __iomem *) AR5K_AR5312_ENABLE);
|
||||
}
|
||||
|
||||
ath5k_deinit_softc(sc);
|
||||
ath5k_deinit_softc(ah);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
ieee80211_free_hw(hw);
|
||||
|
||||
|
||||
@@ -74,7 +74,7 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
|
||||
static const s8 fr[] = { -78, -80 };
|
||||
#endif
|
||||
if (level < 0 || level >= ARRAY_SIZE(sz)) {
|
||||
ATH5K_ERR(ah->ah_sc, "noise immunity level %d out of range",
|
||||
ATH5K_ERR(ah, "noise immunity level %d out of range",
|
||||
level);
|
||||
return;
|
||||
}
|
||||
@@ -88,8 +88,8 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
|
||||
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
|
||||
AR5K_PHY_SIG_FIRPWR, fr[level]);
|
||||
|
||||
ah->ah_sc->ani_state.noise_imm_level = level;
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level);
|
||||
ah->ani_state.noise_imm_level = level;
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
|
||||
}
|
||||
|
||||
|
||||
@@ -105,8 +105,8 @@ ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
|
||||
static const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
|
||||
|
||||
if (level < 0 || level >= ARRAY_SIZE(val) ||
|
||||
level > ah->ah_sc->ani_state.max_spur_level) {
|
||||
ATH5K_ERR(ah->ah_sc, "spur immunity level %d out of range",
|
||||
level > ah->ani_state.max_spur_level) {
|
||||
ATH5K_ERR(ah, "spur immunity level %d out of range",
|
||||
level);
|
||||
return;
|
||||
}
|
||||
@@ -114,8 +114,8 @@ ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
|
||||
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
|
||||
AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, val[level]);
|
||||
|
||||
ah->ah_sc->ani_state.spur_level = level;
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level);
|
||||
ah->ani_state.spur_level = level;
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
|
||||
}
|
||||
|
||||
|
||||
@@ -130,15 +130,15 @@ ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
|
||||
static const int val[] = { 0, 4, 8 };
|
||||
|
||||
if (level < 0 || level >= ARRAY_SIZE(val)) {
|
||||
ATH5K_ERR(ah->ah_sc, "firstep level %d out of range", level);
|
||||
ATH5K_ERR(ah, "firstep level %d out of range", level);
|
||||
return;
|
||||
}
|
||||
|
||||
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
|
||||
AR5K_PHY_SIG_FIRSTEP, val[level]);
|
||||
|
||||
ah->ah_sc->ani_state.firstep_level = level;
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level);
|
||||
ah->ani_state.firstep_level = level;
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
|
||||
}
|
||||
|
||||
|
||||
@@ -178,8 +178,8 @@ ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
|
||||
AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
|
||||
AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN);
|
||||
|
||||
ah->ah_sc->ani_state.ofdm_weak_sig = on;
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s",
|
||||
ah->ani_state.ofdm_weak_sig = on;
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "turned %s",
|
||||
on ? "on" : "off");
|
||||
}
|
||||
|
||||
@@ -195,8 +195,8 @@ ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
|
||||
static const int val[] = { 8, 6 };
|
||||
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR,
|
||||
AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]);
|
||||
ah->ah_sc->ani_state.cck_weak_sig = on;
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s",
|
||||
ah->ani_state.cck_weak_sig = on;
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "turned %s",
|
||||
on ? "on" : "off");
|
||||
}
|
||||
|
||||
@@ -218,7 +218,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
|
||||
{
|
||||
int rssi = ewma_read(&ah->ah_beacon_rssi_avg);
|
||||
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "raise immunity (%s)",
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "raise immunity (%s)",
|
||||
ofdm_trigger ? "ODFM" : "CCK");
|
||||
|
||||
/* first: raise noise immunity */
|
||||
@@ -229,13 +229,13 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
|
||||
|
||||
/* only OFDM: raise spur immunity level */
|
||||
if (ofdm_trigger &&
|
||||
as->spur_level < ah->ah_sc->ani_state.max_spur_level) {
|
||||
as->spur_level < ah->ani_state.max_spur_level) {
|
||||
ath5k_ani_set_spur_immunity_level(ah, as->spur_level + 1);
|
||||
return;
|
||||
}
|
||||
|
||||
/* AP mode */
|
||||
if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) {
|
||||
if (ah->opmode == NL80211_IFTYPE_AP) {
|
||||
if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL)
|
||||
ath5k_ani_set_firstep_level(ah, as->firstep_level + 1);
|
||||
return;
|
||||
@@ -248,7 +248,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
|
||||
* don't shut out a remote node by raising immunity too high. */
|
||||
|
||||
if (rssi > ATH5K_ANI_RSSI_THR_HIGH) {
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
|
||||
"beacon RSSI high");
|
||||
/* only OFDM: beacon RSSI is high, we can disable ODFM weak
|
||||
* signal detection */
|
||||
@@ -265,7 +265,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
|
||||
} else if (rssi > ATH5K_ANI_RSSI_THR_LOW) {
|
||||
/* beacon RSSI in mid range, we need OFDM weak signal detect,
|
||||
* but can raise firstep level */
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
|
||||
"beacon RSSI mid");
|
||||
if (ofdm_trigger && as->ofdm_weak_sig == false)
|
||||
ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
|
||||
@@ -275,7 +275,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
|
||||
} else if (ah->ah_current_channel->band == IEEE80211_BAND_2GHZ) {
|
||||
/* beacon RSSI is low. in B/G mode turn of OFDM weak signal
|
||||
* detect and zero firstep level to maximize CCK sensitivity */
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
|
||||
"beacon RSSI low, 2GHz");
|
||||
if (ofdm_trigger && as->ofdm_weak_sig == true)
|
||||
ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
|
||||
@@ -303,9 +303,9 @@ ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
|
||||
{
|
||||
int rssi = ewma_read(&ah->ah_beacon_rssi_avg);
|
||||
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "lower immunity");
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "lower immunity");
|
||||
|
||||
if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) {
|
||||
if (ah->opmode == NL80211_IFTYPE_AP) {
|
||||
/* AP mode */
|
||||
if (as->firstep_level > 0) {
|
||||
ath5k_ani_set_firstep_level(ah, as->firstep_level - 1);
|
||||
@@ -464,7 +464,7 @@ ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as)
|
||||
void
|
||||
ath5k_ani_calibration(struct ath5k_hw *ah)
|
||||
{
|
||||
struct ath5k_ani_state *as = &ah->ah_sc->ani_state;
|
||||
struct ath5k_ani_state *as = &ah->ani_state;
|
||||
int listen, ofdm_high, ofdm_low, cck_high, cck_low;
|
||||
|
||||
/* get listen time since last call and add it to the counter because we
|
||||
@@ -483,9 +483,9 @@ ath5k_ani_calibration(struct ath5k_hw *ah)
|
||||
ofdm_low = as->listen_time * ATH5K_ANI_OFDM_TRIG_LOW / 1000;
|
||||
cck_low = as->listen_time * ATH5K_ANI_CCK_TRIG_LOW / 1000;
|
||||
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
|
||||
"listen %d (now %d)", as->listen_time, listen);
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
|
||||
"check high ofdm %d/%d cck %d/%d",
|
||||
as->ofdm_errors, ofdm_high, as->cck_errors, cck_high);
|
||||
|
||||
@@ -498,7 +498,7 @@ ath5k_ani_calibration(struct ath5k_hw *ah)
|
||||
} else if (as->listen_time > 5 * ATH5K_ANI_LISTEN_PERIOD) {
|
||||
/* If more than 5 (TODO: why 5?) periods have passed and we got
|
||||
* relatively little errors we can try to lower immunity */
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
|
||||
"check low ofdm %d/%d cck %d/%d",
|
||||
as->ofdm_errors, ofdm_low, as->cck_errors, cck_low);
|
||||
|
||||
@@ -525,7 +525,7 @@ ath5k_ani_calibration(struct ath5k_hw *ah)
|
||||
void
|
||||
ath5k_ani_mib_intr(struct ath5k_hw *ah)
|
||||
{
|
||||
struct ath5k_ani_state *as = &ah->ah_sc->ani_state;
|
||||
struct ath5k_ani_state *as = &ah->ani_state;
|
||||
|
||||
/* nothing to do here if HW does not have PHY error counters - they
|
||||
* can't be the reason for the MIB interrupt then */
|
||||
@@ -536,7 +536,7 @@ ath5k_ani_mib_intr(struct ath5k_hw *ah)
|
||||
ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
|
||||
ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
|
||||
|
||||
if (ah->ah_sc->ani_state.ani_mode != ATH5K_ANI_MODE_AUTO)
|
||||
if (ah->ani_state.ani_mode != ATH5K_ANI_MODE_AUTO)
|
||||
return;
|
||||
|
||||
/* If one of the errors triggered, we can get a superfluous second
|
||||
@@ -547,7 +547,7 @@ ath5k_ani_mib_intr(struct ath5k_hw *ah)
|
||||
|
||||
if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH ||
|
||||
as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH)
|
||||
tasklet_schedule(&ah->ah_sc->ani_tasklet);
|
||||
tasklet_schedule(&ah->ani_tasklet);
|
||||
}
|
||||
|
||||
|
||||
@@ -561,16 +561,16 @@ void
|
||||
ath5k_ani_phy_error_report(struct ath5k_hw *ah,
|
||||
enum ath5k_phy_error_code phyerr)
|
||||
{
|
||||
struct ath5k_ani_state *as = &ah->ah_sc->ani_state;
|
||||
struct ath5k_ani_state *as = &ah->ani_state;
|
||||
|
||||
if (phyerr == AR5K_RX_PHY_ERROR_OFDM_TIMING) {
|
||||
as->ofdm_errors++;
|
||||
if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH)
|
||||
tasklet_schedule(&ah->ah_sc->ani_tasklet);
|
||||
tasklet_schedule(&ah->ani_tasklet);
|
||||
} else if (phyerr == AR5K_RX_PHY_ERROR_CCK_TIMING) {
|
||||
as->cck_errors++;
|
||||
if (as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH)
|
||||
tasklet_schedule(&ah->ah_sc->ani_tasklet);
|
||||
tasklet_schedule(&ah->ani_tasklet);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -631,24 +631,24 @@ ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
|
||||
return;
|
||||
|
||||
if (mode < ATH5K_ANI_MODE_OFF || mode > ATH5K_ANI_MODE_AUTO) {
|
||||
ATH5K_ERR(ah->ah_sc, "ANI mode %d out of range", mode);
|
||||
ATH5K_ERR(ah, "ANI mode %d out of range", mode);
|
||||
return;
|
||||
}
|
||||
|
||||
/* clear old state information */
|
||||
memset(&ah->ah_sc->ani_state, 0, sizeof(ah->ah_sc->ani_state));
|
||||
memset(&ah->ani_state, 0, sizeof(ah->ani_state));
|
||||
|
||||
/* older hardware has more spur levels than newer */
|
||||
if (ah->ah_mac_srev < AR5K_SREV_AR2414)
|
||||
ah->ah_sc->ani_state.max_spur_level = 7;
|
||||
ah->ani_state.max_spur_level = 7;
|
||||
else
|
||||
ah->ah_sc->ani_state.max_spur_level = 2;
|
||||
ah->ani_state.max_spur_level = 2;
|
||||
|
||||
/* initial values for our ani parameters */
|
||||
if (mode == ATH5K_ANI_MODE_OFF) {
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI off\n");
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "ANI off\n");
|
||||
} else if (mode == ATH5K_ANI_MODE_MANUAL_LOW) {
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
|
||||
"ANI manual low -> high sensitivity\n");
|
||||
ath5k_ani_set_noise_immunity_level(ah, 0);
|
||||
ath5k_ani_set_spur_immunity_level(ah, 0);
|
||||
@@ -656,17 +656,17 @@ ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
|
||||
ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
|
||||
ath5k_ani_set_cck_weak_signal_detection(ah, true);
|
||||
} else if (mode == ATH5K_ANI_MODE_MANUAL_HIGH) {
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
|
||||
"ANI manual high -> low sensitivity\n");
|
||||
ath5k_ani_set_noise_immunity_level(ah,
|
||||
ATH5K_ANI_MAX_NOISE_IMM_LVL);
|
||||
ath5k_ani_set_spur_immunity_level(ah,
|
||||
ah->ah_sc->ani_state.max_spur_level);
|
||||
ah->ani_state.max_spur_level);
|
||||
ath5k_ani_set_firstep_level(ah, ATH5K_ANI_MAX_FIRSTEP_LVL);
|
||||
ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
|
||||
ath5k_ani_set_cck_weak_signal_detection(ah, false);
|
||||
} else if (mode == ATH5K_ANI_MODE_AUTO) {
|
||||
ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI auto\n");
|
||||
ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "ANI auto\n");
|
||||
ath5k_ani_set_noise_immunity_level(ah, 0);
|
||||
ath5k_ani_set_spur_immunity_level(ah, 0);
|
||||
ath5k_ani_set_firstep_level(ah, 0);
|
||||
@@ -692,7 +692,7 @@ ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
|
||||
~AR5K_RX_FILTER_PHYERR);
|
||||
}
|
||||
|
||||
ah->ah_sc->ani_state.ani_mode = mode;
|
||||
ah->ani_state.ani_mode = mode;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -24,8 +24,10 @@
|
||||
#define CHAN_DEBUG 0
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/average.h>
|
||||
#include <linux/leds.h>
|
||||
#include <net/mac80211.h>
|
||||
|
||||
/* RX/TX descriptor hw structs
|
||||
@@ -36,7 +38,9 @@
|
||||
* TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
|
||||
* and clean up common bits, then introduce set/get functions in eeprom.c */
|
||||
#include "eeprom.h"
|
||||
#include "debug.h"
|
||||
#include "../ath.h"
|
||||
#include "ani.h"
|
||||
|
||||
/* PCI IDs */
|
||||
#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
|
||||
@@ -537,6 +541,27 @@ enum ath5k_tx_queue_id {
|
||||
#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
|
||||
#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
|
||||
|
||||
/*
|
||||
* Data transmit queue state. One of these exists for each
|
||||
* hardware transmit queue. Packets sent to us from above
|
||||
* are assigned to queues based on their priority. Not all
|
||||
* devices support a complete set of hardware transmit queues.
|
||||
* For those devices the array sc_ac2q will map multiple
|
||||
* priorities to fewer hardware queues (typically all to one
|
||||
* hardware queue).
|
||||
*/
|
||||
struct ath5k_txq {
|
||||
unsigned int qnum; /* hardware q number */
|
||||
u32 *link; /* link ptr in last TX desc */
|
||||
struct list_head q; /* transmit queue */
|
||||
spinlock_t lock; /* lock on q and link */
|
||||
bool setup;
|
||||
int txq_len; /* number of queued buffers */
|
||||
int txq_max; /* max allowed num of queued buffers */
|
||||
bool txq_poll_mark;
|
||||
unsigned int txq_stuck; /* informational counter */
|
||||
};
|
||||
|
||||
/*
|
||||
* A struct to hold tx queue's parameters
|
||||
*/
|
||||
@@ -947,35 +972,6 @@ enum ath5k_power_mode {
|
||||
#define AR5K_SOFTLED_ON 0
|
||||
#define AR5K_SOFTLED_OFF 1
|
||||
|
||||
/*
|
||||
* Chipset capabilities -see ath5k_hw_get_capability-
|
||||
* get_capability function is not yet fully implemented
|
||||
* in ath5k so most of these don't work yet...
|
||||
* TODO: Implement these & merge with _TUNE_ stuff above
|
||||
*/
|
||||
enum ath5k_capability_type {
|
||||
AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
|
||||
AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
|
||||
AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
|
||||
AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
|
||||
AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
|
||||
AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
|
||||
AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
|
||||
AR5K_CAP_COMPRESSION = 8, /* Supports compression */
|
||||
AR5K_CAP_BURST = 9, /* Supports packet bursting */
|
||||
AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
|
||||
AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
|
||||
AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
|
||||
AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
|
||||
AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
|
||||
AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
|
||||
AR5K_CAP_XR = 16, /* Supports XR mode */
|
||||
AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
|
||||
AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
|
||||
AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
|
||||
AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
|
||||
};
|
||||
|
||||
|
||||
/* XXX: we *may* move cap_range stuff to struct wiphy */
|
||||
struct ath5k_capabilities {
|
||||
@@ -1027,9 +1023,66 @@ struct ath5k_avg_val {
|
||||
int avg_weight;
|
||||
};
|
||||
|
||||
/***************************************\
|
||||
HARDWARE ABSTRACTION LAYER STRUCTURE
|
||||
\***************************************/
|
||||
#define ATH5K_LED_MAX_NAME_LEN 31
|
||||
|
||||
/*
|
||||
* State for LED triggers
|
||||
*/
|
||||
struct ath5k_led {
|
||||
char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
|
||||
struct ath5k_hw *ah; /* driver state */
|
||||
struct led_classdev led_dev; /* led classdev */
|
||||
};
|
||||
|
||||
/* Rfkill */
|
||||
struct ath5k_rfkill {
|
||||
/* GPIO PIN for rfkill */
|
||||
u16 gpio;
|
||||
/* polarity of rfkill GPIO PIN */
|
||||
bool polarity;
|
||||
/* RFKILL toggle tasklet */
|
||||
struct tasklet_struct toggleq;
|
||||
};
|
||||
|
||||
/* statistics */
|
||||
struct ath5k_statistics {
|
||||
/* antenna use */
|
||||
unsigned int antenna_rx[5]; /* frames count per antenna RX */
|
||||
unsigned int antenna_tx[5]; /* frames count per antenna TX */
|
||||
|
||||
/* frame errors */
|
||||
unsigned int rx_all_count; /* all RX frames, including errors */
|
||||
unsigned int tx_all_count; /* all TX frames, including errors */
|
||||
unsigned int rx_bytes_count; /* all RX bytes, including errored pkts
|
||||
* and the MAC headers for each packet
|
||||
*/
|
||||
unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
|
||||
* and the MAC headers and padding for
|
||||
* each packet.
|
||||
*/
|
||||
unsigned int rxerr_crc;
|
||||
unsigned int rxerr_phy;
|
||||
unsigned int rxerr_phy_code[32];
|
||||
unsigned int rxerr_fifo;
|
||||
unsigned int rxerr_decrypt;
|
||||
unsigned int rxerr_mic;
|
||||
unsigned int rxerr_proc;
|
||||
unsigned int rxerr_jumbo;
|
||||
unsigned int txerr_retry;
|
||||
unsigned int txerr_fifo;
|
||||
unsigned int txerr_filt;
|
||||
|
||||
/* MIB counters */
|
||||
unsigned int ack_fail;
|
||||
unsigned int rts_fail;
|
||||
unsigned int rts_ok;
|
||||
unsigned int fcs_error;
|
||||
unsigned int beacons;
|
||||
|
||||
unsigned int mib_intr;
|
||||
unsigned int rxorn_intr;
|
||||
unsigned int rxeol_intr;
|
||||
};
|
||||
|
||||
/*
|
||||
* Misc defines
|
||||
@@ -1038,12 +1091,114 @@ struct ath5k_avg_val {
|
||||
#define AR5K_MAX_GPIO 10
|
||||
#define AR5K_MAX_RF_BANKS 8
|
||||
|
||||
/* TODO: Clean up and merge with ath5k_softc */
|
||||
#if CHAN_DEBUG
|
||||
#define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200)
|
||||
#else
|
||||
#define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)
|
||||
#endif
|
||||
|
||||
#define ATH_RXBUF 40 /* number of RX buffers */
|
||||
#define ATH_TXBUF 200 /* number of TX buffers */
|
||||
#define ATH_BCBUF 4 /* number of beacon buffers */
|
||||
#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
|
||||
#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
|
||||
|
||||
/* Driver state associated with an instance of a device */
|
||||
struct ath5k_hw {
|
||||
struct ath_common common;
|
||||
|
||||
struct ath5k_softc *ah_sc;
|
||||
void __iomem *ah_iobase;
|
||||
struct pci_dev *pdev;
|
||||
struct device *dev; /* for dma mapping */
|
||||
int irq;
|
||||
u16 devid;
|
||||
void __iomem *iobase; /* address of the device */
|
||||
struct mutex lock; /* dev-level lock */
|
||||
struct ieee80211_hw *hw; /* IEEE 802.11 common */
|
||||
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
|
||||
struct ieee80211_channel channels[ATH_CHAN_MAX];
|
||||
struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
|
||||
s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
|
||||
enum nl80211_iftype opmode;
|
||||
|
||||
#ifdef CONFIG_ATH5K_DEBUG
|
||||
struct ath5k_dbg_info debug; /* debug info */
|
||||
#endif /* CONFIG_ATH5K_DEBUG */
|
||||
|
||||
struct ath5k_buf *bufptr; /* allocated buffer ptr */
|
||||
struct ath5k_desc *desc; /* TX/RX descriptors */
|
||||
dma_addr_t desc_daddr; /* DMA (physical) address */
|
||||
size_t desc_len; /* size of TX/RX descriptors */
|
||||
|
||||
DECLARE_BITMAP(status, 6);
|
||||
#define ATH_STAT_INVALID 0 /* disable hardware accesses */
|
||||
#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
|
||||
#define ATH_STAT_PROMISC 2
|
||||
#define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
|
||||
#define ATH_STAT_STARTED 4 /* opened & irqs enabled */
|
||||
#define ATH_STAT_2G_DISABLED 5 /* multiband radio without 2G */
|
||||
|
||||
unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
|
||||
struct ieee80211_channel *curchan; /* current h/w channel */
|
||||
|
||||
u16 nvifs;
|
||||
|
||||
enum ath5k_int imask; /* interrupt mask copy */
|
||||
|
||||
spinlock_t irqlock;
|
||||
bool rx_pending; /* rx tasklet pending */
|
||||
bool tx_pending; /* tx tasklet pending */
|
||||
|
||||
u8 lladdr[ETH_ALEN];
|
||||
u8 bssidmask[ETH_ALEN];
|
||||
|
||||
unsigned int led_pin, /* GPIO pin for driving LED */
|
||||
led_on; /* pin setting for LED on */
|
||||
|
||||
struct work_struct reset_work; /* deferred chip reset */
|
||||
|
||||
unsigned int rxbufsize; /* rx size based on mtu */
|
||||
struct list_head rxbuf; /* receive buffer */
|
||||
spinlock_t rxbuflock;
|
||||
u32 *rxlink; /* link ptr in last RX desc */
|
||||
struct tasklet_struct rxtq; /* rx intr tasklet */
|
||||
struct ath5k_led rx_led; /* rx led */
|
||||
|
||||
struct list_head txbuf; /* transmit buffer */
|
||||
spinlock_t txbuflock;
|
||||
unsigned int txbuf_len; /* buf count in txbuf list */
|
||||
struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
|
||||
struct tasklet_struct txtq; /* tx intr tasklet */
|
||||
struct ath5k_led tx_led; /* tx led */
|
||||
|
||||
struct ath5k_rfkill rf_kill;
|
||||
|
||||
struct tasklet_struct calib; /* calibration tasklet */
|
||||
|
||||
spinlock_t block; /* protects beacon */
|
||||
struct tasklet_struct beacontq; /* beacon intr tasklet */
|
||||
struct list_head bcbuf; /* beacon buffer */
|
||||
struct ieee80211_vif *bslot[ATH_BCBUF];
|
||||
u16 num_ap_vifs;
|
||||
u16 num_adhoc_vifs;
|
||||
unsigned int bhalq, /* SW q for outgoing beacons */
|
||||
bmisscount, /* missed beacon transmits */
|
||||
bintval, /* beacon interval in TU */
|
||||
bsent;
|
||||
unsigned int nexttbtt; /* next beacon time in TU */
|
||||
struct ath5k_txq *cabq; /* content after beacon */
|
||||
|
||||
int power_level; /* Requested tx power in dBm */
|
||||
bool assoc; /* associate state */
|
||||
bool enable_beacon; /* true if beacons are on */
|
||||
|
||||
struct ath5k_statistics stats;
|
||||
|
||||
struct ath5k_ani_state ani_state;
|
||||
struct tasklet_struct ani_tasklet; /* ANI calibration */
|
||||
|
||||
struct delayed_work tx_complete_work;
|
||||
|
||||
struct survey_info survey; /* collected survey info */
|
||||
|
||||
enum ath5k_int ah_imr;
|
||||
|
||||
@@ -1172,43 +1327,43 @@ struct ath_bus_ops {
|
||||
extern const struct ieee80211_ops ath5k_hw_ops;
|
||||
|
||||
/* Initialization and detach functions */
|
||||
int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops);
|
||||
void ath5k_deinit_softc(struct ath5k_softc *sc);
|
||||
int ath5k_hw_init(struct ath5k_softc *sc);
|
||||
int ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops);
|
||||
void ath5k_deinit_softc(struct ath5k_hw *ah);
|
||||
int ath5k_hw_init(struct ath5k_hw *ah);
|
||||
void ath5k_hw_deinit(struct ath5k_hw *ah);
|
||||
|
||||
int ath5k_sysfs_register(struct ath5k_softc *sc);
|
||||
void ath5k_sysfs_unregister(struct ath5k_softc *sc);
|
||||
int ath5k_sysfs_register(struct ath5k_hw *ah);
|
||||
void ath5k_sysfs_unregister(struct ath5k_hw *ah);
|
||||
|
||||
/* base.c */
|
||||
struct ath5k_buf;
|
||||
struct ath5k_txq;
|
||||
|
||||
void ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable);
|
||||
bool ath5k_any_vif_assoc(struct ath5k_softc *sc);
|
||||
bool ath5k_any_vif_assoc(struct ath5k_hw *ah);
|
||||
void ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
|
||||
struct ath5k_txq *txq);
|
||||
int ath5k_init_hw(struct ath5k_softc *sc);
|
||||
int ath5k_stop_hw(struct ath5k_softc *sc);
|
||||
void ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif);
|
||||
void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
|
||||
int ath5k_start(struct ieee80211_hw *hw);
|
||||
void ath5k_stop(struct ieee80211_hw *hw);
|
||||
void ath5k_mode_setup(struct ath5k_hw *ah, struct ieee80211_vif *vif);
|
||||
void ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
|
||||
struct ieee80211_vif *vif);
|
||||
int ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan);
|
||||
void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
|
||||
int ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan);
|
||||
void ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf);
|
||||
int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
|
||||
void ath5k_beacon_config(struct ath5k_softc *sc);
|
||||
void ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf);
|
||||
void ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf);
|
||||
void ath5k_beacon_config(struct ath5k_hw *ah);
|
||||
void ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf);
|
||||
void ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf);
|
||||
|
||||
/*Chip id helper functions */
|
||||
const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val);
|
||||
int ath5k_hw_read_srev(struct ath5k_hw *ah);
|
||||
|
||||
/* LED functions */
|
||||
int ath5k_init_leds(struct ath5k_softc *sc);
|
||||
void ath5k_led_enable(struct ath5k_softc *sc);
|
||||
void ath5k_led_off(struct ath5k_softc *sc);
|
||||
void ath5k_unregister_leds(struct ath5k_softc *sc);
|
||||
int ath5k_init_leds(struct ath5k_hw *ah);
|
||||
void ath5k_led_enable(struct ath5k_hw *ah);
|
||||
void ath5k_led_off(struct ath5k_hw *ah);
|
||||
void ath5k_unregister_leds(struct ath5k_hw *ah);
|
||||
|
||||
|
||||
/* Reset Functions */
|
||||
@@ -1322,9 +1477,6 @@ void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
|
||||
|
||||
/* Misc functions TODO: Cleanup */
|
||||
int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
|
||||
int ath5k_hw_get_capability(struct ath5k_hw *ah,
|
||||
enum ath5k_capability_type cap_type, u32 capability,
|
||||
u32 *result);
|
||||
int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
|
||||
int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
|
||||
|
||||
@@ -1384,7 +1536,7 @@ static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
|
||||
(ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
|
||||
return AR5K_AR2315_PCI_BASE + reg;
|
||||
|
||||
return ah->ah_iobase + reg;
|
||||
return ah->iobase + reg;
|
||||
}
|
||||
|
||||
static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
|
||||
@@ -1401,12 +1553,12 @@ static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
|
||||
|
||||
static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
|
||||
{
|
||||
return ioread32(ah->ah_iobase + reg);
|
||||
return ioread32(ah->iobase + reg);
|
||||
}
|
||||
|
||||
static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
|
||||
{
|
||||
iowrite32(val, ah->ah_iobase + reg);
|
||||
iowrite32(val, ah->iobase + reg);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -59,7 +59,7 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
|
||||
cur_val = ath5k_hw_reg_read(ah, cur_reg);
|
||||
|
||||
if (cur_val != var_pattern) {
|
||||
ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
|
||||
ATH5K_ERR(ah, "POST Failed !!!\n");
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
@@ -74,7 +74,7 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
|
||||
cur_val = ath5k_hw_reg_read(ah, cur_reg);
|
||||
|
||||
if (cur_val != var_pattern) {
|
||||
ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
|
||||
ATH5K_ERR(ah, "POST Failed !!!\n");
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
@@ -95,19 +95,18 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
|
||||
/**
|
||||
* ath5k_hw_init - Check if hw is supported and init the needed structs
|
||||
*
|
||||
* @sc: The &struct ath5k_softc we got from the driver's init_softc function
|
||||
* @ah: The &struct ath5k_hw we got from the driver's init_softc function
|
||||
*
|
||||
* Check if the device is supported, perform a POST and initialize the needed
|
||||
* structs. Returns -ENOMEM if we don't have memory for the needed structs,
|
||||
* -ENODEV if the device is not supported or prints an error msg if something
|
||||
* else went wrong.
|
||||
*/
|
||||
int ath5k_hw_init(struct ath5k_softc *sc)
|
||||
int ath5k_hw_init(struct ath5k_hw *ah)
|
||||
{
|
||||
static const u8 zero_mac[ETH_ALEN] = { };
|
||||
struct ath5k_hw *ah = sc->ah;
|
||||
struct ath_common *common = ath5k_hw_common(ah);
|
||||
struct pci_dev *pdev = sc->pdev;
|
||||
struct pci_dev *pdev = ah->pdev;
|
||||
struct ath5k_eeprom_info *ee;
|
||||
int ret;
|
||||
u32 srev;
|
||||
@@ -123,8 +122,8 @@ int ath5k_hw_init(struct ath5k_softc *sc)
|
||||
ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
|
||||
ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
|
||||
ah->ah_noise_floor = -95; /* until first NF calibration is run */
|
||||
sc->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
|
||||
ah->ah_current_channel = &sc->channels[0];
|
||||
ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
|
||||
ah->ah_current_channel = &ah->channels[0];
|
||||
|
||||
/*
|
||||
* Find the mac version
|
||||
@@ -237,7 +236,7 @@ int ath5k_hw_init(struct ath5k_softc *sc)
|
||||
ah->ah_single_chip = true;
|
||||
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
|
||||
} else {
|
||||
ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
|
||||
ATH5K_ERR(ah, "Couldn't identify radio revision.\n");
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
@@ -246,7 +245,7 @@ int ath5k_hw_init(struct ath5k_softc *sc)
|
||||
|
||||
/* Return on unsupported chips (unsupported eeprom etc) */
|
||||
if ((srev >= AR5K_SREV_AR5416) && (srev < AR5K_SREV_AR2425)) {
|
||||
ATH5K_ERR(sc, "Device not yet supported.\n");
|
||||
ATH5K_ERR(ah, "Device not yet supported.\n");
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
@@ -268,7 +267,7 @@ int ath5k_hw_init(struct ath5k_softc *sc)
|
||||
*/
|
||||
ret = ath5k_eeprom_init(ah);
|
||||
if (ret) {
|
||||
ATH5K_ERR(sc, "unable to init EEPROM\n");
|
||||
ATH5K_ERR(ah, "unable to init EEPROM\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
@@ -309,17 +308,17 @@ int ath5k_hw_init(struct ath5k_softc *sc)
|
||||
/* Get misc capabilities */
|
||||
ret = ath5k_hw_set_capabilities(ah);
|
||||
if (ret) {
|
||||
ATH5K_ERR(sc, "unable to get device capabilities\n");
|
||||
ATH5K_ERR(ah, "unable to get device capabilities\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (test_bit(ATH_STAT_2G_DISABLED, sc->status)) {
|
||||
if (test_bit(ATH_STAT_2G_DISABLED, ah->status)) {
|
||||
__clear_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode);
|
||||
__clear_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode);
|
||||
}
|
||||
|
||||
/* Crypto settings */
|
||||
common->keymax = (sc->ah->ah_version == AR5K_AR5210 ?
|
||||
common->keymax = (ah->ah_version == AR5K_AR5210 ?
|
||||
AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
|
||||
|
||||
if (srev >= AR5K_SREV_AR5212_V4 &&
|
||||
@@ -339,7 +338,7 @@ int ath5k_hw_init(struct ath5k_softc *sc)
|
||||
/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
|
||||
memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
|
||||
ath5k_hw_set_bssid(ah);
|
||||
ath5k_hw_set_opmode(ah, sc->opmode);
|
||||
ath5k_hw_set_opmode(ah, ah->opmode);
|
||||
|
||||
ath5k_hw_rfgain_opt_init(ah);
|
||||
|
||||
@@ -360,7 +359,7 @@ err:
|
||||
*/
|
||||
void ath5k_hw_deinit(struct ath5k_hw *ah)
|
||||
{
|
||||
__set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
|
||||
__set_bit(ATH_STAT_INVALID, ah->status);
|
||||
|
||||
if (ah->ah_rf_banks != NULL)
|
||||
kfree(ah->ah_rf_banks);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -45,23 +45,13 @@
|
||||
#include <linux/list.h>
|
||||
#include <linux/wireless.h>
|
||||
#include <linux/if_ether.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/rfkill.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include "ath5k.h"
|
||||
#include "debug.h"
|
||||
#include "ani.h"
|
||||
|
||||
#include "../regd.h"
|
||||
#include "../ath.h"
|
||||
|
||||
#define ATH_RXBUF 40 /* number of RX buffers */
|
||||
#define ATH_TXBUF 200 /* number of TX buffers */
|
||||
#define ATH_BCBUF 4 /* number of beacon buffers */
|
||||
#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
|
||||
#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
|
||||
|
||||
struct ath5k_buf {
|
||||
struct list_head list;
|
||||
struct ath5k_desc *desc; /* virtual addr of desc */
|
||||
@@ -70,94 +60,6 @@ struct ath5k_buf {
|
||||
dma_addr_t skbaddr;/* physical addr of skb data */
|
||||
};
|
||||
|
||||
/*
|
||||
* Data transmit queue state. One of these exists for each
|
||||
* hardware transmit queue. Packets sent to us from above
|
||||
* are assigned to queues based on their priority. Not all
|
||||
* devices support a complete set of hardware transmit queues.
|
||||
* For those devices the array sc_ac2q will map multiple
|
||||
* priorities to fewer hardware queues (typically all to one
|
||||
* hardware queue).
|
||||
*/
|
||||
struct ath5k_txq {
|
||||
unsigned int qnum; /* hardware q number */
|
||||
u32 *link; /* link ptr in last TX desc */
|
||||
struct list_head q; /* transmit queue */
|
||||
spinlock_t lock; /* lock on q and link */
|
||||
bool setup;
|
||||
int txq_len; /* number of queued buffers */
|
||||
int txq_max; /* max allowed num of queued buffers */
|
||||
bool txq_poll_mark;
|
||||
unsigned int txq_stuck; /* informational counter */
|
||||
};
|
||||
|
||||
#define ATH5K_LED_MAX_NAME_LEN 31
|
||||
|
||||
/*
|
||||
* State for LED triggers
|
||||
*/
|
||||
struct ath5k_led {
|
||||
char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
|
||||
struct ath5k_softc *sc; /* driver state */
|
||||
struct led_classdev led_dev; /* led classdev */
|
||||
};
|
||||
|
||||
/* Rfkill */
|
||||
struct ath5k_rfkill {
|
||||
/* GPIO PIN for rfkill */
|
||||
u16 gpio;
|
||||
/* polarity of rfkill GPIO PIN */
|
||||
bool polarity;
|
||||
/* RFKILL toggle tasklet */
|
||||
struct tasklet_struct toggleq;
|
||||
};
|
||||
|
||||
/* statistics */
|
||||
struct ath5k_statistics {
|
||||
/* antenna use */
|
||||
unsigned int antenna_rx[5]; /* frames count per antenna RX */
|
||||
unsigned int antenna_tx[5]; /* frames count per antenna TX */
|
||||
|
||||
/* frame errors */
|
||||
unsigned int rx_all_count; /* all RX frames, including errors */
|
||||
unsigned int tx_all_count; /* all TX frames, including errors */
|
||||
unsigned int rx_bytes_count; /* all RX bytes, including errored pkts
|
||||
* and the MAC headers for each packet
|
||||
*/
|
||||
unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
|
||||
* and the MAC headers and padding for
|
||||
* each packet.
|
||||
*/
|
||||
unsigned int rxerr_crc;
|
||||
unsigned int rxerr_phy;
|
||||
unsigned int rxerr_phy_code[32];
|
||||
unsigned int rxerr_fifo;
|
||||
unsigned int rxerr_decrypt;
|
||||
unsigned int rxerr_mic;
|
||||
unsigned int rxerr_proc;
|
||||
unsigned int rxerr_jumbo;
|
||||
unsigned int txerr_retry;
|
||||
unsigned int txerr_fifo;
|
||||
unsigned int txerr_filt;
|
||||
|
||||
/* MIB counters */
|
||||
unsigned int ack_fail;
|
||||
unsigned int rts_fail;
|
||||
unsigned int rts_ok;
|
||||
unsigned int fcs_error;
|
||||
unsigned int beacons;
|
||||
|
||||
unsigned int mib_intr;
|
||||
unsigned int rxorn_intr;
|
||||
unsigned int rxeol_intr;
|
||||
};
|
||||
|
||||
#if CHAN_DEBUG
|
||||
#define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200)
|
||||
#else
|
||||
#define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)
|
||||
#endif
|
||||
|
||||
struct ath5k_vif {
|
||||
bool assoc; /* are we associated or not */
|
||||
enum nl80211_iftype opmode;
|
||||
@@ -166,104 +68,6 @@ struct ath5k_vif {
|
||||
u8 lladdr[ETH_ALEN];
|
||||
};
|
||||
|
||||
/* Software Carrier, keeps track of the driver state
|
||||
* associated with an instance of a device */
|
||||
struct ath5k_softc {
|
||||
struct pci_dev *pdev;
|
||||
struct device *dev; /* for dma mapping */
|
||||
int irq;
|
||||
u16 devid;
|
||||
void __iomem *iobase; /* address of the device */
|
||||
struct mutex lock; /* dev-level lock */
|
||||
struct ieee80211_hw *hw; /* IEEE 802.11 common */
|
||||
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
|
||||
struct ieee80211_channel channels[ATH_CHAN_MAX];
|
||||
struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
|
||||
s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
|
||||
enum nl80211_iftype opmode;
|
||||
struct ath5k_hw *ah; /* Atheros HW */
|
||||
|
||||
#ifdef CONFIG_ATH5K_DEBUG
|
||||
struct ath5k_dbg_info debug; /* debug info */
|
||||
#endif /* CONFIG_ATH5K_DEBUG */
|
||||
|
||||
struct ath5k_buf *bufptr; /* allocated buffer ptr */
|
||||
struct ath5k_desc *desc; /* TX/RX descriptors */
|
||||
dma_addr_t desc_daddr; /* DMA (physical) address */
|
||||
size_t desc_len; /* size of TX/RX descriptors */
|
||||
|
||||
DECLARE_BITMAP(status, 6);
|
||||
#define ATH_STAT_INVALID 0 /* disable hardware accesses */
|
||||
#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
|
||||
#define ATH_STAT_PROMISC 2
|
||||
#define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
|
||||
#define ATH_STAT_STARTED 4 /* opened & irqs enabled */
|
||||
#define ATH_STAT_2G_DISABLED 5 /* multiband radio without 2G */
|
||||
|
||||
unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
|
||||
struct ieee80211_channel *curchan; /* current h/w channel */
|
||||
|
||||
u16 nvifs;
|
||||
|
||||
enum ath5k_int imask; /* interrupt mask copy */
|
||||
|
||||
spinlock_t irqlock;
|
||||
bool rx_pending; /* rx tasklet pending */
|
||||
bool tx_pending; /* tx tasklet pending */
|
||||
|
||||
u8 lladdr[ETH_ALEN];
|
||||
u8 bssidmask[ETH_ALEN];
|
||||
|
||||
unsigned int led_pin, /* GPIO pin for driving LED */
|
||||
led_on; /* pin setting for LED on */
|
||||
|
||||
struct work_struct reset_work; /* deferred chip reset */
|
||||
|
||||
unsigned int rxbufsize; /* rx size based on mtu */
|
||||
struct list_head rxbuf; /* receive buffer */
|
||||
spinlock_t rxbuflock;
|
||||
u32 *rxlink; /* link ptr in last RX desc */
|
||||
struct tasklet_struct rxtq; /* rx intr tasklet */
|
||||
struct ath5k_led rx_led; /* rx led */
|
||||
|
||||
struct list_head txbuf; /* transmit buffer */
|
||||
spinlock_t txbuflock;
|
||||
unsigned int txbuf_len; /* buf count in txbuf list */
|
||||
struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
|
||||
struct tasklet_struct txtq; /* tx intr tasklet */
|
||||
struct ath5k_led tx_led; /* tx led */
|
||||
|
||||
struct ath5k_rfkill rf_kill;
|
||||
|
||||
struct tasklet_struct calib; /* calibration tasklet */
|
||||
|
||||
spinlock_t block; /* protects beacon */
|
||||
struct tasklet_struct beacontq; /* beacon intr tasklet */
|
||||
struct list_head bcbuf; /* beacon buffer */
|
||||
struct ieee80211_vif *bslot[ATH_BCBUF];
|
||||
u16 num_ap_vifs;
|
||||
u16 num_adhoc_vifs;
|
||||
unsigned int bhalq, /* SW q for outgoing beacons */
|
||||
bmisscount, /* missed beacon transmits */
|
||||
bintval, /* beacon interval in TU */
|
||||
bsent;
|
||||
unsigned int nexttbtt; /* next beacon time in TU */
|
||||
struct ath5k_txq *cabq; /* content after beacon */
|
||||
|
||||
int power_level; /* Requested tx power in dBm */
|
||||
bool assoc; /* associate state */
|
||||
bool enable_beacon; /* true if beacons are on */
|
||||
|
||||
struct ath5k_statistics stats;
|
||||
|
||||
struct ath5k_ani_state ani_state;
|
||||
struct tasklet_struct ani_tasklet; /* ANI calibration */
|
||||
|
||||
struct delayed_work tx_complete_work;
|
||||
|
||||
struct survey_info survey; /* collected survey info */
|
||||
};
|
||||
|
||||
struct ath5k_vif_iter_data {
|
||||
const u8 *hw_macaddr;
|
||||
u8 mask[ETH_ALEN];
|
||||
@@ -277,9 +81,10 @@ struct ath5k_vif_iter_data {
|
||||
void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif);
|
||||
|
||||
|
||||
#define ath5k_hw_hasbssidmask(_ah) \
|
||||
(ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
|
||||
#define ath5k_hw_hasveol(_ah) \
|
||||
(ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)
|
||||
/* Check whether BSSID mask is supported */
|
||||
#define ath5k_hw_hasbssidmask(_ah) (ah->ah_version == AR5K_AR5212)
|
||||
|
||||
/* Check whether virtual EOL is supported */
|
||||
#define ath5k_hw_hasveol(_ah) (ah->ah_version != AR5K_AR5210)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -112,51 +112,6 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Main function used by the driver part to check caps */
|
||||
int ath5k_hw_get_capability(struct ath5k_hw *ah,
|
||||
enum ath5k_capability_type cap_type,
|
||||
u32 capability, u32 *result)
|
||||
{
|
||||
switch (cap_type) {
|
||||
case AR5K_CAP_NUM_TXQUEUES:
|
||||
if (result) {
|
||||
if (ah->ah_version == AR5K_AR5210)
|
||||
*result = AR5K_NUM_TX_QUEUES_NOQCU;
|
||||
else
|
||||
*result = AR5K_NUM_TX_QUEUES;
|
||||
goto yes;
|
||||
}
|
||||
case AR5K_CAP_VEOL:
|
||||
goto yes;
|
||||
case AR5K_CAP_COMPRESSION:
|
||||
if (ah->ah_version == AR5K_AR5212)
|
||||
goto yes;
|
||||
else
|
||||
goto no;
|
||||
case AR5K_CAP_BURST:
|
||||
goto yes;
|
||||
case AR5K_CAP_TPC:
|
||||
goto yes;
|
||||
case AR5K_CAP_BSSIDMASK:
|
||||
if (ah->ah_version == AR5K_AR5212)
|
||||
goto yes;
|
||||
else
|
||||
goto no;
|
||||
case AR5K_CAP_XR:
|
||||
if (ah->ah_version == AR5K_AR5212)
|
||||
goto yes;
|
||||
else
|
||||
goto no;
|
||||
default:
|
||||
goto no;
|
||||
}
|
||||
|
||||
no:
|
||||
return -EINVAL;
|
||||
yes:
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* TODO: Following functions should be part of a new function
|
||||
* set_capability
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -61,7 +61,6 @@
|
||||
#ifndef _ATH5K_DEBUG_H
|
||||
#define _ATH5K_DEBUG_H
|
||||
|
||||
struct ath5k_softc;
|
||||
struct ath5k_hw;
|
||||
struct sk_buff;
|
||||
struct ath5k_buf;
|
||||
@@ -127,39 +126,39 @@ enum ath5k_debug_level {
|
||||
} while (0)
|
||||
|
||||
void
|
||||
ath5k_debug_init_device(struct ath5k_softc *sc);
|
||||
ath5k_debug_init_device(struct ath5k_hw *ah);
|
||||
|
||||
void
|
||||
ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah);
|
||||
ath5k_debug_printrxbuffs(struct ath5k_hw *ah);
|
||||
|
||||
void
|
||||
ath5k_debug_dump_bands(struct ath5k_softc *sc);
|
||||
ath5k_debug_dump_bands(struct ath5k_hw *ah);
|
||||
|
||||
void
|
||||
ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf);
|
||||
ath5k_debug_printtxbuf(struct ath5k_hw *ah, struct ath5k_buf *bf);
|
||||
|
||||
#else /* no debugging */
|
||||
|
||||
#include <linux/compiler.h>
|
||||
|
||||
static inline void __attribute__ ((format (printf, 3, 4)))
|
||||
ATH5K_DBG(struct ath5k_softc *sc, unsigned int m, const char *fmt, ...) {}
|
||||
ATH5K_DBG(struct ath5k_hw *ah, unsigned int m, const char *fmt, ...) {}
|
||||
|
||||
static inline void __attribute__ ((format (printf, 3, 4)))
|
||||
ATH5K_DBG_UNLIMIT(struct ath5k_softc *sc, unsigned int m, const char *fmt, ...)
|
||||
ATH5K_DBG_UNLIMIT(struct ath5k_hw *ah, unsigned int m, const char *fmt, ...)
|
||||
{}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_init_device(struct ath5k_softc *sc) {}
|
||||
ath5k_debug_init_device(struct ath5k_hw *ah) {}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah) {}
|
||||
ath5k_debug_printrxbuffs(struct ath5k_hw *ah) {}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_dump_bands(struct ath5k_softc *sc) {}
|
||||
ath5k_debug_dump_bands(struct ath5k_hw *ah) {}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf) {}
|
||||
ath5k_debug_printtxbuf(struct ath5k_hw *ah, struct ath5k_buf *bf) {}
|
||||
|
||||
#endif /* ifdef CONFIG_ATH5K_DEBUG */
|
||||
|
||||
|
||||
@@ -55,12 +55,12 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
|
||||
* noise on the channel, so it is important to avoid this.
|
||||
*/
|
||||
if (unlikely(tx_tries0 == 0)) {
|
||||
ATH5K_ERR(ah->ah_sc, "zero retries\n");
|
||||
ATH5K_ERR(ah, "zero retries\n");
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (unlikely(tx_rate0 == 0)) {
|
||||
ATH5K_ERR(ah->ah_sc, "zero rate\n");
|
||||
ATH5K_ERR(ah, "zero rate\n");
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
@@ -203,12 +203,12 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
|
||||
* noise on the channel, so it is important to avoid this.
|
||||
*/
|
||||
if (unlikely(tx_tries0 == 0)) {
|
||||
ATH5K_ERR(ah->ah_sc, "zero retries\n");
|
||||
ATH5K_ERR(ah, "zero retries\n");
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (unlikely(tx_rate0 == 0)) {
|
||||
ATH5K_ERR(ah->ah_sc, "zero rate\n");
|
||||
ATH5K_ERR(ah, "zero rate\n");
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
@@ -316,7 +316,7 @@ ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
|
||||
if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
|
||||
(tx_rate2 == 0 && tx_tries2 != 0) ||
|
||||
(tx_rate3 == 0 && tx_tries3 != 0))) {
|
||||
ATH5K_ERR(ah->ah_sc, "zero rate\n");
|
||||
ATH5K_ERR(ah, "zero rate\n");
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@@ -73,7 +73,7 @@ static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
|
||||
udelay(100);
|
||||
|
||||
if (!i)
|
||||
ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
|
||||
ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
|
||||
"failed to stop RX DMA !\n");
|
||||
|
||||
return i ? 0 : -EBUSY;
|
||||
@@ -100,7 +100,7 @@ u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
|
||||
int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
|
||||
{
|
||||
if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
|
||||
ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
|
||||
ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
|
||||
"tried to set RXDP while rx was active !\n");
|
||||
return -EIO;
|
||||
}
|
||||
@@ -243,7 +243,7 @@ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
|
||||
udelay(100);
|
||||
|
||||
if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
|
||||
ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
|
||||
ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
|
||||
"queue %i didn't stop !\n", queue);
|
||||
|
||||
/* Check for pending frames */
|
||||
@@ -295,7 +295,7 @@ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
|
||||
AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
|
||||
|
||||
if (pending)
|
||||
ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
|
||||
ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
|
||||
"quiet mechanism didn't work q:%i !\n",
|
||||
queue);
|
||||
}
|
||||
@@ -309,7 +309,7 @@ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
|
||||
/* Clear register */
|
||||
ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
|
||||
if (pending) {
|
||||
ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
|
||||
ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
|
||||
"tx dma didn't stop (q:%i, frm:%i) !\n",
|
||||
queue, pending);
|
||||
return -EBUSY;
|
||||
@@ -333,7 +333,7 @@ int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
int ret;
|
||||
ret = ath5k_hw_stop_tx_dma(ah, queue);
|
||||
if (ret) {
|
||||
ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
|
||||
ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
|
||||
"beacon queue didn't stop !\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
@@ -105,7 +105,7 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
|
||||
* big still, waiting on a better value.
|
||||
*/
|
||||
if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
|
||||
ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: "
|
||||
ATH5K_ERR(ah, "Invalid max custom EEPROM size: "
|
||||
"%d (0x%04x) max expected: %d (0x%04x)\n",
|
||||
eep_max, eep_max,
|
||||
3 * AR5K_EEPROM_INFO_MAX,
|
||||
@@ -119,7 +119,7 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
|
||||
cksum ^= val;
|
||||
}
|
||||
if (cksum != AR5K_EEPROM_INFO_CKSUM) {
|
||||
ATH5K_ERR(ah->ah_sc, "Invalid EEPROM "
|
||||
ATH5K_ERR(ah, "Invalid EEPROM "
|
||||
"checksum: 0x%04x eep_max: 0x%04x (%s)\n",
|
||||
cksum, eep_max,
|
||||
eep_max == AR5K_EEPROM_INFO_MAX ?
|
||||
|
||||
@@ -1542,7 +1542,7 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
|
||||
|
||||
/* AR5K_MODE_11B */
|
||||
if (mode > 2) {
|
||||
ATH5K_ERR(ah->ah_sc,
|
||||
ATH5K_ERR(ah,
|
||||
"unsupported channel mode: %d\n", mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@@ -86,26 +86,26 @@ static DEFINE_PCI_DEVICE_TABLE(ath5k_led_devices) = {
|
||||
{ }
|
||||
};
|
||||
|
||||
void ath5k_led_enable(struct ath5k_softc *sc)
|
||||
void ath5k_led_enable(struct ath5k_hw *ah)
|
||||
{
|
||||
if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
|
||||
ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
|
||||
ath5k_led_off(sc);
|
||||
if (test_bit(ATH_STAT_LEDSOFT, ah->status)) {
|
||||
ath5k_hw_set_gpio_output(ah, ah->led_pin);
|
||||
ath5k_led_off(ah);
|
||||
}
|
||||
}
|
||||
|
||||
static void ath5k_led_on(struct ath5k_softc *sc)
|
||||
static void ath5k_led_on(struct ath5k_hw *ah)
|
||||
{
|
||||
if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
|
||||
if (!test_bit(ATH_STAT_LEDSOFT, ah->status))
|
||||
return;
|
||||
ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
|
||||
ath5k_hw_set_gpio(ah, ah->led_pin, ah->led_on);
|
||||
}
|
||||
|
||||
void ath5k_led_off(struct ath5k_softc *sc)
|
||||
void ath5k_led_off(struct ath5k_hw *ah)
|
||||
{
|
||||
if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
|
||||
if (!test_bit(ATH_STAT_LEDSOFT, ah->status))
|
||||
return;
|
||||
ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
|
||||
ath5k_hw_set_gpio(ah, ah->led_pin, !ah->led_on);
|
||||
}
|
||||
|
||||
static void
|
||||
@@ -116,27 +116,27 @@ ath5k_led_brightness_set(struct led_classdev *led_dev,
|
||||
led_dev);
|
||||
|
||||
if (brightness == LED_OFF)
|
||||
ath5k_led_off(led->sc);
|
||||
ath5k_led_off(led->ah);
|
||||
else
|
||||
ath5k_led_on(led->sc);
|
||||
ath5k_led_on(led->ah);
|
||||
}
|
||||
|
||||
static int
|
||||
ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
|
||||
ath5k_register_led(struct ath5k_hw *ah, struct ath5k_led *led,
|
||||
const char *name, char *trigger)
|
||||
{
|
||||
int err;
|
||||
|
||||
led->sc = sc;
|
||||
led->ah = ah;
|
||||
strncpy(led->name, name, sizeof(led->name));
|
||||
led->led_dev.name = led->name;
|
||||
led->led_dev.default_trigger = trigger;
|
||||
led->led_dev.brightness_set = ath5k_led_brightness_set;
|
||||
|
||||
err = led_classdev_register(sc->dev, &led->led_dev);
|
||||
err = led_classdev_register(ah->dev, &led->led_dev);
|
||||
if (err) {
|
||||
ATH5K_WARN(sc, "could not register LED %s\n", name);
|
||||
led->sc = NULL;
|
||||
ATH5K_WARN(ah, "could not register LED %s\n", name);
|
||||
led->ah = NULL;
|
||||
}
|
||||
return err;
|
||||
}
|
||||
@@ -144,30 +144,30 @@ ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
|
||||
static void
|
||||
ath5k_unregister_led(struct ath5k_led *led)
|
||||
{
|
||||
if (!led->sc)
|
||||
if (!led->ah)
|
||||
return;
|
||||
led_classdev_unregister(&led->led_dev);
|
||||
ath5k_led_off(led->sc);
|
||||
led->sc = NULL;
|
||||
ath5k_led_off(led->ah);
|
||||
led->ah = NULL;
|
||||
}
|
||||
|
||||
void ath5k_unregister_leds(struct ath5k_softc *sc)
|
||||
void ath5k_unregister_leds(struct ath5k_hw *ah)
|
||||
{
|
||||
ath5k_unregister_led(&sc->rx_led);
|
||||
ath5k_unregister_led(&sc->tx_led);
|
||||
ath5k_unregister_led(&ah->rx_led);
|
||||
ath5k_unregister_led(&ah->tx_led);
|
||||
}
|
||||
|
||||
int __devinit ath5k_init_leds(struct ath5k_softc *sc)
|
||||
int __devinit ath5k_init_leds(struct ath5k_hw *ah)
|
||||
{
|
||||
int ret = 0;
|
||||
struct ieee80211_hw *hw = sc->hw;
|
||||
struct ieee80211_hw *hw = ah->hw;
|
||||
#ifndef CONFIG_ATHEROS_AR231X
|
||||
struct pci_dev *pdev = sc->pdev;
|
||||
struct pci_dev *pdev = ah->pdev;
|
||||
#endif
|
||||
char name[ATH5K_LED_MAX_NAME_LEN + 1];
|
||||
const struct pci_device_id *match;
|
||||
|
||||
if (!sc->pdev)
|
||||
if (!ah->pdev)
|
||||
return 0;
|
||||
|
||||
#ifdef CONFIG_ATHEROS_AR231X
|
||||
@@ -176,24 +176,24 @@ int __devinit ath5k_init_leds(struct ath5k_softc *sc)
|
||||
match = pci_match_id(&ath5k_led_devices[0], pdev);
|
||||
#endif
|
||||
if (match) {
|
||||
__set_bit(ATH_STAT_LEDSOFT, sc->status);
|
||||
sc->led_pin = ATH_PIN(match->driver_data);
|
||||
sc->led_on = ATH_POLARITY(match->driver_data);
|
||||
__set_bit(ATH_STAT_LEDSOFT, ah->status);
|
||||
ah->led_pin = ATH_PIN(match->driver_data);
|
||||
ah->led_on = ATH_POLARITY(match->driver_data);
|
||||
}
|
||||
|
||||
if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
|
||||
if (!test_bit(ATH_STAT_LEDSOFT, ah->status))
|
||||
goto out;
|
||||
|
||||
ath5k_led_enable(sc);
|
||||
ath5k_led_enable(ah);
|
||||
|
||||
snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
|
||||
ret = ath5k_register_led(sc, &sc->rx_led, name,
|
||||
ret = ath5k_register_led(ah, &ah->rx_led, name,
|
||||
ieee80211_get_rx_led_name(hw));
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
|
||||
ret = ath5k_register_led(sc, &sc->tx_led, name,
|
||||
ret = ath5k_register_led(ah, &ah->tx_led, name,
|
||||
ieee80211_get_tx_led_name(hw));
|
||||
out:
|
||||
return ret;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user