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drm/radeon/kms: add support for hw i2c on r1xx-r5xx
wire hw i2c support into radeon i2c algo. fixes merged: - handle bus probing correctly - use meaningful error numbers - abort if transaction fails - The line mapping is different depending on the asic. - protect hw i2c engine with a mutex - rs300 doesn't have a pin select bit - r200 has a different pin select setup Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
committed by
Dave Airlie
Dave Airlie
parent
5a6f98f5bf
commit
40bacf1631
@@ -717,54 +717,62 @@
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#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988
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#define AVIVO_DC_GPIO_HPD_A 0x7e94
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#define AVIVO_GPIO_0 0x7e30
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#define AVIVO_GPIO_1 0x7e40
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#define AVIVO_GPIO_2 0x7e50
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#define AVIVO_GPIO_3 0x7e60
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#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
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#define AVIVO_I2C_STATUS 0x7d30
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# define AVIVO_I2C_STATUS_DONE (1 << 0)
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# define AVIVO_I2C_STATUS_NACK (1 << 1)
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# define AVIVO_I2C_STATUS_HALT (1 << 2)
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# define AVIVO_I2C_STATUS_GO (1 << 3)
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# define AVIVO_I2C_STATUS_MASK 0x7
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/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
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* DONE? */
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# define AVIVO_I2C_STATUS_CMD_RESET 0x7
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# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3)
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#define AVIVO_I2C_STOP 0x7d34
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#define AVIVO_I2C_START_CNTL 0x7d38
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# define AVIVO_I2C_START (1 << 8)
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# define AVIVO_I2C_CONNECTOR0 (0 << 16)
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# define AVIVO_I2C_CONNECTOR1 (1 << 16)
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#define R520_I2C_START (1<<0)
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#define R520_I2C_STOP (1<<1)
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#define R520_I2C_RX (1<<2)
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#define R520_I2C_EN (1<<8)
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#define R520_I2C_DDC1 (0<<16)
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#define R520_I2C_DDC2 (1<<16)
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#define R520_I2C_DDC3 (2<<16)
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#define R520_I2C_DDC_MASK (3<<16)
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#define AVIVO_I2C_CONTROL2 0x7d3c
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# define AVIVO_I2C_7D3C_SIZE_SHIFT 8
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# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8)
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#define AVIVO_I2C_CONTROL3 0x7d40
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/* Reading is done 4 bytes at a time: read the bottom 8 bits from
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* 7d44, four times in a row.
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* Writing is a little more complex. First write DATA with
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* 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
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* magic number, zz is, I think, the slave address, and yy is the byte
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* you want to write. */
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#define AVIVO_I2C_DATA 0x7d44
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#define R520_I2C_ADDR_COUNT_MASK (0x7)
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#define R520_I2C_DATA_COUNT_SHIFT (8)
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#define R520_I2C_DATA_COUNT_MASK (0xF00)
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#define AVIVO_I2C_CNTL 0x7d50
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# define AVIVO_I2C_EN (1 << 0)
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# define AVIVO_I2C_RESET (1 << 8)
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#define AVIVO_DC_I2C_STATUS1 0x7d30
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# define AVIVO_DC_I2C_DONE (1 << 0)
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# define AVIVO_DC_I2C_NACK (1 << 1)
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# define AVIVO_DC_I2C_HALT (1 << 2)
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# define AVIVO_DC_I2C_GO (1 << 3)
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#define AVIVO_DC_I2C_RESET 0x7d34
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# define AVIVO_DC_I2C_SOFT_RESET (1 << 0)
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# define AVIVO_DC_I2C_ABORT (1 << 8)
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#define AVIVO_DC_I2C_CONTROL1 0x7d38
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# define AVIVO_DC_I2C_START (1 << 0)
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# define AVIVO_DC_I2C_STOP (1 << 1)
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# define AVIVO_DC_I2C_RECEIVE (1 << 2)
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# define AVIVO_DC_I2C_EN (1 << 8)
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# define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16)
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# define AVIVO_SEL_DDC1 0
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# define AVIVO_SEL_DDC2 1
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# define AVIVO_SEL_DDC3 2
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#define AVIVO_DC_I2C_CONTROL2 0x7d3c
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# define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0)
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# define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8)
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#define AVIVO_DC_I2C_CONTROL3 0x7d40
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# define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0)
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# define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1)
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# define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7)
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# define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8)
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# define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16)
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# define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24)
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#define AVIVO_DC_I2C_DATA 0x7d44
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#define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48
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# define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0)
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# define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8)
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# define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16)
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#define AVIVO_DC_I2C_ARBITRATION 0x7d50
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# define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0)
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# define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1)
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# define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8)
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# define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9)
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# define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16)
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# define AVIVO_DC_I2C_HW_USING_I2C (1 << 17)
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#define AVIVO_DC_GPIO_DDC1_MASK 0x7e40
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#define AVIVO_DC_GPIO_DDC1_A 0x7e44
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#define AVIVO_DC_GPIO_DDC1_EN 0x7e48
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#define AVIVO_DC_GPIO_DDC1_Y 0x7e4c
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#define AVIVO_DC_GPIO_DDC2_MASK 0x7e50
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#define AVIVO_DC_GPIO_DDC2_A 0x7e54
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#define AVIVO_DC_GPIO_DDC2_EN 0x7e58
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#define AVIVO_DC_GPIO_DDC2_Y 0x7e5c
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#define AVIVO_DC_GPIO_DDC3_MASK 0x7e60
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#define AVIVO_DC_GPIO_DDC3_A 0x7e64
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#define AVIVO_DC_GPIO_DDC3_EN 0x7e68
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#define AVIVO_DC_GPIO_DDC3_Y 0x7e6c
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#define AVIVO_DISP_INTERRUPT_STATUS 0x7edc
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# define AVIVO_D1_VBLANK_INTERRUPT (1 << 4)
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@@ -829,6 +829,7 @@ struct radeon_device {
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struct r600_ih ih; /* r6/700 interrupt ring */
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struct workqueue_struct *wq;
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struct work_struct hotplug_work;
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struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
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/* audio stuff */
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struct timer_list audio_timer;
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@@ -486,9 +486,65 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
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i2c.y_data_reg = ddc_line;
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}
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if (rdev->family < CHIP_R200)
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i2c.hw_capable = false;
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else {
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switch (rdev->family) {
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case CHIP_R100:
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case CHIP_RV100:
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case CHIP_RS100:
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case CHIP_RV200:
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case CHIP_RS200:
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case CHIP_RS300:
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switch (ddc_line) {
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case RADEON_GPIO_DVI_DDC:
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/* in theory this should be hw capable,
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* but it doesn't seem to work
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*/
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i2c.hw_capable = false;
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break;
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default:
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i2c.hw_capable = false;
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break;
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}
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break;
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case CHIP_R200:
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switch (ddc_line) {
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case RADEON_GPIO_DVI_DDC:
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case RADEON_GPIO_MONID:
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i2c.hw_capable = true;
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break;
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default:
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i2c.hw_capable = false;
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break;
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}
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break;
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case CHIP_RV250:
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case CHIP_RV280:
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switch (ddc_line) {
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case RADEON_GPIO_VGA_DDC:
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case RADEON_GPIO_DVI_DDC:
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case RADEON_GPIO_CRT2_DDC:
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i2c.hw_capable = true;
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break;
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default:
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i2c.hw_capable = false;
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break;
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}
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break;
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case CHIP_R300:
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case CHIP_R350:
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switch (ddc_line) {
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case RADEON_GPIO_VGA_DDC:
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case RADEON_GPIO_DVI_DDC:
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i2c.hw_capable = true;
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break;
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default:
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i2c.hw_capable = false;
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break;
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}
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break;
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case CHIP_RV350:
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case CHIP_RV380:
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case CHIP_RS400:
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case CHIP_RS480:
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switch (ddc_line) {
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case RADEON_GPIO_VGA_DDC:
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case RADEON_GPIO_DVI_DDC:
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@@ -504,6 +560,10 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
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i2c.hw_capable = false;
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break;
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}
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break;
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default:
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i2c.hw_capable = false;
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break;
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}
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i2c.mm_i2c = false;
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i2c.i2c_id = 0;
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@@ -1253,7 +1313,10 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder
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tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
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break;
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case DDC_LCD: /* MM i2c */
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DRM_ERROR("MM i2c requires hw i2c engine\n");
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i2c_bus.valid = true;
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i2c_bus.hw_capable = true;
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i2c_bus.mm_i2c = true;
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tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
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break;
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default:
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DRM_ERROR("Unsupported gpio %d\n", gpio);
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@@ -638,6 +638,7 @@ int radeon_device_init(struct radeon_device *rdev,
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mutex_init(&rdev->cs_mutex);
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mutex_init(&rdev->ib_pool.mutex);
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mutex_init(&rdev->cp.mutex);
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mutex_init(&rdev->dc_hw_i2c_mutex);
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if (rdev->family >= CHIP_R600)
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spin_lock_init(&rdev->ih.lock);
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mutex_init(&rdev->gem.mutex);
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File diff suppressed because it is too large
Load Diff
@@ -1060,32 +1060,38 @@
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/* Multimedia I2C bus */
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#define RADEON_I2C_CNTL_0 0x0090
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#define RADEON_I2C_DONE (1 << 0)
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#define RADEON_I2C_NACK (1 << 1)
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#define RADEON_I2C_HALT (1 << 2)
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#define RADEON_I2C_SOFT_RST (1 << 5)
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#define RADEON_I2C_DRIVE_EN (1 << 6)
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#define RADEON_I2C_DRIVE_SEL (1 << 7)
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#define RADEON_I2C_START (1 << 8)
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#define RADEON_I2C_STOP (1 << 9)
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#define RADEON_I2C_RECEIVE (1 << 10)
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#define RADEON_I2C_ABORT (1 << 11)
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#define RADEON_I2C_GO (1 << 12)
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#define RADEON_I2C_PRESCALE_SHIFT 16
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# define RADEON_I2C_DONE (1 << 0)
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# define RADEON_I2C_NACK (1 << 1)
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# define RADEON_I2C_HALT (1 << 2)
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# define RADEON_I2C_SOFT_RST (1 << 5)
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# define RADEON_I2C_DRIVE_EN (1 << 6)
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# define RADEON_I2C_DRIVE_SEL (1 << 7)
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# define RADEON_I2C_START (1 << 8)
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# define RADEON_I2C_STOP (1 << 9)
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# define RADEON_I2C_RECEIVE (1 << 10)
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# define RADEON_I2C_ABORT (1 << 11)
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# define RADEON_I2C_GO (1 << 12)
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# define RADEON_I2C_PRESCALE_SHIFT 16
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#define RADEON_I2C_CNTL_1 0x0094
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#define RADEON_I2C_DATA_COUNT_SHIFT 0
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#define RADEON_I2C_ADDR_COUNT_SHIFT 4
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#define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8
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#define RADEON_I2C_SEL (1 << 16)
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#define RADEON_I2C_EN (1 << 17)
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#define RADEON_I2C_TIME_LIMIT_SHIFT 24
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# define RADEON_I2C_DATA_COUNT_SHIFT 0
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# define RADEON_I2C_ADDR_COUNT_SHIFT 4
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# define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8
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# define RADEON_I2C_SEL (1 << 16)
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# define RADEON_I2C_EN (1 << 17)
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# define RADEON_I2C_TIME_LIMIT_SHIFT 24
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#define RADEON_I2C_DATA 0x0098
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#define RADEON_DVI_I2C_CNTL_0 0x02e0
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# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)
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# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */
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# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */
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# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */
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# define R200_SEL_DDC1 0 /* depends on asic */
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# define R200_SEL_DDC2 1 /* depends on asic */
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# define R200_SEL_DDC3 2 /* depends on asic */
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# define RADEON_SW_WANTS_TO_USE_DVI_I2C (1 << 13)
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# define RADEON_SW_CAN_USE_DVI_I2C (1 << 13)
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# define RADEON_SW_DONE_USING_DVI_I2C (1 << 14)
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# define RADEON_HW_NEEDS_DVI_I2C (1 << 14)
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# define RADEON_ABORT_HW_DVI_I2C (1 << 15)
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# define RADEON_HW_USING_DVI_I2C (1 << 15)
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#define RADEON_DVI_I2C_CNTL_1 0x02e4
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#define RADEON_DVI_I2C_DATA 0x02e8
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