You've already forked linux-apfs
mirror of
https://github.com/linux-apfs/linux-apfs.git
synced 2026-05-01 15:00:59 -07:00
Merge branches 'ib-mfd-arm-i2c-4.14', 'ib-mfd-arm-usb-video-4.14', 'ib-mfd-hwmon-4.14', 'ib-mfd-iio-pwm-4.14', 'ib-mfd-input-rtc-4.14', 'ib-mfd-many-4.14' and 'ib-mfd-pinctrl-regulator-4.14' into ibs-for-mfd-merged
This commit is contained in:
Lee Jones
@@ -0,0 +1,57 @@
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_count0_preset
|
||||
KernelVersion: 4.13
|
||||
Contact: fabrice.gasnier@st.com
|
||||
Description:
|
||||
Reading returns the current preset value. Writing sets the
|
||||
preset value. Encoder counts continuously from 0 to preset
|
||||
value, depending on direction (up/down).
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_count_quadrature_mode_available
|
||||
KernelVersion: 4.13
|
||||
Contact: fabrice.gasnier@st.com
|
||||
Description:
|
||||
Reading returns the list possible quadrature modes.
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_count0_quadrature_mode
|
||||
KernelVersion: 4.13
|
||||
Contact: fabrice.gasnier@st.com
|
||||
Description:
|
||||
Configure the device counter quadrature modes:
|
||||
- non-quadrature:
|
||||
Encoder IN1 input servers as the count input (up
|
||||
direction).
|
||||
- quadrature:
|
||||
Encoder IN1 and IN2 inputs are mixed to get direction
|
||||
and count.
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_count_polarity_available
|
||||
KernelVersion: 4.13
|
||||
Contact: fabrice.gasnier@st.com
|
||||
Description:
|
||||
Reading returns the list possible active edges.
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_count0_polarity
|
||||
KernelVersion: 4.13
|
||||
Contact: fabrice.gasnier@st.com
|
||||
Description:
|
||||
Configure the device encoder/counter active edge:
|
||||
- rising-edge
|
||||
- falling-edge
|
||||
- both-edges
|
||||
|
||||
In non-quadrature mode, device counts up on active edge.
|
||||
In quadrature mode, encoder counting scenarios are as follows:
|
||||
----------------------------------------------------------------
|
||||
| Active | Level on | IN1 signal | IN2 signal |
|
||||
| edge | opposite |------------------------------------------
|
||||
| | signal | Rising | Falling | Rising | Falling |
|
||||
----------------------------------------------------------------
|
||||
| Rising | High -> | Down | - | Up | - |
|
||||
| edge | Low -> | Up | - | Down | - |
|
||||
----------------------------------------------------------------
|
||||
| Falling | High -> | - | Up | - | Down |
|
||||
| edge | Low -> | - | Down | - | Up |
|
||||
----------------------------------------------------------------
|
||||
| Both | High -> | Down | Up | Up | Down |
|
||||
| edges | Low -> | Up | Down | Down | Up |
|
||||
----------------------------------------------------------------
|
||||
@@ -237,6 +237,14 @@ are the following:
|
||||
This attribute is not present if the scaling driver in use does not
|
||||
support it.
|
||||
|
||||
``cpuinfo_cur_freq``
|
||||
Current frequency of the CPUs belonging to this policy as obtained from
|
||||
the hardware (in KHz).
|
||||
|
||||
This is expected to be the frequency the hardware actually runs at.
|
||||
If that frequency cannot be determined, this attribute should not
|
||||
be present.
|
||||
|
||||
``cpuinfo_max_freq``
|
||||
Maximum possible operating frequency the CPUs belonging to this policy
|
||||
can run at (in kHz).
|
||||
|
||||
@@ -343,3 +343,4 @@ Version History
|
||||
1.11.0 Fix table line argument order
|
||||
(wrong raid10_copies/raid10_format sequence)
|
||||
1.11.1 Add raid4/5/6 journal write-back support via journal_mode option
|
||||
1.12.1 fix for MD deadlock between mddev_suspend() and md_write_start() available
|
||||
|
||||
@@ -1,14 +1,22 @@
|
||||
* Renesas R-Car SATA
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain one of the following:
|
||||
- compatible : should contain one or more of the following:
|
||||
- "renesas,sata-r8a7779" for R-Car H1
|
||||
("renesas,rcar-sata" is deprecated)
|
||||
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
|
||||
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
|
||||
- "renesas,sata-r8a7791" for R-Car M2-W
|
||||
- "renesas,sata-r8a7793" for R-Car M2-N
|
||||
- "renesas,sata-r8a7795" for R-Car H3
|
||||
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
|
||||
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
|
||||
- "renesas,rcar-sata" is deprecated
|
||||
|
||||
When compatible with the generic version nodes
|
||||
must list the SoC-specific version corresponding
|
||||
to the platform first followed by the generic
|
||||
version.
|
||||
|
||||
- reg : address and length of the SATA registers;
|
||||
- interrupts : must consist of one interrupt specifier.
|
||||
- clocks : must contain a reference to the functional clock.
|
||||
@@ -16,7 +24,7 @@ Required properties:
|
||||
Example:
|
||||
|
||||
sata0: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a7791";
|
||||
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
|
||||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@@ -8,7 +8,6 @@ Required properties:
|
||||
|
||||
Optional properties:
|
||||
- clocks: Reference to the crypto engine clock.
|
||||
- dma-mask: The address mask limitation. Defaults to 64.
|
||||
|
||||
Example:
|
||||
|
||||
@@ -24,6 +23,5 @@ Example:
|
||||
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
|
||||
"eip";
|
||||
clocks = <&cpm_syscon0 1 26>;
|
||||
dma-mask = <0xff 0xffffffff>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -0,0 +1,5 @@
|
||||
Exportable MPIO interface of Exar UART chips
|
||||
|
||||
Required properties of the device:
|
||||
- exar,first-pin: first exportable pins (0..15)
|
||||
- ngpios: number of exportable pins (1..16)
|
||||
@@ -40,7 +40,7 @@ Optional properties:
|
||||
Example for a Mali-T760:
|
||||
|
||||
gpu@ffa30000 {
|
||||
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
|
||||
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
|
||||
reg = <0xffa30000 0x10000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
@@ -0,0 +1,27 @@
|
||||
STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter
|
||||
|
||||
STM32 Low-Power Timer provides several counter modes. It can be used as:
|
||||
- quadrature encoder to detect angular position and direction of rotary
|
||||
elements, from IN1 and IN2 input signals.
|
||||
- simple counter from IN1 input signal.
|
||||
|
||||
Must be a sub-node of an STM32 Low-Power Timer device tree node.
|
||||
See ../mfd/stm32-lptimer.txt for details about the parent node.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32-lptimer-counter".
|
||||
- pinctrl-names: Set to "default".
|
||||
- pinctrl-0: List of phandles pointing to pin configuration nodes,
|
||||
to set IN1/IN2 pins in mode of operation for Low-Power
|
||||
Timer input on external pin.
|
||||
|
||||
Example:
|
||||
timer@40002400 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
...
|
||||
counter {
|
||||
compatible = "st,stm32-lptimer-counter";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lptim1_in_pins>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,23 @@
|
||||
STMicroelectronics STM32 Low-Power Timer Trigger
|
||||
|
||||
STM32 Low-Power Timer provides trigger source (LPTIM output) that can be used
|
||||
by STM32 internal ADC and/or DAC.
|
||||
|
||||
Must be a sub-node of an STM32 Low-Power Timer device tree node.
|
||||
See ../mfd/stm32-lptimer.txt for details about the parent node.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32-lptimer-trigger".
|
||||
- reg: Identify trigger hardware block. Must be 0, 1 or 2
|
||||
respectively for lptimer1, lptimer2 or lptimer3
|
||||
trigger output.
|
||||
|
||||
Example:
|
||||
timer@40002400 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
...
|
||||
trigger@0 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
@@ -1,11 +1,14 @@
|
||||
RK8XX Power Management Integrated Circuit
|
||||
|
||||
The rk8xx family current members:
|
||||
rk805
|
||||
rk808
|
||||
rk818
|
||||
|
||||
Required properties:
|
||||
- compatible: "rockchip,rk808", "rockchip,rk818"
|
||||
- compatible: "rockchip,rk805"
|
||||
- compatible: "rockchip,rk808"
|
||||
- compatible: "rockchip,rk818"
|
||||
- reg: I2C slave address
|
||||
- interrupt-parent: The parent interrupt controller.
|
||||
- interrupts: the interrupt outputs of the controller.
|
||||
@@ -18,6 +21,14 @@ Optional properties:
|
||||
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
|
||||
the system power.
|
||||
|
||||
Optional RK805 properties:
|
||||
- vcc1-supply: The input supply for DCDC_REG1
|
||||
- vcc2-supply: The input supply for DCDC_REG2
|
||||
- vcc3-supply: The input supply for DCDC_REG3
|
||||
- vcc4-supply: The input supply for DCDC_REG4
|
||||
- vcc5-supply: The input supply for LDO_REG1 and LDO_REG2
|
||||
- vcc6-supply: The input supply for LDO_REG3
|
||||
|
||||
Optional RK808 properties:
|
||||
- vcc1-supply: The input supply for DCDC_REG1
|
||||
- vcc2-supply: The input supply for DCDC_REG2
|
||||
@@ -56,6 +67,15 @@ by a child node of the 'regulators' node.
|
||||
/* standard regulator bindings here */
|
||||
};
|
||||
|
||||
Following regulators of the RK805 PMIC regulators are supported. Note that
|
||||
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
|
||||
number as described in RK805 datasheet.
|
||||
|
||||
- DCDC_REGn
|
||||
- valid values for n are 1 to 4.
|
||||
- LDO_REGn
|
||||
- valid values for n are 1 to 3
|
||||
|
||||
Following regulators of the RK808 PMIC block are supported. Note that
|
||||
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
|
||||
number as described in RK808 datasheet.
|
||||
|
||||
@@ -0,0 +1,48 @@
|
||||
STMicroelectronics STM32 Low-Power Timer
|
||||
|
||||
The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
|
||||
functions:
|
||||
- PWM output (with programmable prescaler, configurable polarity)
|
||||
- Quadrature encoder, counter
|
||||
- Trigger source for STM32 ADC/DAC (LPTIM_OUT)
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32-lptimer".
|
||||
- reg: Offset and length of the device's register set.
|
||||
- clocks: Phandle to the clock used by the LP Timer module.
|
||||
- clock-names: Must be "mux".
|
||||
- #address-cells: Should be '<1>'.
|
||||
- #size-cells: Should be '<0>'.
|
||||
|
||||
Optional subnodes:
|
||||
- pwm: See ../pwm/pwm-stm32-lp.txt
|
||||
- counter: See ../iio/timer/stm32-lptimer-cnt.txt
|
||||
- trigger: See ../iio/timer/stm32-lptimer-trigger.txt
|
||||
|
||||
Example:
|
||||
|
||||
timer@40002400 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x40002400 0x400>;
|
||||
clocks = <&timer_clk>;
|
||||
clock-names = "mux";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lppwm1_pins>;
|
||||
};
|
||||
|
||||
trigger@0 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-lptimer-counter";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lptim1_in_pins>;
|
||||
};
|
||||
};
|
||||
@@ -78,7 +78,6 @@ Example:
|
||||
};
|
||||
|
||||
dwmmc0@12200000 {
|
||||
num-slots = <1>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
broken-cd;
|
||||
|
||||
@@ -24,6 +24,5 @@ Example:
|
||||
|
||||
fifo-depth = <0x20>;
|
||||
bus-width = <4>;
|
||||
num-slots = <1>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
@@ -36,7 +36,6 @@ Example:
|
||||
|
||||
/* Board portion */
|
||||
dwmmc0@fcd03000 {
|
||||
num-slots = <1>;
|
||||
vmmc-supply = <&ldo12>;
|
||||
fifo-depth = <0x100>;
|
||||
pinctrl-names = "default";
|
||||
@@ -52,7 +51,6 @@ Example:
|
||||
|
||||
dwmmc_1: dwmmc1@f723e000 {
|
||||
compatible = "hisilicon,hi6220-dw-mshc";
|
||||
num-slots = <0x1>;
|
||||
bus-width = <0x4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
|
||||
@@ -12,12 +12,12 @@ Required Properties:
|
||||
* #address-cells: should be 1.
|
||||
* #size-cells: should be 0.
|
||||
|
||||
# Slots: The slot specific information are contained within child-nodes with
|
||||
each child-node representing a supported slot. There should be atleast one
|
||||
child node representing a card slot. The name of the child node representing
|
||||
the slot is recommended to be slot@n where n is the unique number of the slot
|
||||
connected to the controller. The following are optional properties which
|
||||
can be included in the slot child node.
|
||||
# Slots (DEPRECATED): The slot specific information are contained within
|
||||
child-nodes with each child-node representing a supported slot. There should
|
||||
be atleast one child node representing a card slot. The name of the child node
|
||||
representing the slot is recommended to be slot@n where n is the unique number
|
||||
of the slot connected to the controller. The following are optional properties
|
||||
which can be included in the slot child node.
|
||||
|
||||
* reg: specifies the physical slot number. The valid values of this
|
||||
property is 0 to (num-slots -1), where num-slots is the value
|
||||
@@ -63,7 +63,7 @@ Optional properties:
|
||||
clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default.
|
||||
(Use the "max-frequency" instead of "clock-freq-min-max".)
|
||||
|
||||
* num-slots: specifies the number of slots supported by the controller.
|
||||
* num-slots (DEPRECATED): specifies the number of slots supported by the controller.
|
||||
The number of physical slots actually used could be equal or less than the
|
||||
value specified by num-slots. If this property is not specified, the value
|
||||
of num-slot property is assumed to be 1.
|
||||
@@ -124,7 +124,6 @@ board specific portions as listed below.
|
||||
dwmmc0@12200000 {
|
||||
clock-frequency = <400000000>;
|
||||
clock-freq-min-max = <400000 200000000>;
|
||||
num-slots = <1>;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
@@ -139,7 +138,6 @@ board specific portions as listed below.
|
||||
dwmmc0@12200000 {
|
||||
clock-frequency = <400000000>;
|
||||
clock-freq-min-max = <400000 200000000>;
|
||||
num-slots = <1>;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
|
||||
@@ -25,7 +25,6 @@ Example:
|
||||
clock-frequency = <50000000>;
|
||||
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
|
||||
clock-names = "biu", "ciu";
|
||||
num-slots = <1>;
|
||||
max-frequency = <50000000>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
|
||||
@@ -11,6 +11,7 @@ Required properties:
|
||||
- reg-names: Names of the registers.
|
||||
"amac_base": Address and length of the GMAC registers
|
||||
"idm_base": Address and length of the GMAC IDM registers
|
||||
(required for NSP and Northstar2)
|
||||
"nicpm_base": Address and length of the NIC Port Manager
|
||||
registers (required for Northstar2)
|
||||
- interrupts: Interrupt number
|
||||
|
||||
@@ -1,24 +0,0 @@
|
||||
Broadcom GMAC Ethernet Controller Device Tree Bindings
|
||||
-------------------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: "brcm,bgmac-nsp"
|
||||
- reg: Address and length of the GMAC registers,
|
||||
Address and length of the GMAC IDM registers
|
||||
- reg-names: Names of the registers. Must have both "gmac_base" and
|
||||
"idm_base"
|
||||
- interrupts: Interrupt number
|
||||
|
||||
Optional properties:
|
||||
- mac-address: See ethernet.txt file in the same directory
|
||||
|
||||
Examples:
|
||||
|
||||
gmac0: ethernet@18022000 {
|
||||
compatible = "brcm,bgmac-nsp";
|
||||
reg = <0x18022000 0x1000>,
|
||||
<0x18110000 0x1000>;
|
||||
reg-names = "gmac_base", "idm_base";
|
||||
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -1,84 +0,0 @@
|
||||
* Allwinner sun8i GMAC ethernet controller
|
||||
|
||||
This device is a platform glue layer for stmmac.
|
||||
Please see stmmac.txt for the other unchanged properties.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following string:
|
||||
"allwinner,sun8i-a83t-emac"
|
||||
"allwinner,sun8i-h3-emac"
|
||||
"allwinner,sun8i-v3s-emac"
|
||||
"allwinner,sun50i-a64-emac"
|
||||
- reg: address and length of the register for the device.
|
||||
- interrupts: interrupt for the device
|
||||
- interrupt-names: should be "macirq"
|
||||
- clocks: A phandle to the reference clock for this device
|
||||
- clock-names: should be "stmmaceth"
|
||||
- resets: A phandle to the reset control for this device
|
||||
- reset-names: should be "stmmaceth"
|
||||
- phy-mode: See ethernet.txt
|
||||
- phy-handle: See ethernet.txt
|
||||
- #address-cells: shall be 1
|
||||
- #size-cells: shall be 0
|
||||
- syscon: A phandle to the syscon of the SoC with one of the following
|
||||
compatible string:
|
||||
- allwinner,sun8i-h3-system-controller
|
||||
- allwinner,sun8i-v3s-system-controller
|
||||
- allwinner,sun50i-a64-system-controller
|
||||
- allwinner,sun8i-a83t-system-controller
|
||||
|
||||
Optional properties:
|
||||
- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
|
||||
- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
|
||||
Both delay properties need to be a multiple of 100. They control the delay for
|
||||
external PHY.
|
||||
|
||||
Optional properties for the following compatibles:
|
||||
- "allwinner,sun8i-h3-emac",
|
||||
- "allwinner,sun8i-v3s-emac":
|
||||
- allwinner,leds-active-low: EPHY LEDs are active low
|
||||
|
||||
Required child node of emac:
|
||||
- mdio bus node: should be named mdio
|
||||
|
||||
Required properties of the mdio node:
|
||||
- #address-cells: shall be 1
|
||||
- #size-cells: shall be 0
|
||||
|
||||
The device node referenced by "phy" or "phy-handle" should be a child node
|
||||
of the mdio node. See phy.txt for the generic PHY bindings.
|
||||
|
||||
Required properties of the phy node with the following compatibles:
|
||||
- "allwinner,sun8i-h3-emac",
|
||||
- "allwinner,sun8i-v3s-emac":
|
||||
- clocks: a phandle to the reference clock for the EPHY
|
||||
- resets: a phandle to the reset control for the EPHY
|
||||
|
||||
Example:
|
||||
|
||||
emac: ethernet@1c0b000 {
|
||||
compatible = "allwinner,sun8i-h3-emac";
|
||||
syscon = <&syscon>;
|
||||
reg = <0x01c0b000 0x104>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
resets = <&ccu RST_BUS_EMAC>;
|
||||
reset-names = "stmmaceth";
|
||||
clocks = <&ccu CLK_BUS_EMAC>;
|
||||
clock-names = "stmmaceth";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy-handle = <&int_mii_phy>;
|
||||
phy-mode = "mii";
|
||||
allwinner,leds-active-low;
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
int_mii_phy: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
clocks = <&ccu CLK_BUS_EPHY>;
|
||||
resets = <&ccu RST_BUS_EPHY>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -4,7 +4,7 @@ Required properties:
|
||||
- compatible: Should be one of the following.
|
||||
- "rockchip,rk3066a-efuse" - for RK3066a SoCs.
|
||||
- "rockchip,rk3188-efuse" - for RK3188 SoCs.
|
||||
- "rockchip,rk322x-efuse" - for RK322x SoCs.
|
||||
- "rockchip,rk3228-efuse" - for RK3228 SoCs.
|
||||
- "rockchip,rk3288-efuse" - for RK3288 SoCs.
|
||||
- "rockchip,rk3399-efuse" - for RK3399 SoCs.
|
||||
- reg: Should contain the registers location and exact eFuse size
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user