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Merge branch '4.0-fixes' into mips-for-linux-next
This commit is contained in:
Ralf Baechle
+37
-2
@@ -415,6 +415,7 @@ config MIPS_MALTA
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_HAS_CPU_MIPS32_R3_5
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select SYS_HAS_CPU_MIPS32_R5
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select SYS_HAS_CPU_MIPS32_R6
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select SYS_HAS_CPU_MIPS64_R1
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select SYS_HAS_CPU_MIPS64_R2
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@@ -424,6 +425,7 @@ config MIPS_MALTA
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_HIGHMEM
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_MICROMIPS
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select SYS_SUPPORTS_MIPS_CMP
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@@ -1638,6 +1640,33 @@ config CPU_MIPS32_3_5_EVA
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One of its primary benefits is an increase in the maximum size
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of lowmem (up to 3GB). If unsure, say 'N' here.
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config CPU_MIPS32_R5_FEATURES
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bool "MIPS32 Release 5 Features"
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depends on SYS_HAS_CPU_MIPS32_R5
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depends on CPU_MIPS32_R2
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help
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Choose this option to build a kernel for release 2 or later of the
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MIPS32 architecture including features from release 5 such as
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support for Extended Physical Addressing (XPA).
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config CPU_MIPS32_R5_XPA
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bool "Extended Physical Addressing (XPA)"
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depends on CPU_MIPS32_R5_FEATURES
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depends on !EVA
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depends on !PAGE_SIZE_4KB
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depends on SYS_SUPPORTS_HIGHMEM
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select XPA
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select HIGHMEM
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select ARCH_PHYS_ADDR_T_64BIT
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default n
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help
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Choose this option if you want to enable the Extended Physical
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Addressing (XPA) on your MIPS32 core (such as P5600 series). The
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benefit is to increase physical addressing equal to or greater
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than 40 bits. Note that this has the side effect of turning on
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64-bit addressing which in turn makes the PTEs 64-bit in size.
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If unsure, say 'N' here.
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if CPU_LOONGSON2F
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config CPU_NOP_WORKAROUNDS
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bool
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@@ -1741,6 +1770,9 @@ config SYS_HAS_CPU_MIPS32_R2
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config SYS_HAS_CPU_MIPS32_R3_5
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bool
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config SYS_HAS_CPU_MIPS32_R5
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bool
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config SYS_HAS_CPU_MIPS32_R6
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bool
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@@ -1878,6 +1910,9 @@ config CPU_MIPSR6
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config EVA
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bool
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config XPA
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bool
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config SYS_SUPPORTS_32BIT_KERNEL
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bool
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config SYS_SUPPORTS_64BIT_KERNEL
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@@ -2114,7 +2149,7 @@ config MIPSR2_TO_R6_EMULATOR
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help
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Choose this option if you want to run non-R6 MIPS userland code.
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Even if you say 'Y' here, the emulator will still be disabled by
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default. You can enable it using the 'mipsr2emul' kernel option.
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default. You can enable it using the 'mipsr2emu' kernel option.
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The only reason this is a build-time option is to save ~14K from the
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final kernel image.
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comment "MIPS R2-to-R6 emulator is only available for UP kernels"
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@@ -2184,7 +2219,7 @@ config MIPS_CMP
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config MIPS_CPS
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bool "MIPS Coherent Processing System support"
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depends on SYS_SUPPORTS_MIPS_CPS
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depends on SYS_SUPPORTS_MIPS_CPS && !64BIT
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select MIPS_CM
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select MIPS_CPC
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select MIPS_CPS_PM if HOTPLUG_CPU
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+10
-4
@@ -197,11 +197,17 @@ endif
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# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
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# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
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# been fixed properly.
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mips-cflags := "$(cflags-y)"
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cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,$(mips-cflags),-msmartmips) -Wa,--no-warn
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cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,$(mips-cflags),-mmicromips)
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mips-cflags := $(cflags-y)
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ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y)
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smartmips-ase := $(call cc-option-yn,$(mips-cflags) -msmartmips)
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cflags-$(smartmips-ase) += -msmartmips -Wa,--no-warn
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endif
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ifeq ($(CONFIG_CPU_MICROMIPS),y)
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micromips-ase := $(call cc-option-yn,$(mips-cflags) -mmicromips)
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cflags-$(micromips-ase) += -mmicromips
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endif
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ifeq ($(CONFIG_CPU_HAS_MSA),y)
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toolchain-msa := $(call cc-option-yn,-$(mips-cflags),mhard-float -mfp64 -Wa$(comma)-mmsa)
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toolchain-msa := $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa)
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cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
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endif
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@@ -235,8 +235,8 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
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}
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if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0 &&
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bcm47xx_nvram_getenv("boardtype", buf2, sizeof(buf2)) >= 0) {
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for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) {
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bcm47xx_nvram_getenv("boardnum", buf2, sizeof(buf2)) >= 0) {
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for (e2 = bcm47xx_board_list_hw_version_num; e2->value1; e2++) {
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if (!strstarts(buf1, e2->value1) &&
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!strcmp(buf2, e2->value2))
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return &e2->board;
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@@ -17,7 +17,6 @@
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_gpio.h>
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void __init prom_init(void)
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{
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@@ -53,9 +52,6 @@ void __init prom_init(void)
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reg &= ~mask;
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bcm_perf_writel(reg, PERF_CKCTL_REG);
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|
||||
/* register gpiochip */
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bcm63xx_gpio_init();
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/* do low level board init */
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board_prom_init();
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||||
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||||
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@@ -20,6 +20,7 @@
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||||
#include <bcm63xx_cpu.h>
|
||||
#include <bcm63xx_regs.h>
|
||||
#include <bcm63xx_io.h>
|
||||
#include <bcm63xx_gpio.h>
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||||
|
||||
void bcm63xx_machine_halt(void)
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{
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@@ -160,6 +161,9 @@ void __init plat_mem_setup(void)
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int __init bcm63xx_register_devices(void)
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{
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/* register gpiochip */
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||||
bcm63xx_gpio_init();
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||||
|
||||
return board_register_devices();
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||||
}
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||||
|
||||
|
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@@ -306,7 +306,7 @@ void __init plat_swiotlb_setup(void)
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||||
swiotlbsize = 64 * (1<<20);
|
||||
}
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||||
#endif
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||||
#ifdef CONFIG_USB_OCTEON_OHCI
|
||||
#ifdef CONFIG_USB_OHCI_HCD_PLATFORM
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||||
/* OCTEON II ohci is only 32-bit. */
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if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
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swiotlbsize = 64 * (1<<20);
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@@ -11,6 +11,36 @@
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#define __ASM_ASM_EVA_H
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#ifndef __ASSEMBLY__
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/* Kernel variants */
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||||
#define kernel_cache(op, base) "cache " op ", " base "\n"
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#define kernel_ll(reg, addr) "ll " reg ", " addr "\n"
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#define kernel_sc(reg, addr) "sc " reg ", " addr "\n"
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#define kernel_lw(reg, addr) "lw " reg ", " addr "\n"
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#define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n"
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#define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n"
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#define kernel_lh(reg, addr) "lh " reg ", " addr "\n"
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#define kernel_lb(reg, addr) "lb " reg ", " addr "\n"
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#define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n"
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#define kernel_sw(reg, addr) "sw " reg ", " addr "\n"
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#define kernel_swl(reg, addr) "swl " reg ", " addr "\n"
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#define kernel_swr(reg, addr) "swr " reg ", " addr "\n"
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#define kernel_sh(reg, addr) "sh " reg ", " addr "\n"
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#define kernel_sb(reg, addr) "sb " reg ", " addr "\n"
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#ifdef CONFIG_32BIT
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/*
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* No 'sd' or 'ld' instructions in 32-bit but the code will
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* do the correct thing
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*/
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#define kernel_sd(reg, addr) user_sw(reg, addr)
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#define kernel_ld(reg, addr) user_lw(reg, addr)
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#else
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#define kernel_sd(reg, addr) "sd " reg", " addr "\n"
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#define kernel_ld(reg, addr) "ld " reg", " addr "\n"
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#endif /* CONFIG_32BIT */
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#ifdef CONFIG_EVA
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#define __BUILD_EVA_INSN(insn, reg, addr) \
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@@ -41,37 +71,60 @@
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#else
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#define user_cache(op, base) "cache " op ", " base "\n"
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#define user_ll(reg, addr) "ll " reg ", " addr "\n"
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#define user_sc(reg, addr) "sc " reg ", " addr "\n"
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#define user_lw(reg, addr) "lw " reg ", " addr "\n"
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#define user_lwl(reg, addr) "lwl " reg ", " addr "\n"
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#define user_lwr(reg, addr) "lwr " reg ", " addr "\n"
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#define user_lh(reg, addr) "lh " reg ", " addr "\n"
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#define user_lb(reg, addr) "lb " reg ", " addr "\n"
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#define user_lbu(reg, addr) "lbu " reg ", " addr "\n"
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#define user_sw(reg, addr) "sw " reg ", " addr "\n"
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#define user_swl(reg, addr) "swl " reg ", " addr "\n"
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#define user_swr(reg, addr) "swr " reg ", " addr "\n"
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#define user_sh(reg, addr) "sh " reg ", " addr "\n"
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#define user_sb(reg, addr) "sb " reg ", " addr "\n"
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#define user_cache(op, base) kernel_cache(op, base)
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#define user_ll(reg, addr) kernel_ll(reg, addr)
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#define user_sc(reg, addr) kernel_sc(reg, addr)
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#define user_lw(reg, addr) kernel_lw(reg, addr)
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#define user_lwl(reg, addr) kernel_lwl(reg, addr)
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#define user_lwr(reg, addr) kernel_lwr(reg, addr)
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#define user_lh(reg, addr) kernel_lh(reg, addr)
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#define user_lb(reg, addr) kernel_lb(reg, addr)
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#define user_lbu(reg, addr) kernel_lbu(reg, addr)
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#define user_sw(reg, addr) kernel_sw(reg, addr)
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#define user_swl(reg, addr) kernel_swl(reg, addr)
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#define user_swr(reg, addr) kernel_swr(reg, addr)
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#define user_sh(reg, addr) kernel_sh(reg, addr)
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#define user_sb(reg, addr) kernel_sb(reg, addr)
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
#define user_sd(reg, addr) kernel_sw(reg, addr)
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||||
#define user_ld(reg, addr) kernel_lw(reg, addr)
|
||||
#else
|
||||
#define user_sd(reg, addr) kernel_sd(reg, addr)
|
||||
#define user_ld(reg, addr) kernel_ld(reg, addr)
|
||||
#endif /* CONFIG_32BIT */
|
||||
|
||||
#endif /* CONFIG_EVA */
|
||||
|
||||
#else /* __ASSEMBLY__ */
|
||||
|
||||
#define kernel_cache(op, base) cache op, base
|
||||
#define kernel_ll(reg, addr) ll reg, addr
|
||||
#define kernel_sc(reg, addr) sc reg, addr
|
||||
#define kernel_lw(reg, addr) lw reg, addr
|
||||
#define kernel_lwl(reg, addr) lwl reg, addr
|
||||
#define kernel_lwr(reg, addr) lwr reg, addr
|
||||
#define kernel_lh(reg, addr) lh reg, addr
|
||||
#define kernel_lb(reg, addr) lb reg, addr
|
||||
#define kernel_lbu(reg, addr) lbu reg, addr
|
||||
#define kernel_sw(reg, addr) sw reg, addr
|
||||
#define kernel_swl(reg, addr) swl reg, addr
|
||||
#define kernel_swr(reg, addr) swr reg, addr
|
||||
#define kernel_sh(reg, addr) sh reg, addr
|
||||
#define kernel_sb(reg, addr) sb reg, addr
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
/*
|
||||
* No 'sd' or 'ld' instructions in 32-bit but the code will
|
||||
* do the correct thing
|
||||
*/
|
||||
#define user_sd(reg, addr) user_sw(reg, addr)
|
||||
#define user_ld(reg, addr) user_lw(reg, addr)
|
||||
#define kernel_sd(reg, addr) user_sw(reg, addr)
|
||||
#define kernel_ld(reg, addr) user_lw(reg, addr)
|
||||
#else
|
||||
#define user_sd(reg, addr) "sd " reg", " addr "\n"
|
||||
#define user_ld(reg, addr) "ld " reg", " addr "\n"
|
||||
#define kernel_sd(reg, addr) sd reg, addr
|
||||
#define kernel_ld(reg, addr) ld reg, addr
|
||||
#endif /* CONFIG_32BIT */
|
||||
|
||||
#endif /* CONFIG_EVA */
|
||||
|
||||
#else /* __ASSEMBLY__ */
|
||||
|
||||
#ifdef CONFIG_EVA
|
||||
|
||||
#define __BUILD_EVA_INSN(insn, reg, addr) \
|
||||
@@ -101,31 +154,27 @@
|
||||
#define user_sd(reg, addr) user_sw(reg, addr)
|
||||
#else
|
||||
|
||||
#define user_cache(op, base) cache op, base
|
||||
#define user_ll(reg, addr) ll reg, addr
|
||||
#define user_sc(reg, addr) sc reg, addr
|
||||
#define user_lw(reg, addr) lw reg, addr
|
||||
#define user_lwl(reg, addr) lwl reg, addr
|
||||
#define user_lwr(reg, addr) lwr reg, addr
|
||||
#define user_lh(reg, addr) lh reg, addr
|
||||
#define user_lb(reg, addr) lb reg, addr
|
||||
#define user_lbu(reg, addr) lbu reg, addr
|
||||
#define user_sw(reg, addr) sw reg, addr
|
||||
#define user_swl(reg, addr) swl reg, addr
|
||||
#define user_swr(reg, addr) swr reg, addr
|
||||
#define user_sh(reg, addr) sh reg, addr
|
||||
#define user_sb(reg, addr) sb reg, addr
|
||||
#define user_cache(op, base) kernel_cache(op, base)
|
||||
#define user_ll(reg, addr) kernel_ll(reg, addr)
|
||||
#define user_sc(reg, addr) kernel_sc(reg, addr)
|
||||
#define user_lw(reg, addr) kernel_lw(reg, addr)
|
||||
#define user_lwl(reg, addr) kernel_lwl(reg, addr)
|
||||
#define user_lwr(reg, addr) kernel_lwr(reg, addr)
|
||||
#define user_lh(reg, addr) kernel_lh(reg, addr)
|
||||
#define user_lb(reg, addr) kernel_lb(reg, addr)
|
||||
#define user_lbu(reg, addr) kernel_lbu(reg, addr)
|
||||
#define user_sw(reg, addr) kernel_sw(reg, addr)
|
||||
#define user_swl(reg, addr) kernel_swl(reg, addr)
|
||||
#define user_swr(reg, addr) kernel_swr(reg, addr)
|
||||
#define user_sh(reg, addr) kernel_sh(reg, addr)
|
||||
#define user_sb(reg, addr) kernel_sb(reg, addr)
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
/*
|
||||
* No 'sd' or 'ld' instructions in 32-bit but the code will
|
||||
* do the correct thing
|
||||
*/
|
||||
#define user_sd(reg, addr) user_sw(reg, addr)
|
||||
#define user_ld(reg, addr) user_lw(reg, addr)
|
||||
#define user_sd(reg, addr) kernel_sw(reg, addr)
|
||||
#define user_ld(reg, addr) kernel_lw(reg, addr)
|
||||
#else
|
||||
#define user_sd(reg, addr) sd reg, addr
|
||||
#define user_ld(reg, addr) ld reg, addr
|
||||
#define user_sd(reg, addr) kernel_sd(reg, addr)
|
||||
#define user_ld(reg, addr) kernel_sd(reg, addr)
|
||||
#endif /* CONFIG_32BIT */
|
||||
|
||||
#endif /* CONFIG_EVA */
|
||||
|
||||
@@ -29,6 +29,20 @@
|
||||
* - flush_icache_all() flush the entire instruction cache
|
||||
* - flush_data_cache_page() flushes a page from the data cache
|
||||
*/
|
||||
|
||||
/*
|
||||
* This flag is used to indicate that the page pointed to by a pte
|
||||
* is dirty and requires cleaning before returning it to the user.
|
||||
*/
|
||||
#define PG_dcache_dirty PG_arch_1
|
||||
|
||||
#define Page_dcache_dirty(page) \
|
||||
test_bit(PG_dcache_dirty, &(page)->flags)
|
||||
#define SetPageDcacheDirty(page) \
|
||||
set_bit(PG_dcache_dirty, &(page)->flags)
|
||||
#define ClearPageDcacheDirty(page) \
|
||||
clear_bit(PG_dcache_dirty, &(page)->flags)
|
||||
|
||||
extern void (*flush_cache_all)(void);
|
||||
extern void (*__flush_cache_all)(void);
|
||||
extern void (*flush_cache_mm)(struct mm_struct *mm);
|
||||
@@ -37,13 +51,15 @@ extern void (*flush_cache_range)(struct vm_area_struct *vma,
|
||||
unsigned long start, unsigned long end);
|
||||
extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
|
||||
extern void __flush_dcache_page(struct page *page);
|
||||
extern void __flush_icache_page(struct vm_area_struct *vma, struct page *page);
|
||||
|
||||
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
|
||||
static inline void flush_dcache_page(struct page *page)
|
||||
{
|
||||
if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
|
||||
if (cpu_has_dc_aliases)
|
||||
__flush_dcache_page(page);
|
||||
|
||||
else if (!cpu_has_ic_fills_f_dc)
|
||||
SetPageDcacheDirty(page);
|
||||
}
|
||||
|
||||
#define flush_dcache_mmap_lock(mapping) do { } while (0)
|
||||
@@ -61,6 +77,11 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
|
||||
static inline void flush_icache_page(struct vm_area_struct *vma,
|
||||
struct page *page)
|
||||
{
|
||||
if (!cpu_has_ic_fills_f_dc && (vma->vm_flags & VM_EXEC) &&
|
||||
Page_dcache_dirty(page)) {
|
||||
__flush_icache_page(vma, page);
|
||||
ClearPageDcacheDirty(page);
|
||||
}
|
||||
}
|
||||
|
||||
extern void (*flush_icache_range)(unsigned long start, unsigned long end);
|
||||
@@ -95,19 +116,6 @@ extern void (*flush_icache_all)(void);
|
||||
extern void (*local_flush_data_cache_page)(void * addr);
|
||||
extern void (*flush_data_cache_page)(unsigned long addr);
|
||||
|
||||
/*
|
||||
* This flag is used to indicate that the page pointed to by a pte
|
||||
* is dirty and requires cleaning before returning it to the user.
|
||||
*/
|
||||
#define PG_dcache_dirty PG_arch_1
|
||||
|
||||
#define Page_dcache_dirty(page) \
|
||||
test_bit(PG_dcache_dirty, &(page)->flags)
|
||||
#define SetPageDcacheDirty(page) \
|
||||
set_bit(PG_dcache_dirty, &(page)->flags)
|
||||
#define ClearPageDcacheDirty(page) \
|
||||
clear_bit(PG_dcache_dirty, &(page)->flags)
|
||||
|
||||
/* Run kernel code uncached, useful for cache probing functions. */
|
||||
unsigned long run_uncached(void *func);
|
||||
|
||||
|
||||
@@ -140,6 +140,9 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef cpu_has_xpa
|
||||
#define cpu_has_xpa (cpu_data[0].options & MIPS_CPU_XPA)
|
||||
#endif
|
||||
#ifndef cpu_has_vtag_icache
|
||||
#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
|
||||
#endif
|
||||
@@ -239,8 +242,39 @@
|
||||
/* MIPSR2 and MIPSR6 have a lot of similarities */
|
||||
#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
|
||||
|
||||
/*
|
||||
* cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
|
||||
*
|
||||
* Returns non-zero value if the current processor implementation requires
|
||||
* an IHB instruction to deal with an instruction hazard as per MIPS R2
|
||||
* architecture specification, zero otherwise.
|
||||
*/
|
||||
#ifndef cpu_has_mips_r2_exec_hazard
|
||||
#define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6)
|
||||
#define cpu_has_mips_r2_exec_hazard \
|
||||
({ \
|
||||
int __res; \
|
||||
\
|
||||
switch (current_cpu_type()) { \
|
||||
case CPU_M14KC: \
|
||||
case CPU_74K: \
|
||||
case CPU_1074K: \
|
||||
case CPU_PROAPTIV: \
|
||||
case CPU_P5600: \
|
||||
case CPU_M5150: \
|
||||
case CPU_QEMU_GENERIC: \
|
||||
case CPU_CAVIUM_OCTEON: \
|
||||
case CPU_CAVIUM_OCTEON_PLUS: \
|
||||
case CPU_CAVIUM_OCTEON2: \
|
||||
case CPU_CAVIUM_OCTEON3: \
|
||||
__res = 0; \
|
||||
break; \
|
||||
\
|
||||
default: \
|
||||
__res = 1; \
|
||||
} \
|
||||
\
|
||||
__res; \
|
||||
})
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
||||
@@ -377,7 +377,8 @@ enum cpu_type_enum {
|
||||
#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
|
||||
#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */
|
||||
#define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */
|
||||
#define MIPS_CPU_CDMM 0x2000000000ull /* CPU has Common Device Memory Map */
|
||||
#define MIPS_CPU_XPA 0x2000000000ull /* CPU supports Extended Physical Addressing */
|
||||
#define MIPS_CPU_CDMM 0x4000000000ull /* CPU has Common Device Memory Map */
|
||||
|
||||
/*
|
||||
* CPU ASE encodings
|
||||
|
||||
@@ -297,6 +297,9 @@ do { \
|
||||
if (personality(current->personality) != PER_LINUX) \
|
||||
set_personality(PER_LINUX); \
|
||||
\
|
||||
clear_thread_flag(TIF_HYBRID_FPREGS); \
|
||||
set_thread_flag(TIF_32BIT_FPREGS); \
|
||||
\
|
||||
mips_set_personality_fp(state); \
|
||||
\
|
||||
current->thread.abi = &mips_abi; \
|
||||
@@ -324,6 +327,8 @@ do { \
|
||||
do { \
|
||||
set_thread_flag(TIF_32BIT_REGS); \
|
||||
set_thread_flag(TIF_32BIT_ADDR); \
|
||||
clear_thread_flag(TIF_HYBRID_FPREGS); \
|
||||
set_thread_flag(TIF_32BIT_FPREGS); \
|
||||
\
|
||||
mips_set_personality_fp(state); \
|
||||
\
|
||||
|
||||
@@ -50,7 +50,6 @@
|
||||
#define cpu_has_mips32r2 0
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 1
|
||||
#define cpu_has_mips_r2_exec_hazard 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_dsp2 0
|
||||
#define cpu_has_mipsmt 0
|
||||
|
||||
@@ -11,9 +11,6 @@
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
||||
/* Some PCI cards require delays when accessing config space. */
|
||||
#define PCI_CONFIG_SPACE_DELAY 10000
|
||||
|
||||
/*
|
||||
* The physical memory base mapped by BAR1. 256MB at the end of the
|
||||
* first 4GB.
|
||||
|
||||
@@ -105,13 +105,16 @@ static inline void pmd_clear(pmd_t *pmdp)
|
||||
|
||||
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
|
||||
#define pte_page(x) pfn_to_page(pte_pfn(x))
|
||||
#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
|
||||
#define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
|
||||
static inline pte_t
|
||||
pfn_pte(unsigned long pfn, pgprot_t prot)
|
||||
{
|
||||
pte_t pte;
|
||||
pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
|
||||
pte.pte_low = pgprot_val(prot);
|
||||
|
||||
pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
|
||||
(pgprot_val(prot) & ~_PFNX_MASK);
|
||||
pte.pte_high = (pfn << _PFN_SHIFT) |
|
||||
(pgprot_val(prot) & ~_PFN_MASK);
|
||||
return pte;
|
||||
}
|
||||
|
||||
@@ -166,9 +169,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
|
||||
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
|
||||
|
||||
/* Swap entries must have VALID and GLOBAL bits cleared. */
|
||||
#define __swp_type(x) (((x).val >> 2) & 0x1f)
|
||||
#define __swp_offset(x) ((x).val >> 7)
|
||||
#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
|
||||
#define __swp_type(x) (((x).val >> 4) & 0x1f)
|
||||
#define __swp_offset(x) ((x).val >> 9)
|
||||
#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 9) })
|
||||
#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
|
||||
#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
|
||||
|
||||
|
||||
@@ -37,7 +37,11 @@
|
||||
/*
|
||||
* The following bits are implemented by the TLB hardware
|
||||
*/
|
||||
#define _PAGE_GLOBAL_SHIFT 0
|
||||
#define _PAGE_NO_EXEC_SHIFT 0
|
||||
#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
|
||||
#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
|
||||
#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
|
||||
#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
|
||||
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
|
||||
#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
|
||||
#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
|
||||
@@ -49,7 +53,7 @@
|
||||
/*
|
||||
* The following bits are implemented in software
|
||||
*/
|
||||
#define _PAGE_PRESENT_SHIFT (_CACHE_SHIFT + 3)
|
||||
#define _PAGE_PRESENT_SHIFT (24)
|
||||
#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
|
||||
#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
|
||||
#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
|
||||
@@ -62,6 +66,11 @@
|
||||
|
||||
#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
|
||||
|
||||
/*
|
||||
* Bits for extended EntryLo0/EntryLo1 registers
|
||||
*/
|
||||
#define _PFNX_MASK 0xffffff
|
||||
|
||||
#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
||||
|
||||
/*
|
||||
@@ -95,11 +104,7 @@
|
||||
|
||||
#else
|
||||
/*
|
||||
* When using the RI/XI bit support, we have 13 bits of flags below
|
||||
* the physical address. The RI/XI bits are placed such that a SRL 5
|
||||
* can strip off the software bits, then a ROTR 2 can move the RI/XI
|
||||
* into bits [63:62]. This also limits physical address to 56 bits,
|
||||
* which is more than we need right now.
|
||||
* Below are the "Normal" R4K cases
|
||||
*/
|
||||
|
||||
/*
|
||||
@@ -107,38 +112,59 @@
|
||||
*/
|
||||
#define _PAGE_PRESENT_SHIFT 0
|
||||
#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
|
||||
#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
|
||||
#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; })
|
||||
/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
|
||||
#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
|
||||
#else
|
||||
#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
|
||||
#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
|
||||
#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
|
||||
#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
|
||||
#endif
|
||||
#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
|
||||
#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
|
||||
#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
|
||||
#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
|
||||
|
||||
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
|
||||
/* huge tlb page */
|
||||
#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
|
||||
/* Huge TLB page */
|
||||
#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
|
||||
#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
|
||||
#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
|
||||
#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
|
||||
|
||||
/* Only R2 or newer cores have the XI bit */
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
|
||||
#else
|
||||
#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT)
|
||||
#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */
|
||||
#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT)
|
||||
#define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */
|
||||
#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
|
||||
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
|
||||
#endif /* CONFIG_CPU_MIPSR2 */
|
||||
|
||||
#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
|
||||
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
/* XI - page cannot be executed */
|
||||
#ifndef _PAGE_NO_EXEC_SHIFT
|
||||
#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
|
||||
#endif
|
||||
#define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
|
||||
|
||||
/* Page cannot be executed */
|
||||
#define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_SPLITTING_SHIFT + 1 : _PAGE_SPLITTING_SHIFT)
|
||||
#define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; })
|
||||
|
||||
/* Page cannot be read */
|
||||
#define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
|
||||
#define _PAGE_NO_READ ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; })
|
||||
/* RI - page cannot be read */
|
||||
#define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
|
||||
#define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
|
||||
#define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
|
||||
#define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
|
||||
|
||||
#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
|
||||
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
|
||||
|
||||
#else /* !CONFIG_CPU_MIPSR2 */
|
||||
#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
|
||||
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
|
||||
#endif /* CONFIG_CPU_MIPSR2 */
|
||||
|
||||
#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
|
||||
#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
|
||||
#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
|
||||
@@ -150,18 +176,26 @@
|
||||
|
||||
#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
|
||||
|
||||
#ifndef _PAGE_NO_EXEC
|
||||
#define _PAGE_NO_EXEC 0
|
||||
#endif
|
||||
#ifndef _PAGE_NO_READ
|
||||
#define _PAGE_NO_READ 0
|
||||
#endif
|
||||
|
||||
#define _PAGE_SILENT_READ _PAGE_VALID
|
||||
#define _PAGE_SILENT_WRITE _PAGE_DIRTY
|
||||
|
||||
#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
|
||||
|
||||
#ifndef _PAGE_NO_READ
|
||||
#define _PAGE_NO_READ ({BUG(); 0; })
|
||||
#define _PAGE_NO_READ_SHIFT ({BUG(); 0; })
|
||||
#endif
|
||||
#ifndef _PAGE_NO_EXEC
|
||||
#define _PAGE_NO_EXEC ({BUG(); 0; })
|
||||
#endif
|
||||
/*
|
||||
* The final layouts of the PTE bits are:
|
||||
*
|
||||
* 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
|
||||
* 32-bit, R1 or earler: CCC D V G M A W R P
|
||||
* 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
|
||||
* 32-bit, R2 or later: CCC D V G RI/R XI M A W P
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
@@ -171,6 +205,7 @@
|
||||
*/
|
||||
static inline uint64_t pte_to_entrylo(unsigned long pte_val)
|
||||
{
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
if (cpu_has_rixi) {
|
||||
int sa;
|
||||
#ifdef CONFIG_32BIT
|
||||
@@ -186,6 +221,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
|
||||
return (pte_val >> _PAGE_GLOBAL_SHIFT) |
|
||||
((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
|
||||
}
|
||||
#endif
|
||||
|
||||
return pte_val >> _PAGE_GLOBAL_SHIFT;
|
||||
}
|
||||
@@ -245,7 +281,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
|
||||
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
|
||||
#endif
|
||||
|
||||
#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
|
||||
#define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
|
||||
#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
|
||||
|
||||
#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
|
||||
|
||||
@@ -24,17 +24,17 @@ struct mm_struct;
|
||||
struct vm_area_struct;
|
||||
|
||||
#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
|
||||
#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_rixi ? 0 : _PAGE_READ) | \
|
||||
#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | \
|
||||
_page_cachable_default)
|
||||
#define PAGE_COPY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \
|
||||
(cpu_has_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default)
|
||||
#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \
|
||||
#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_NO_EXEC | \
|
||||
_page_cachable_default)
|
||||
#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
|
||||
_page_cachable_default)
|
||||
#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
|
||||
_PAGE_GLOBAL | _page_cachable_default)
|
||||
#define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
|
||||
_PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT)
|
||||
#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
|
||||
#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
|
||||
_page_cachable_default)
|
||||
#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
|
||||
__WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
|
||||
@@ -127,13 +127,9 @@ do { \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
|
||||
extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
|
||||
pte_t pteval);
|
||||
|
||||
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
|
||||
|
||||
#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
|
||||
#define pte_none(pte) (!(((pte).pte_high) & ~_PAGE_GLOBAL))
|
||||
#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
|
||||
|
||||
static inline void set_pte(pte_t *ptep, pte_t pte)
|
||||
@@ -142,18 +138,17 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
|
||||
smp_wmb();
|
||||
ptep->pte_low = pte.pte_low;
|
||||
|
||||
if (pte.pte_low & _PAGE_GLOBAL) {
|
||||
if (pte.pte_high & _PAGE_GLOBAL) {
|
||||
pte_t *buddy = ptep_buddy(ptep);
|
||||
/*
|
||||
* Make sure the buddy is global too (if it's !none,
|
||||
* it better already be global)
|
||||
*/
|
||||
if (pte_none(*buddy)) {
|
||||
buddy->pte_low |= _PAGE_GLOBAL;
|
||||
if (pte_none(*buddy))
|
||||
buddy->pte_high |= _PAGE_GLOBAL;
|
||||
}
|
||||
}
|
||||
}
|
||||
#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
|
||||
|
||||
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
||||
{
|
||||
@@ -161,8 +156,8 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
|
||||
|
||||
htw_stop();
|
||||
/* Preserve global status for the pair */
|
||||
if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
|
||||
null.pte_low = null.pte_high = _PAGE_GLOBAL;
|
||||
if (ptep_buddy(ptep)->pte_high & _PAGE_GLOBAL)
|
||||
null.pte_high = _PAGE_GLOBAL;
|
||||
|
||||
set_pte_at(mm, addr, ptep, null);
|
||||
htw_start();
|
||||
@@ -192,6 +187,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
|
||||
|
||||
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
||||
{
|
||||
@@ -242,21 +238,21 @@ static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
|
||||
|
||||
static inline pte_t pte_wrprotect(pte_t pte)
|
||||
{
|
||||
pte.pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
|
||||
pte.pte_low &= ~_PAGE_WRITE;
|
||||
pte.pte_high &= ~_PAGE_SILENT_WRITE;
|
||||
return pte;
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkclean(pte_t pte)
|
||||
{
|
||||
pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
|
||||
pte.pte_low &= ~_PAGE_MODIFIED;
|
||||
pte.pte_high &= ~_PAGE_SILENT_WRITE;
|
||||
return pte;
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkold(pte_t pte)
|
||||
{
|
||||
pte.pte_low &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
|
||||
pte.pte_low &= ~_PAGE_ACCESSED;
|
||||
pte.pte_high &= ~_PAGE_SILENT_READ;
|
||||
return pte;
|
||||
}
|
||||
@@ -264,30 +260,24 @@ static inline pte_t pte_mkold(pte_t pte)
|
||||
static inline pte_t pte_mkwrite(pte_t pte)
|
||||
{
|
||||
pte.pte_low |= _PAGE_WRITE;
|
||||
if (pte.pte_low & _PAGE_MODIFIED) {
|
||||
pte.pte_low |= _PAGE_SILENT_WRITE;
|
||||
if (pte.pte_low & _PAGE_MODIFIED)
|
||||
pte.pte_high |= _PAGE_SILENT_WRITE;
|
||||
}
|
||||
return pte;
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkdirty(pte_t pte)
|
||||
{
|
||||
pte.pte_low |= _PAGE_MODIFIED;
|
||||
if (pte.pte_low & _PAGE_WRITE) {
|
||||
pte.pte_low |= _PAGE_SILENT_WRITE;
|
||||
if (pte.pte_low & _PAGE_WRITE)
|
||||
pte.pte_high |= _PAGE_SILENT_WRITE;
|
||||
}
|
||||
return pte;
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkyoung(pte_t pte)
|
||||
{
|
||||
pte.pte_low |= _PAGE_ACCESSED;
|
||||
if (pte.pte_low & _PAGE_READ) {
|
||||
pte.pte_low |= _PAGE_SILENT_READ;
|
||||
if (pte.pte_low & _PAGE_READ)
|
||||
pte.pte_high |= _PAGE_SILENT_READ;
|
||||
}
|
||||
return pte;
|
||||
}
|
||||
#else
|
||||
@@ -332,13 +322,13 @@ static inline pte_t pte_mkdirty(pte_t pte)
|
||||
static inline pte_t pte_mkyoung(pte_t pte)
|
||||
{
|
||||
pte_val(pte) |= _PAGE_ACCESSED;
|
||||
if (cpu_has_rixi) {
|
||||
if (!(pte_val(pte) & _PAGE_NO_READ))
|
||||
pte_val(pte) |= _PAGE_SILENT_READ;
|
||||
} else {
|
||||
if (pte_val(pte) & _PAGE_READ)
|
||||
pte_val(pte) |= _PAGE_SILENT_READ;
|
||||
}
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
if (!(pte_val(pte) & _PAGE_NO_READ))
|
||||
pte_val(pte) |= _PAGE_SILENT_READ;
|
||||
else
|
||||
#endif
|
||||
if (pte_val(pte) & _PAGE_READ)
|
||||
pte_val(pte) |= _PAGE_SILENT_READ;
|
||||
return pte;
|
||||
}
|
||||
|
||||
@@ -391,10 +381,10 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
|
||||
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
|
||||
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||||
{
|
||||
pte.pte_low &= _PAGE_CHG_MASK;
|
||||
pte.pte_low &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK);
|
||||
pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
|
||||
pte.pte_low |= pgprot_val(newprot);
|
||||
pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
|
||||
pte.pte_low |= pgprot_val(newprot) & ~_PFNX_MASK;
|
||||
pte.pte_high |= pgprot_val(newprot) & ~_PFN_MASK;
|
||||
return pte;
|
||||
}
|
||||
#else
|
||||
@@ -407,12 +397,15 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||||
|
||||
extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
|
||||
pte_t pte);
|
||||
extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
|
||||
pte_t pte);
|
||||
|
||||
static inline void update_mmu_cache(struct vm_area_struct *vma,
|
||||
unsigned long address, pte_t *ptep)
|
||||
{
|
||||
pte_t pte = *ptep;
|
||||
__update_tlb(vma, address, pte);
|
||||
__update_cache(vma, address, pte);
|
||||
}
|
||||
|
||||
static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
|
||||
@@ -534,13 +527,13 @@ static inline pmd_t pmd_mkyoung(pmd_t pmd)
|
||||
{
|
||||
pmd_val(pmd) |= _PAGE_ACCESSED;
|
||||
|
||||
if (cpu_has_rixi) {
|
||||
if (!(pmd_val(pmd) & _PAGE_NO_READ))
|
||||
pmd_val(pmd) |= _PAGE_SILENT_READ;
|
||||
} else {
|
||||
if (pmd_val(pmd) & _PAGE_READ)
|
||||
pmd_val(pmd) |= _PAGE_SILENT_READ;
|
||||
}
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
if (!(pmd_val(pmd) & _PAGE_NO_READ))
|
||||
pmd_val(pmd) |= _PAGE_SILENT_READ;
|
||||
else
|
||||
#endif
|
||||
if (pmd_val(pmd) & _PAGE_READ)
|
||||
pmd_val(pmd) |= _PAGE_SILENT_READ;
|
||||
|
||||
return pmd;
|
||||
}
|
||||
|
||||
@@ -12,6 +12,8 @@
|
||||
#ifndef _ASM_R4KCACHE_H
|
||||
#define _ASM_R4KCACHE_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/cacheops.h>
|
||||
#include <asm/compiler.h>
|
||||
@@ -344,7 +346,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
|
||||
" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \
|
||||
" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \
|
||||
" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \
|
||||
" addiu $1, $0, 0x100 \n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x010($1)\n" \
|
||||
" cache %1, 0x020($1); cache %1, 0x030($1)\n" \
|
||||
" cache %1, 0x040($1); cache %1, 0x050($1)\n" \
|
||||
@@ -368,17 +370,17 @@ static inline void invalidate_tcache_page(unsigned long addr)
|
||||
" cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \
|
||||
" cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \
|
||||
" cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x020($1)\n" \
|
||||
" cache %1, 0x040($1); cache %1, 0x060($1)\n" \
|
||||
" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
|
||||
" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
|
||||
" addiu $1, $1, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x020($1)\n" \
|
||||
" cache %1, 0x040($1); cache %1, 0x060($1)\n" \
|
||||
" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
|
||||
" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
|
||||
" addiu $1, $1, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100\n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x020($1)\n" \
|
||||
" cache %1, 0x040($1); cache %1, 0x060($1)\n" \
|
||||
" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
|
||||
@@ -396,25 +398,25 @@ static inline void invalidate_tcache_page(unsigned long addr)
|
||||
" .set noat\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \
|
||||
" cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
|
||||
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
|
||||
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
|
||||
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
|
||||
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
|
||||
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
|
||||
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
|
||||
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
|
||||
" .set pop\n" \
|
||||
@@ -429,39 +431,38 @@ static inline void invalidate_tcache_page(unsigned long addr)
|
||||
" .set mips64r6\n" \
|
||||
" .set noat\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
|
||||
" addiu $1, %0, 0x100\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
|
||||
" cache %1, 0x000($1); cache %1, 0x080($1)\n" \
|
||||
" .set pop\n" \
|
||||
: \
|
||||
: "r" (base), \
|
||||
|
||||
@@ -263,7 +263,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
|
||||
if (R10000_LLSC_WAR) {
|
||||
__asm__ __volatile__(
|
||||
"1: ll %1, %2 # arch_read_unlock \n"
|
||||
" addiu %1, 1 \n"
|
||||
" addiu %1, -1 \n"
|
||||
" sc %1, %0 \n"
|
||||
" beqzl %1, 1b \n"
|
||||
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
|
||||
|
||||
@@ -600,6 +600,10 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
|
||||
c->options |= MIPS_CPU_MAAR;
|
||||
if (config5 & MIPS_CONF5_LLB)
|
||||
c->options |= MIPS_CPU_RW_LLB;
|
||||
#ifdef CONFIG_XPA
|
||||
if (config5 & MIPS_CONF5_MVH)
|
||||
c->options |= MIPS_CPU_XPA;
|
||||
#endif
|
||||
|
||||
return config5 & MIPS_CONF_M;
|
||||
}
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/asmmacro.h>
|
||||
#include <asm/compiler.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/stackframe.h>
|
||||
@@ -185,7 +186,7 @@ syscall_exit_work:
|
||||
* For C code use the inline version named instruction_hazard().
|
||||
*/
|
||||
LEAF(mips_ihb)
|
||||
.set mips32r2
|
||||
.set MIPS_ISA_LEVEL_RAW
|
||||
jr.hb ra
|
||||
nop
|
||||
END(mips_ihb)
|
||||
|
||||
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Reference in New Issue
Block a user