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Merge tag 'pci-v4.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas: "Resource management: - Add support for Enhanced Allocation devices (Sean O. Stalley) - Add Enhanced Allocation register entries (Sean O. Stalley) - Handle IORESOURCE_PCI_FIXED when sizing resources (David Daney) - Handle IORESOURCE_PCI_FIXED when assigning resources (David Daney) - Handle Enhanced Allocation capability for SR-IOV devices (David Daney) - Clear IORESOURCE_UNSET when reverting to firmware-assigned address (Bjorn Helgaas) - Make Enhanced Allocation bitmasks more obvious (Bjorn Helgaas) - Expand Enhanced Allocation BAR output (Bjorn Helgaas) - Add of_pci_check_probe_only to parse "linux,pci-probe-only" (Marc Zyngier) - Fix lookup of linux,pci-probe-only property (Marc Zyngier) - Add sparc mem64 resource parsing for root bus (Yinghai Lu) PCI device hotplug: - pciehp: Queue power work requests in dedicated function (Guenter Roeck) Driver binding: - Add builtin_pci_driver() to avoid registration boilerplate (Paul Gortmaker) Virtualization: - Set SR-IOV NumVFs to zero after enumeration (Alexander Duyck) - Remove redundant validation of SR-IOV offset/stride registers (Alexander Duyck) - Remove VFs in reverse order if virtfn_add() fails (Alexander Duyck) - Reorder pcibios_sriov_disable() (Alexander Duyck) - Wait 1 second between disabling VFs and clearing NumVFs (Alexander Duyck) - Fix sriov_enable() error path for pcibios_enable_sriov() failures (Alexander Duyck) - Enable SR-IOV ARI Capable Hierarchy before reading TotalVFs (Ben Shelton) - Don't try to restore VF BARs (Wei Yang) MSI: - Don't alloc pcibios-irq when MSI is enabled (Joerg Roedel) - Add msi_controller setup_irqs() method for special multivector setup (Lucas Stach) - Export all remapped MSIs to sysfs attributes (Romain Bezut) - Disable MSI on SiS 761 (Ondrej Zary) AER: - Clear error status registers during enumeration and restore (Taku Izumi) Generic host bridge driver: - Fix lookup of linux,pci-probe-only property (Marc Zyngier) - Allow multiple hosts with different map_bus() methods (David Daney) - Pass starting bus number to pci_scan_root_bus() (David Daney) - Fix address window calculation for non-zero starting bus (David Daney) Altera host bridge driver: - Add msi.h to ARM Kbuild (Ley Foon Tan) - Add Altera PCIe host controller driver (Ley Foon Tan) - Add Altera PCIe MSI driver (Ley Foon Tan) APM X-Gene host bridge driver: - Remove msi_controller assignment (Duc Dang) Broadcom iProc host bridge driver: - Fix header comment "Corporation" misspelling (Florian Fainelli) - Fix code comment to match code (Ray Jui) - Remove unused struct iproc_pcie.irqs[] (Ray Jui) - Call pci_fixup_irqs() for ARM64 as well as ARM (Ray Jui) - Fix PCIe reset logic (Ray Jui) - Improve link detection logic (Ray Jui) - Update PCIe device tree bindings (Ray Jui) - Add outbound mapping support (Ray Jui) Freescale i.MX6 host bridge driver: - Return real error code from imx6_add_pcie_port() (Fabio Estevam) - Add PCIE_PHY_RX_ASIC_OUT_VALID definition (Fabio Estevam) Freescale Layerscape host bridge driver: - Remove ls_pcie_establish_link() (Minghuan Lian) - Ignore PCIe controllers in Endpoint mode (Minghuan Lian) - Factor out SCFG related function (Minghuan Lian) - Update ls_add_pcie_port() (Minghuan Lian) - Remove unused fields from struct ls_pcie (Minghuan Lian) - Add support for LS1043a and LS2080a (Minghuan Lian) - Add ls_pcie_msi_host_init() (Minghuan Lian) HiSilicon host bridge driver: - Add HiSilicon SoC Hip05 PCIe driver (Zhou Wang) Marvell MVEBU host bridge driver: - Return zero for reserved or unimplemented config space (Russell King) - Use exact config access size; don't read/modify/write (Russell King) - Use of_get_available_child_count() (Russell King) - Use for_each_available_child_of_node() to walk child nodes (Russell King) - Report full node name when reporting a DT error (Russell King) - Use port->name rather than "PCIe%d.%d" (Russell King) - Move port parsing and resource claiming to separate function (Russell King) - Fix memory leaks and refcount leaks (Russell King) - Split port parsing and resource claiming from port setup (Russell King) - Use gpio_set_value_cansleep() (Russell King) - Use devm_kcalloc() to allocate an array (Russell King) - Use gpio_desc to carry around gpio (Russell King) - Improve clock/reset handling (Russell King) - Add PCI Express root complex capability block (Russell King) - Remove code restricting accesses to slot 0 (Russell King) NVIDIA Tegra host bridge driver: - Wrap static pgprot_t initializer with __pgprot() (Ard Biesheuvel) Renesas R-Car host bridge driver: - Build pci-rcar-gen2.c only on ARM (Geert Uytterhoeven) - Build pcie-rcar.c only on ARM (Geert Uytterhoeven) - Make PCI aware of the I/O resources (Phil Edworthy) - Remove dependency on ARM-specific struct hw_pci (Phil Edworthy) - Set root bus nr to that provided in DT (Phil Edworthy) - Fix I/O offset for multiple host bridges (Phil Edworthy) ST Microelectronics SPEAr13xx host bridge driver: - Fix dw_pcie_cfg_read/write() usage (Gabriele Paoloni) Synopsys DesignWare host bridge driver: - Make "clocks" and "clock-names" optional DT properties (Bhupesh Sharma) - Use exact access size in dw_pcie_cfg_read() (Gabriele Paoloni) - Simplify dw_pcie_cfg_read/write() interfaces (Gabriele Paoloni) - Require config accesses to be naturally aligned (Gabriele Paoloni) - Make "num-lanes" an optional DT property (Gabriele Paoloni) - Move calculation of bus addresses to DRA7xx (Gabriele Paoloni) - Replace ARM pci_sys_data->align_resource with global function pointer (Gabriele Paoloni) - Factor out MSI msg setup (Lucas Stach) - Implement multivector MSI IRQ setup (Lucas Stach) - Make get_msi_addr() return phys_addr_t, not u32 (Lucas Stach) - Set up high part of MSI target address (Lucas Stach) - Fix PORT_LOGIC_LINK_WIDTH_MASK (Zhou Wang) - Revert "PCI: designware: Program ATU with untranslated address" (Zhou Wang) - Use of_pci_get_host_bridge_resources() to parse DT (Zhou Wang) - Make driver arch-agnostic (Zhou Wang) Miscellaneous: - Make x86 pci_subsys_init() static (Alexander Kuleshov) - Turn off Request Attributes to avoid Chelsio T5 Completion erratum (Hariprasad Shenai)" * tag 'pci-v4.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (94 commits) PCI: altera: Add Altera PCIe MSI driver PCI: hisi: Add HiSilicon SoC Hip05 PCIe driver PCI: layerscape: Add ls_pcie_msi_host_init() PCI: layerscape: Add support for LS1043a and LS2080a PCI: layerscape: Remove unused fields from struct ls_pcie PCI: layerscape: Update ls_add_pcie_port() PCI: layerscape: Factor out SCFG related function PCI: layerscape: Ignore PCIe controllers in Endpoint mode PCI: layerscape: Remove ls_pcie_establish_link() PCI: designware: Make "clocks" and "clock-names" optional DT properties PCI: designware: Make driver arch-agnostic ARM/PCI: Replace pci_sys_data->align_resource with global function pointer PCI: designware: Use of_pci_get_host_bridge_resources() to parse DT Revert "PCI: designware: Program ATU with untranslated address" PCI: designware: Move calculation of bus addresses to DRA7xx PCI: designware: Make "num-lanes" an optional DT property PCI: designware: Require config accesses to be naturally aligned PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces PCI: designware: Use exact access size in dw_pcie_cfg_read() PCI: spear: Fix dw_pcie_cfg_read/write() usage ...
This commit is contained in:
Linus Torvalds
@@ -166,6 +166,23 @@ Example:
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reboot-offset = <0x4>;
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};
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-----------------------------------------------------------------------
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Hisilicon HiP05 PCIe-SAS system controller
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Required properties:
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- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
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- reg : Register address and size
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The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
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HiP05 Soc to implement some basic configurations.
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Example:
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/* for HiP05 PCIe-SAS system */
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pcie_sas: system_controller@0xb0000000 {
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compatible = "hisilicon,pcie-sas-subctrl", "syscon";
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reg = <0xb0000000 0x10000>;
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};
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-----------------------------------------------------------------------
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Hisilicon CPU controller
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@@ -0,0 +1,28 @@
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* Altera PCIe MSI controller
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Required properties:
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- compatible: should contain "altr,msi-1.0"
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- reg: specifies the physical base address of the controller and
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the length of the memory mapped region.
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- reg-names: must include the following entries:
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"csr": CSR registers
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"vector_slave": vectors slave port region
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- interrupt-parent: interrupt source phandle.
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- interrupts: specifies the interrupt source of the parent interrupt
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controller. The format of the interrupt specifier depends on the
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parent interrupt controller.
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- num-vectors: number of vectors, range 1 to 32.
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- msi-controller: indicates that this is MSI controller node
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Example
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msi0: msi@0xFF200000 {
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compatible = "altr,msi-1.0";
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reg = <0xFF200000 0x00000010
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0xFF200010 0x00000080>;
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reg-names = "csr", "vector_slave";
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interrupt-parent = <&hps_0_arm_gic_0>;
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interrupts = <0 42 4>;
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msi-controller;
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num-vectors = <32>;
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};
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@@ -0,0 +1,49 @@
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* Altera PCIe controller
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Required properties:
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- compatible : should contain "altr,pcie-root-port-1.0"
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- reg: a list of physical base address and length for TXS and CRA.
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- reg-names: must include the following entries:
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"Txs": TX slave port region
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"Cra": Control register access region
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- interrupt-parent: interrupt source phandle.
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- interrupts: specifies the interrupt source of the parent interrupt controller.
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The format of the interrupt specifier depends on the parent interrupt
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controller.
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- device_type: must be "pci"
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- #interrupt-cells: set to <1>
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- ranges: describes the translation of addresses for root ports and standard
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PCI regions.
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- interrupt-map-mask and interrupt-map: standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers.
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Optional properties:
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- msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe
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controller.
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- bus-range: PCI bus numbers covered
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Example
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pcie_0: pcie@0xc00000000 {
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compatible = "altr,pcie-root-port-1.0";
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reg = <0xc0000000 0x20000000>,
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<0xff220000 0x00004000>;
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reg-names = "Txs", "Cra";
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interrupt-parent = <&hps_0_arm_gic_0>;
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interrupts = <0 40 4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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bus-range = <0x0 0xFF>;
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device_type = "pci";
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msi-parent = <&msi_to_gic_gen_0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_0 1>,
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<0 0 0 2 &pcie_0 2>,
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<0 0 0 3 &pcie_0 3>,
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<0 0 0 4 &pcie_0 4>;
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ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
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0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
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};
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@@ -17,6 +17,21 @@ Optional properties:
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- phys: phandle of the PCIe PHY device
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- phy-names: must be "pcie-phy"
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- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done
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by the ASIC after power on reset. In this case, SW needs to configure it
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If the brcm,pcie-ob property is present, the following properties become
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effective:
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Required:
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- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal
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address used by the iProc PCIe core (not the PCIe address)
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- brcm,pcie-ob-window-size: The outbound address mapping window size (in MB)
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Optional:
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- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
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increase the outbound window size
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Example:
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pcie0: pcie@18012000 {
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compatible = "brcm,iproc-pcie";
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@@ -38,6 +53,11 @@ Example:
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phys = <&phy 0 5>;
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phy-names = "pcie-phy";
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brcm,pcie-ob;
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brcm,pcie-ob-oarr-size;
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brcm,pcie-ob-axi-offset = <0x00000000>;
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brcm,pcie-ob-window-size = <256>;
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};
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pcie1: pcie@18013000 {
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@@ -15,14 +15,16 @@ Required properties:
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to define the mapping of the PCIe interface to interrupt
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numbers.
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- num-lanes: number of lanes to use
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Optional properties:
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- num-lanes: number of lanes to use (this property should be specified unless
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the link is brought already up in BIOS)
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- reset-gpio: gpio pin number of power good signal
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- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
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specify this property, to keep backwards compatibility a range of 0x00-0xff
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is assumed if not present)
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "pcie"
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- "pcie_bus"
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Optional properties:
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- reset-gpio: gpio pin number of power good signal
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- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
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specify this property, to keep backwards compatibility a range of 0x00-0xff
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is assumed if not present)
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@@ -0,0 +1,44 @@
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HiSilicon PCIe host bridge DT description
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HiSilicon PCIe host controller is based on Designware PCI core.
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It shares common functions with PCIe Designware core driver and inherits
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pci.txt.
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Additional properties are described here:
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Required properties:
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- compatible: Should contain "hisilicon,hip05-pcie".
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- reg: Should contain rc_dbi, config registers location and length.
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- reg-names: Must include the following entries:
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"rc_dbi": controller configuration registers;
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"config": PCIe configuration space registers.
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- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
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- port-id: Should be 0, 1, 2 or 3.
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Optional properties:
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- status: Either "ok" or "disabled".
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- dma-coherent: Present if DMA operations are coherent.
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Example:
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pcie@0xb0080000 {
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compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
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reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
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reg-names = "rc_dbi", "config";
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bus-range = <0 15>;
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msi-parent = <&its_pcie>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
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num-lanes = <8>;
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port-id = <1>;
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#interrupts-cells = <1>;
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interrupts-map-mask = <0xf800 0 0 7>;
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interrupts-map = <0x0 0 0 1 &mbigen_pcie 1 10
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0x0 0 0 2 &mbigen_pcie 2 11
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0x0 0 0 3 &mbigen_pcie 3 12
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0x0 0 0 4 &mbigen_pcie 4 13>;
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status = "ok";
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};
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@@ -34,8 +34,9 @@ Properties of the host controller node:
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- #size-cells : Must be 2.
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- reg : The Configuration Space base address and size, as accessed
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from the parent bus.
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from the parent bus. The base address corresponds to
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the first bus in the "bus-range" property. If no
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"bus-range" is specified, this will be bus 0 (the default).
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Properties of the /chosen node:
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@@ -1,10 +1,20 @@
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Freescale Layerscape PCIe controller
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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This controller derives its clocks from the Reset Configuration Word (RCW)
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which is used to describe the PLL settings at the time of chip-reset.
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Also as per the available Reference Manuals, there is no specific 'version'
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register available in the Freescale PCIe controller register set,
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which can allow determining the underlying DesignWare PCIe controller version
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information.
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Required properties:
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- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
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- compatible: should contain the platform identifier such as:
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"fsl,ls1021a-pcie", "snps,dw-pcie"
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"fsl,ls2080a-pcie", "snps,dw-pcie"
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- reg: base addresses and lengths of the PCIe controller
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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+23
@@ -8063,6 +8063,14 @@ F: include/linux/pci*
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F: arch/x86/pci/
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F: arch/x86/kernel/quirks.c
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PCI DRIVER FOR ALTERA PCIE IP
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M: Ley Foon Tan <lftan@altera.com>
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L: rfi@lists.rocketboards.org (moderated for non-subscribers)
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L: linux-pci@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/pci/altera-pcie.txt
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F: drivers/pci/host/pcie-altera.c
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PCI DRIVER FOR ARM VERSATILE PLATFORM
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M: Rob Herring <robh@kernel.org>
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L: linux-pci@vger.kernel.org
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@@ -8164,6 +8172,14 @@ L: linux-pci@vger.kernel.org
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S: Maintained
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F: drivers/pci/host/*spear*
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PCI MSI DRIVER FOR ALTERA MSI IP
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M: Ley Foon Tan <lftan@altera.com>
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L: rfi@lists.rocketboards.org (moderated for non-subscribers)
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L: linux-pci@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
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F: drivers/pci/host/pcie-altera-msi.c
|
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PCI MSI DRIVER FOR APPLIEDMICRO XGENE
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M: Duc Dang <dhdang@apm.com>
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L: linux-pci@vger.kernel.org
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@@ -8172,6 +8188,13 @@ S: Maintained
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F: Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
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F: drivers/pci/host/pci-xgene-msi.c
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PCIE DRIVER FOR HISILICON
|
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M: Zhou Wang <wangzhou1@hisilicon.com>
|
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L: linux-pci@vger.kernel.org
|
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S: Maintained
|
||||
F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
|
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F: drivers/pci/host/pcie-hisi.c
|
||||
|
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PCMCIA SUBSYSTEM
|
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P: Linux PCMCIA Team
|
||||
L: linux-pcmcia@lists.infradead.org
|
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|
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@@ -14,6 +14,7 @@ generic-y += local.h
|
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generic-y += local64.h
|
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generic-y += mm-arch-hooks.h
|
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generic-y += msgbuf.h
|
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generic-y += msi.h
|
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generic-y += param.h
|
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generic-y += parport.h
|
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generic-y += poll.h
|
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|
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@@ -52,12 +52,6 @@ struct pci_sys_data {
|
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u8 (*swizzle)(struct pci_dev *, u8 *);
|
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/* IRQ mapping */
|
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int (*map_irq)(const struct pci_dev *, u8, u8);
|
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/* Resource alignement requirements */
|
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resource_size_t (*align_resource)(struct pci_dev *dev,
|
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const struct resource *res,
|
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resource_size_t start,
|
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resource_size_t size,
|
||||
resource_size_t align);
|
||||
void *private_data; /* platform controller private data */
|
||||
};
|
||||
|
||||
|
||||
@@ -17,6 +17,11 @@
|
||||
#include <asm/mach/pci.h>
|
||||
|
||||
static int debug_pci;
|
||||
static resource_size_t (*align_resource)(struct pci_dev *dev,
|
||||
const struct resource *res,
|
||||
resource_size_t start,
|
||||
resource_size_t size,
|
||||
resource_size_t align) = NULL;
|
||||
|
||||
/*
|
||||
* We can't use pci_get_device() here since we are
|
||||
@@ -456,7 +461,7 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
|
||||
sys->busnr = busnr;
|
||||
sys->swizzle = hw->swizzle;
|
||||
sys->map_irq = hw->map_irq;
|
||||
sys->align_resource = hw->align_resource;
|
||||
align_resource = hw->align_resource;
|
||||
INIT_LIST_HEAD(&sys->resources);
|
||||
|
||||
if (hw->private_data)
|
||||
@@ -572,7 +577,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
|
||||
resource_size_t size, resource_size_t align)
|
||||
{
|
||||
struct pci_dev *dev = data;
|
||||
struct pci_sys_data *sys = dev->sysdata;
|
||||
resource_size_t start = res->start;
|
||||
|
||||
if (res->flags & IORESOURCE_IO && start & 0x300)
|
||||
@@ -580,8 +584,8 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
|
||||
|
||||
start = (start + align - 1) & ~(align - 1);
|
||||
|
||||
if (sys->align_resource)
|
||||
return sys->align_resource(dev, res, start, size, align);
|
||||
if (align_resource)
|
||||
return align_resource(dev, res, start, size, align);
|
||||
|
||||
return start;
|
||||
}
|
||||
|
||||
@@ -14,7 +14,6 @@
|
||||
|
||||
chosen {
|
||||
stdout-path = &serial0;
|
||||
linux,pci-probe-only;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -40,6 +40,7 @@
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/kexec.h>
|
||||
|
||||
#include <asm/mmu.h>
|
||||
@@ -495,18 +496,7 @@ static void __init find_and_init_phbs(void)
|
||||
* PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
|
||||
* in chosen.
|
||||
*/
|
||||
if (of_chosen) {
|
||||
const int *prop;
|
||||
|
||||
prop = of_get_property(of_chosen,
|
||||
"linux,pci-probe-only", NULL);
|
||||
if (prop) {
|
||||
if (*prop)
|
||||
pci_add_flags(PCI_PROBE_ONLY);
|
||||
else
|
||||
pci_clear_flags(PCI_PROBE_ONLY);
|
||||
}
|
||||
}
|
||||
of_pci_check_probe_only();
|
||||
}
|
||||
|
||||
static void __init pSeries_setup_arch(void)
|
||||
|
||||
@@ -185,8 +185,10 @@ static unsigned long pci_parse_of_flags(u32 addr0)
|
||||
|
||||
if (addr0 & 0x02000000) {
|
||||
flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
|
||||
flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
|
||||
flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
|
||||
if (addr0 & 0x01000000)
|
||||
flags |= IORESOURCE_MEM_64
|
||||
| PCI_BASE_ADDRESS_MEM_TYPE_64;
|
||||
if (addr0 & 0x40000000)
|
||||
flags |= IORESOURCE_PREFETCH
|
||||
| PCI_BASE_ADDRESS_MEM_PREFETCH;
|
||||
@@ -655,6 +657,9 @@ struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
|
||||
pbm->io_space.start);
|
||||
pci_add_resource_offset(&resources, &pbm->mem_space,
|
||||
pbm->mem_space.start);
|
||||
if (pbm->mem64_space.flags)
|
||||
pci_add_resource_offset(&resources, &pbm->mem64_space,
|
||||
pbm->mem_space.start);
|
||||
pbm->busn.start = pbm->pci_first_busno;
|
||||
pbm->busn.end = pbm->pci_last_busno;
|
||||
pbm->busn.flags = IORESOURCE_BUS;
|
||||
|
||||
@@ -406,6 +406,7 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
|
||||
}
|
||||
|
||||
num_pbm_ranges = i / sizeof(*pbm_ranges);
|
||||
memset(&pbm->mem64_space, 0, sizeof(struct resource));
|
||||
|
||||
for (i = 0; i < num_pbm_ranges; i++) {
|
||||
const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
|
||||
@@ -451,7 +452,12 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
|
||||
break;
|
||||
|
||||
case 3:
|
||||
/* XXX 64-bit MEM handling XXX */
|
||||
/* 64-bit MEM handling */
|
||||
pbm->mem64_space.start = a;
|
||||
pbm->mem64_space.end = a + size - 1UL;
|
||||
pbm->mem64_space.flags = IORESOURCE_MEM;
|
||||
saw_mem = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
@@ -465,15 +471,22 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
|
||||
prom_halt();
|
||||
}
|
||||
|
||||
printk("%s: PCI IO[%llx] MEM[%llx]\n",
|
||||
printk("%s: PCI IO[%llx] MEM[%llx]",
|
||||
pbm->name,
|
||||
pbm->io_space.start,
|
||||
pbm->mem_space.start);
|
||||
if (pbm->mem64_space.flags)
|
||||
printk(" MEM64[%llx]",
|
||||
pbm->mem64_space.start);
|
||||
printk("\n");
|
||||
|
||||
pbm->io_space.name = pbm->mem_space.name = pbm->name;
|
||||
pbm->mem64_space.name = pbm->name;
|
||||
|
||||
request_resource(&ioport_resource, &pbm->io_space);
|
||||
request_resource(&iomem_resource, &pbm->mem_space);
|
||||
if (pbm->mem64_space.flags)
|
||||
request_resource(&iomem_resource, &pbm->mem64_space);
|
||||
|
||||
pci_register_legacy_regions(&pbm->io_space,
|
||||
&pbm->mem_space);
|
||||
|
||||
@@ -97,6 +97,7 @@ struct pci_pbm_info {
|
||||
/* PBM I/O and Memory space resources. */
|
||||
struct resource io_space;
|
||||
struct resource mem_space;
|
||||
struct resource mem64_space;
|
||||
struct resource busn;
|
||||
|
||||
/* Base of PCI Config space, can be per-PBM or shared. */
|
||||
|
||||
@@ -675,6 +675,14 @@ int pcibios_add_device(struct pci_dev *dev)
|
||||
|
||||
int pcibios_alloc_irq(struct pci_dev *dev)
|
||||
{
|
||||
/*
|
||||
* If the PCI device was already claimed by core code and has
|
||||
* MSI enabled, probing of the pcibios IRQ will overwrite
|
||||
* dev->irq. So bail out if MSI is already enabled.
|
||||
*/
|
||||
if (pci_dev_msi_enabled(dev))
|
||||
return -EBUSY;
|
||||
|
||||
return pcibios_enable_irq(dev);
|
||||
}
|
||||
|
||||
|
||||
@@ -54,7 +54,7 @@ void pcibios_scan_specific_bus(int busn)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pcibios_scan_specific_bus);
|
||||
|
||||
int __init pci_subsys_init(void)
|
||||
static int __init pci_subsys_init(void)
|
||||
{
|
||||
/*
|
||||
* The init function returns an non zero value when
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/slab.h>
|
||||
#include <asm-generic/pci-bridge.h>
|
||||
|
||||
static inline int __of_pci_pci_compare(struct device_node *node,
|
||||
unsigned int data)
|
||||
@@ -117,6 +118,31 @@ int of_get_pci_domain_nr(struct device_node *node)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_get_pci_domain_nr);
|
||||
|
||||
/**
|
||||
* of_pci_check_probe_only - Setup probe only mode if linux,pci-probe-only
|
||||
* is present and valid
|
||||
*/
|
||||
void of_pci_check_probe_only(void)
|
||||
{
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = of_property_read_u32(of_chosen, "linux,pci-probe-only", &val);
|
||||
if (ret) {
|
||||
if (ret == -ENODATA || ret == -EOVERFLOW)
|
||||
pr_warn("linux,pci-probe-only without valid value, ignoring\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (val)
|
||||
pci_add_flags(PCI_PROBE_ONLY);
|
||||
else
|
||||
pci_clear_flags(PCI_PROBE_ONLY);
|
||||
|
||||
pr_info("PCI: PROBE_ONLY %sabled\n", val ? "en" : "dis");
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_pci_check_probe_only);
|
||||
|
||||
/**
|
||||
* of_pci_dma_configure - Setup DMA configuration
|
||||
* @dev: ptr to pci_dev struct of the PCI device
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user