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Merge branch 'master' into for-davem
Conflicts: drivers/net/wireless/ath/ath9k/phy.c drivers/net/wireless/iwlwifi/iwl-6000.c drivers/net/wireless/iwlwifi/iwl-debugfs.c
This commit is contained in:
John W. Linville
@@ -210,90 +210,7 @@ config USB_NET_RNDIS_WLAN
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If you choose to build a module, it'll be called rndis_wlan.
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config RTL8180
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tristate "Realtek 8180/8185 PCI support"
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depends on MAC80211 && PCI && EXPERIMENTAL
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select EEPROM_93CX6
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---help---
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This is a driver for RTL8180 and RTL8185 based cards.
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These are PCI based chips found in cards such as:
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(RTL8185 802.11g)
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A-Link WL54PC
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(RTL8180 802.11b)
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Belkin F5D6020 v3
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Belkin F5D6020 v3
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Dlink DWL-610
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Dlink DWL-510
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Netgear MA521
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Level-One WPC-0101
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Acer Aspire 1357 LMi
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VCTnet PC-11B1
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Ovislink AirLive WL-1120PCM
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Mentor WL-PCI
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Linksys WPC11 v4
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TrendNET TEW-288PI
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D-Link DWL-520 Rev D
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Repotec RP-WP7126
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TP-Link TL-WN250/251
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Zonet ZEW1000
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Longshine LCS-8031-R
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HomeLine HLW-PCC200
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GigaFast WF721-AEX
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Planet WL-3553
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Encore ENLWI-PCI1-NT
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TrendNET TEW-266PC
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Gigabyte GN-WLMR101
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Siemens-fujitsu Amilo D1840W
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Edimax EW-7126
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PheeNet WL-11PCIR
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Tonze PC-2100T
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Planet WL-8303
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Dlink DWL-650 v M1
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Edimax EW-7106
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Q-Tec 770WC
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Topcom Skyr@cer 4011b
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Roper FreeLan 802.11b (edition 2004)
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Wistron Neweb Corp CB-200B
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Pentagram HorNET
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QTec 775WC
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TwinMOS Booming B Series
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Micronet SP906BB
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Sweex LC700010
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Surecom EP-9428
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Safecom SWLCR-1100
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Thanks to Realtek for their support!
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config RTL8187
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tristate "Realtek 8187 and 8187B USB support"
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depends on MAC80211 && USB
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select EEPROM_93CX6
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---help---
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This is a driver for RTL8187 and RTL8187B based cards.
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These are USB based chips found in devices such as:
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Netgear WG111v2
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Level 1 WNC-0301USB
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Micronet SP907GK V5
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Encore ENUWI-G2
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Trendnet TEW-424UB
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ASUS P5B Deluxe/P5K Premium motherboards
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Toshiba Satellite Pro series of laptops
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Asus Wireless Link
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Linksys WUSB54GC-EU v2
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(v1 = rt73usb; v3 is rt2070-based,
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use staging/rt3070 or try rt2800usb)
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Thanks to Realtek for their support!
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# If possible, automatically enable LEDs for RTL8187.
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config RTL8187_LEDS
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bool
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depends on RTL8187 && MAC80211_LEDS && (LEDS_CLASS = y || LEDS_CLASS = RTL8187)
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default y
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source "drivers/net/wireless/rtl818x/Kconfig"
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config ADM8211
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tristate "ADMtek ADM8211 support"
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@@ -71,9 +71,21 @@ struct ath_regulatory {
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struct reg_dmn_pair_mapping *regpair;
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};
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/**
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* struct ath_ops - Register read/write operations
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*
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* @read: Register read
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* @write: Register write
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* @enable_write_buffer: Enable multiple register writes
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* @disable_write_buffer: Disable multiple register writes
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* @write_flush: Flush buffered register writes
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*/
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struct ath_ops {
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unsigned int (*read)(void *, u32 reg_offset);
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void (*write)(void *, u32 val, u32 reg_offset);
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void (*write)(void *, u32 val, u32 reg_offset);
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void (*enable_write_buffer)(void *);
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void (*disable_write_buffer)(void *);
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void (*write_flush) (void *);
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};
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struct ath_common;
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@@ -242,6 +242,8 @@ static int ath5k_set_key(struct ieee80211_hw *hw,
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struct ieee80211_key_conf *key);
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static int ath5k_get_stats(struct ieee80211_hw *hw,
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struct ieee80211_low_level_stats *stats);
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static int ath5k_get_survey(struct ieee80211_hw *hw,
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int idx, struct survey_info *survey);
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static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
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static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
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static void ath5k_reset_tsf(struct ieee80211_hw *hw);
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@@ -267,6 +269,7 @@ static const struct ieee80211_ops ath5k_hw_ops = {
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.configure_filter = ath5k_configure_filter,
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.set_key = ath5k_set_key,
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.get_stats = ath5k_get_stats,
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.get_survey = ath5k_get_survey,
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.conf_tx = NULL,
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.get_tsf = ath5k_get_tsf,
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.set_tsf = ath5k_set_tsf,
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@@ -3292,6 +3295,22 @@ ath5k_get_stats(struct ieee80211_hw *hw,
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return 0;
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}
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static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
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struct survey_info *survey)
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{
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struct ath5k_softc *sc = hw->priv;
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struct ieee80211_conf *conf = &hw->conf;
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if (idx != 0)
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return -ENOENT;
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survey->channel = conf->channel;
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survey->filled = SURVEY_INFO_NOISE_DBM;
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survey->noise = sc->ah->ah_noise_floor;
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return 0;
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}
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static u64
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ath5k_get_tsf(struct ieee80211_hw *hw)
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{
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@@ -496,6 +496,8 @@ void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
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* Beacon control *
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\****************/
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#define ATH5K_MAX_TSF_READ 10
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/**
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* ath5k_hw_get_tsf64 - Get the full 64bit TSF
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*
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@@ -505,10 +507,35 @@ void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
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*/
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u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
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{
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u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
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u32 tsf_lower, tsf_upper1, tsf_upper2;
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int i;
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/*
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* While reading TSF upper and then lower part, the clock is still
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* counting (or jumping in case of IBSS merge) so we might get
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* inconsistent values. To avoid this, we read the upper part again
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* and check it has not been changed. We make the hypothesis that a
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* maximum of 3 changes can happens in a row (we use 10 as a safe
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* value).
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*
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* Impact on performance is pretty small, since in most cases, only
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* 3 register reads are needed.
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*/
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tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
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for (i = 0; i < ATH5K_MAX_TSF_READ; i++) {
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tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
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tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
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if (tsf_upper2 == tsf_upper1)
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break;
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tsf_upper1 = tsf_upper2;
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}
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WARN_ON( i == ATH5K_MAX_TSF_READ );
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ATH5K_TRACE(ah->ah_sc);
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return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
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return (((u64)tsf_upper1 << 32) | tsf_lower);
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}
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/**
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@@ -13,16 +13,26 @@ ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
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obj-$(CONFIG_ATH9K) += ath9k.o
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ath9k_hw-y:= hw.o \
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ath9k_hw-y:= \
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ar9002_hw.o \
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ar9003_hw.o \
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hw.o \
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ar9003_phy.o \
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ar9002_phy.o \
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ar5008_phy.o \
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ar9002_calib.o \
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ar9003_calib.o \
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calib.o \
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eeprom.o \
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eeprom_def.o \
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eeprom_4k.o \
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eeprom_9287.o \
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calib.o \
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ani.o \
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phy.o \
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btcoex.o \
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mac.o \
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ar9002_mac.o \
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ar9003_mac.o \
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ar9003_eeprom.o
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obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
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@@ -15,6 +15,7 @@
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*/
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#include "hw.h"
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#include "hw-ops.h"
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static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
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struct ath9k_channel *chan)
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@@ -37,190 +38,6 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
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return 0;
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}
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static bool ath9k_hw_ani_control(struct ath_hw *ah,
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enum ath9k_ani_cmd cmd, int param)
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{
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struct ar5416AniState *aniState = ah->curani;
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struct ath_common *common = ath9k_hw_common(ah);
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switch (cmd & ah->ani_function) {
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case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
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u32 level = param;
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if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
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ath_print(common, ATH_DBG_ANI,
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"level out of range (%u > %u)\n",
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level,
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(unsigned)ARRAY_SIZE(ah->totalSizeDesired));
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return false;
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}
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REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
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AR_PHY_DESIRED_SZ_TOT_DES,
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ah->totalSizeDesired[level]);
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REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
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AR_PHY_AGC_CTL1_COARSE_LOW,
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ah->coarse_low[level]);
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REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
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AR_PHY_AGC_CTL1_COARSE_HIGH,
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ah->coarse_high[level]);
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REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
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AR_PHY_FIND_SIG_FIRPWR,
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ah->firpwr[level]);
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if (level > aniState->noiseImmunityLevel)
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ah->stats.ast_ani_niup++;
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else if (level < aniState->noiseImmunityLevel)
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ah->stats.ast_ani_nidown++;
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aniState->noiseImmunityLevel = level;
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break;
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}
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case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
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const int m1ThreshLow[] = { 127, 50 };
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const int m2ThreshLow[] = { 127, 40 };
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const int m1Thresh[] = { 127, 0x4d };
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const int m2Thresh[] = { 127, 0x40 };
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const int m2CountThr[] = { 31, 16 };
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const int m2CountThrLow[] = { 63, 48 };
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u32 on = param ? 1 : 0;
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
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m1ThreshLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
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m2ThreshLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR,
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AR_PHY_SFCORR_M1_THRESH,
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m1Thresh[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR,
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AR_PHY_SFCORR_M2_THRESH,
|
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m2Thresh[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR,
|
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AR_PHY_SFCORR_M2COUNT_THR,
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m2CountThr[on]);
|
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
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m2CountThrLow[on]);
|
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|
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
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AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
|
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m1ThreshLow[on]);
|
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
|
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AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
|
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m2ThreshLow[on]);
|
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
|
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AR_PHY_SFCORR_EXT_M1_THRESH,
|
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m1Thresh[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
|
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AR_PHY_SFCORR_EXT_M2_THRESH,
|
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m2Thresh[on]);
|
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|
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if (on)
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REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
|
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else
|
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REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
|
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AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
|
||||
|
||||
if (!on != aniState->ofdmWeakSigDetectOff) {
|
||||
if (on)
|
||||
ah->stats.ast_ani_ofdmon++;
|
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else
|
||||
ah->stats.ast_ani_ofdmoff++;
|
||||
aniState->ofdmWeakSigDetectOff = !on;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
|
||||
const int weakSigThrCck[] = { 8, 6 };
|
||||
u32 high = param ? 1 : 0;
|
||||
|
||||
REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
|
||||
AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
|
||||
weakSigThrCck[high]);
|
||||
if (high != aniState->cckWeakSigThreshold) {
|
||||
if (high)
|
||||
ah->stats.ast_ani_cckhigh++;
|
||||
else
|
||||
ah->stats.ast_ani_ccklow++;
|
||||
aniState->cckWeakSigThreshold = high;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case ATH9K_ANI_FIRSTEP_LEVEL:{
|
||||
const int firstep[] = { 0, 4, 8 };
|
||||
u32 level = param;
|
||||
|
||||
if (level >= ARRAY_SIZE(firstep)) {
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"level out of range (%u > %u)\n",
|
||||
level,
|
||||
(unsigned) ARRAY_SIZE(firstep));
|
||||
return false;
|
||||
}
|
||||
REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
|
||||
AR_PHY_FIND_SIG_FIRSTEP,
|
||||
firstep[level]);
|
||||
if (level > aniState->firstepLevel)
|
||||
ah->stats.ast_ani_stepup++;
|
||||
else if (level < aniState->firstepLevel)
|
||||
ah->stats.ast_ani_stepdown++;
|
||||
aniState->firstepLevel = level;
|
||||
break;
|
||||
}
|
||||
case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
|
||||
const int cycpwrThr1[] =
|
||||
{ 2, 4, 6, 8, 10, 12, 14, 16 };
|
||||
u32 level = param;
|
||||
|
||||
if (level >= ARRAY_SIZE(cycpwrThr1)) {
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"level out of range (%u > %u)\n",
|
||||
level,
|
||||
(unsigned) ARRAY_SIZE(cycpwrThr1));
|
||||
return false;
|
||||
}
|
||||
REG_RMW_FIELD(ah, AR_PHY_TIMING5,
|
||||
AR_PHY_TIMING5_CYCPWR_THR1,
|
||||
cycpwrThr1[level]);
|
||||
if (level > aniState->spurImmunityLevel)
|
||||
ah->stats.ast_ani_spurup++;
|
||||
else if (level < aniState->spurImmunityLevel)
|
||||
ah->stats.ast_ani_spurdown++;
|
||||
aniState->spurImmunityLevel = level;
|
||||
break;
|
||||
}
|
||||
case ATH9K_ANI_PRESENT:
|
||||
break;
|
||||
default:
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"invalid cmd %u\n", cmd);
|
||||
return false;
|
||||
}
|
||||
|
||||
ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"noiseImmunityLevel=%d, spurImmunityLevel=%d, "
|
||||
"ofdmWeakSigDetectOff=%d\n",
|
||||
aniState->noiseImmunityLevel,
|
||||
aniState->spurImmunityLevel,
|
||||
!aniState->ofdmWeakSigDetectOff);
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"cckWeakSigThreshold=%d, "
|
||||
"firstepLevel=%d, listenTime=%d\n",
|
||||
aniState->cckWeakSigThreshold,
|
||||
aniState->firstepLevel,
|
||||
aniState->listenTime);
|
||||
ath_print(common, ATH_DBG_ANI,
|
||||
"cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
|
||||
aniState->cycleCount,
|
||||
aniState->ofdmPhyErrCount,
|
||||
aniState->cckPhyErrCount);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void ath9k_hw_update_mibstats(struct ath_hw *ah,
|
||||
struct ath9k_mib_stats *stats)
|
||||
{
|
||||
@@ -262,11 +79,17 @@ static void ath9k_ani_restart(struct ath_hw *ah)
|
||||
"Writing ofdmbase=%u cckbase=%u\n",
|
||||
aniState->ofdmPhyErrBase,
|
||||
aniState->cckPhyErrBase);
|
||||
|
||||
ENABLE_REGWRITE_BUFFER(ah);
|
||||
|
||||
REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
|
||||
REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
|
||||
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
|
||||
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
|
||||
|
||||
REGWRITE_BUFFER_FLUSH(ah);
|
||||
DISABLE_REGWRITE_BUFFER(ah);
|
||||
|
||||
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
|
||||
|
||||
aniState->ofdmPhyErrCount = 0;
|
||||
@@ -540,8 +363,14 @@ void ath9k_ani_reset(struct ath_hw *ah)
|
||||
ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
|
||||
~ATH9K_RX_FILTER_PHYERR);
|
||||
ath9k_ani_restart(ah);
|
||||
|
||||
ENABLE_REGWRITE_BUFFER(ah);
|
||||
|
||||
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
|
||||
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
|
||||
|
||||
REGWRITE_BUFFER_FLUSH(ah);
|
||||
DISABLE_REGWRITE_BUFFER(ah);
|
||||
}
|
||||
|
||||
void ath9k_hw_ani_monitor(struct ath_hw *ah,
|
||||
@@ -639,6 +468,8 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
|
||||
|
||||
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
|
||||
|
||||
ENABLE_REGWRITE_BUFFER(ah);
|
||||
|
||||
REG_WRITE(ah, AR_FILT_OFDM, 0);
|
||||
REG_WRITE(ah, AR_FILT_CCK, 0);
|
||||
REG_WRITE(ah, AR_MIBC,
|
||||
@@ -646,6 +477,9 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
|
||||
& 0x0f);
|
||||
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
|
||||
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
|
||||
|
||||
REGWRITE_BUFFER_FLUSH(ah);
|
||||
DISABLE_REGWRITE_BUFFER(ah);
|
||||
}
|
||||
|
||||
/* Freeze the MIB counters, get the stats and then clear them */
|
||||
@@ -809,8 +643,14 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
|
||||
ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
|
||||
ah->ani[0].cckPhyErrBase);
|
||||
|
||||
ENABLE_REGWRITE_BUFFER(ah);
|
||||
|
||||
REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
|
||||
REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
|
||||
|
||||
REGWRITE_BUFFER_FLUSH(ah);
|
||||
DISABLE_REGWRITE_BUFFER(ah);
|
||||
|
||||
ath9k_enable_mib_counters(ah);
|
||||
|
||||
ah->aniperiod = ATH9K_ANI_PERIOD;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+41
-2011
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,480 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2009 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "hw.h"
|
||||
|
||||
#define AR_BufLen 0x00000fff
|
||||
|
||||
static void ar9002_hw_rx_enable(struct ath_hw *ah)
|
||||
{
|
||||
REG_WRITE(ah, AR_CR, AR_CR_RXE);
|
||||
}
|
||||
|
||||
static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
|
||||
{
|
||||
((struct ath_desc*) ds)->ds_link = ds_link;
|
||||
}
|
||||
|
||||
static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
|
||||
{
|
||||
*ds_link = &((struct ath_desc *)ds)->ds_link;
|
||||
}
|
||||
|
||||
static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
|
||||
{
|
||||
u32 isr = 0;
|
||||
u32 mask2 = 0;
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
u32 sync_cause = 0;
|
||||
bool fatal_int = false;
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
|
||||
if (!AR_SREV_9100(ah)) {
|
||||
if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
|
||||
if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
|
||||
== AR_RTC_STATUS_ON) {
|
||||
isr = REG_READ(ah, AR_ISR);
|
||||
}
|
||||
}
|
||||
|
||||
sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
|
||||
AR_INTR_SYNC_DEFAULT;
|
||||
|
||||
*masked = 0;
|
||||
|
||||
if (!isr && !sync_cause)
|
||||
return false;
|
||||
} else {
|
||||
*masked = 0;
|
||||
isr = REG_READ(ah, AR_ISR);
|
||||
}
|
||||
|
||||
if (isr) {
|
||||
if (isr & AR_ISR_BCNMISC) {
|
||||
u32 isr2;
|
||||
isr2 = REG_READ(ah, AR_ISR_S2);
|
||||
if (isr2 & AR_ISR_S2_TIM)
|
||||
mask2 |= ATH9K_INT_TIM;
|
||||
if (isr2 & AR_ISR_S2_DTIM)
|
||||
mask2 |= ATH9K_INT_DTIM;
|
||||
if (isr2 & AR_ISR_S2_DTIMSYNC)
|
||||
mask2 |= ATH9K_INT_DTIMSYNC;
|
||||
if (isr2 & (AR_ISR_S2_CABEND))
|
||||
mask2 |= ATH9K_INT_CABEND;
|
||||
if (isr2 & AR_ISR_S2_GTT)
|
||||
mask2 |= ATH9K_INT_GTT;
|
||||
if (isr2 & AR_ISR_S2_CST)
|
||||
mask2 |= ATH9K_INT_CST;
|
||||
if (isr2 & AR_ISR_S2_TSFOOR)
|
||||
mask2 |= ATH9K_INT_TSFOOR;
|
||||
}
|
||||
|
||||
isr = REG_READ(ah, AR_ISR_RAC);
|
||||
if (isr == 0xffffffff) {
|
||||
*masked = 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
*masked = isr & ATH9K_INT_COMMON;
|
||||
|
||||
if (ah->config.rx_intr_mitigation) {
|
||||
if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
|
||||
*masked |= ATH9K_INT_RX;
|
||||
}
|
||||
|
||||
if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
|
||||
*masked |= ATH9K_INT_RX;
|
||||
if (isr &
|
||||
(AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
|
||||
AR_ISR_TXEOL)) {
|
||||
u32 s0_s, s1_s;
|
||||
|
||||
*masked |= ATH9K_INT_TX;
|
||||
|
||||
s0_s = REG_READ(ah, AR_ISR_S0_S);
|
||||
ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
|
||||
ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
|
||||
|
||||
s1_s = REG_READ(ah, AR_ISR_S1_S);
|
||||
ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
|
||||
ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
|
||||
}
|
||||
|
||||
if (isr & AR_ISR_RXORN) {
|
||||
ath_print(common, ATH_DBG_INTERRUPT,
|
||||
"receive FIFO overrun interrupt\n");
|
||||
}
|
||||
|
||||
if (!AR_SREV_9100(ah)) {
|
||||
if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
|
||||
u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
|
||||
if (isr5 & AR_ISR_S5_TIM_TIMER)
|
||||
*masked |= ATH9K_INT_TIM_TIMER;
|
||||
}
|
||||
}
|
||||
|
||||
*masked |= mask2;
|
||||
}
|
||||
|
||||
if (AR_SREV_9100(ah))
|
||||
return true;
|
||||
|
||||
if (isr & AR_ISR_GENTMR) {
|
||||
u32 s5_s;
|
||||
|
||||
s5_s = REG_READ(ah, AR_ISR_S5_S);
|
||||
if (isr & AR_ISR_GENTMR) {
|
||||
ah->intr_gen_timer_trigger =
|
||||
MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
|
||||
|
||||
ah->intr_gen_timer_thresh =
|
||||
MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
|
||||
|
||||
if (ah->intr_gen_timer_trigger)
|
||||
*masked |= ATH9K_INT_GENTIMER;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
if (sync_cause) {
|
||||
fatal_int =
|
||||
(sync_cause &
|
||||
(AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
|
||||
? true : false;
|
||||
|
||||
if (fatal_int) {
|
||||
if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
|
||||
ath_print(common, ATH_DBG_ANY,
|
||||
"received PCI FATAL interrupt\n");
|
||||
}
|
||||
if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
|
||||
ath_print(common, ATH_DBG_ANY,
|
||||
"received PCI PERR interrupt\n");
|
||||
}
|
||||
*masked |= ATH9K_INT_FATAL;
|
||||
}
|
||||
if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
|
||||
ath_print(common, ATH_DBG_INTERRUPT,
|
||||
"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
|
||||
REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
|
||||
REG_WRITE(ah, AR_RC, 0);
|
||||
*masked |= ATH9K_INT_FATAL;
|
||||
}
|
||||
if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
|
||||
ath_print(common, ATH_DBG_INTERRUPT,
|
||||
"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
|
||||
}
|
||||
|
||||
REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
|
||||
(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
|
||||
bool is_firstseg, bool is_lastseg,
|
||||
const void *ds0, dma_addr_t buf_addr,
|
||||
unsigned int qcu)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
|
||||
ads->ds_data = buf_addr;
|
||||
|
||||
if (is_firstseg) {
|
||||
ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
|
||||
} else if (is_lastseg) {
|
||||
ads->ds_ctl0 = 0;
|
||||
ads->ds_ctl1 = seglen;
|
||||
ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
|
||||
ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
|
||||
} else {
|
||||
ads->ds_ctl0 = 0;
|
||||
ads->ds_ctl1 = seglen | AR_TxMore;
|
||||
ads->ds_ctl2 = 0;
|
||||
ads->ds_ctl3 = 0;
|
||||
}
|
||||
ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
|
||||
ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
|
||||
ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
|
||||
ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
|
||||
ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
|
||||
}
|
||||
|
||||
static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
|
||||
struct ath_tx_status *ts)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
|
||||
if ((ads->ds_txstatus9 & AR_TxDone) == 0)
|
||||
return -EINPROGRESS;
|
||||
|
||||
ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
|
||||
ts->ts_tstamp = ads->AR_SendTimestamp;
|
||||
ts->ts_status = 0;
|
||||
ts->ts_flags = 0;
|
||||
|
||||
if (ads->ds_txstatus1 & AR_FrmXmitOK)
|
||||
ts->ts_status |= ATH9K_TX_ACKED;
|
||||
if (ads->ds_txstatus1 & AR_ExcessiveRetries)
|
||||
ts->ts_status |= ATH9K_TXERR_XRETRY;
|
||||
if (ads->ds_txstatus1 & AR_Filtered)
|
||||
ts->ts_status |= ATH9K_TXERR_FILT;
|
||||
if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
|
||||
ts->ts_status |= ATH9K_TXERR_FIFO;
|
||||
ath9k_hw_updatetxtriglevel(ah, true);
|
||||
}
|
||||
if (ads->ds_txstatus9 & AR_TxOpExceeded)
|
||||
ts->ts_status |= ATH9K_TXERR_XTXOP;
|
||||
if (ads->ds_txstatus1 & AR_TxTimerExpired)
|
||||
ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
|
||||
|
||||
if (ads->ds_txstatus1 & AR_DescCfgErr)
|
||||
ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
|
||||
if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
|
||||
ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
|
||||
ath9k_hw_updatetxtriglevel(ah, true);
|
||||
}
|
||||
if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
|
||||
ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
|
||||
ath9k_hw_updatetxtriglevel(ah, true);
|
||||
}
|
||||
if (ads->ds_txstatus0 & AR_TxBaStatus) {
|
||||
ts->ts_flags |= ATH9K_TX_BA;
|
||||
ts->ba_low = ads->AR_BaBitmapLow;
|
||||
ts->ba_high = ads->AR_BaBitmapHigh;
|
||||
}
|
||||
|
||||
ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
|
||||
switch (ts->ts_rateindex) {
|
||||
case 0:
|
||||
ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
|
||||
break;
|
||||
case 1:
|
||||
ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
|
||||
break;
|
||||
case 2:
|
||||
ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
|
||||
break;
|
||||
case 3:
|
||||
ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
|
||||
break;
|
||||
}
|
||||
|
||||
ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
|
||||
ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
|
||||
ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
|
||||
ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
|
||||
ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
|
||||
ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
|
||||
ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
|
||||
ts->evm0 = ads->AR_TxEVM0;
|
||||
ts->evm1 = ads->AR_TxEVM1;
|
||||
ts->evm2 = ads->AR_TxEVM2;
|
||||
ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
|
||||
ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
|
||||
ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
|
||||
ts->ts_antenna = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
|
||||
u32 pktLen, enum ath9k_pkt_type type,
|
||||
u32 txPower, u32 keyIx,
|
||||
enum ath9k_key_type keyType, u32 flags)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
|
||||
txPower += ah->txpower_indexoffset;
|
||||
if (txPower > 63)
|
||||
txPower = 63;
|
||||
|
||||
ads->ds_ctl0 = (pktLen & AR_FrameLen)
|
||||
| (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
|
||||
| SM(txPower, AR_XmitPower)
|
||||
| (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
|
||||
| (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
|
||||
| (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
|
||||
| (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
|
||||
|
||||
ads->ds_ctl1 =
|
||||
(keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
|
||||
| SM(type, AR_FrameType)
|
||||
| (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
|
||||
| (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
|
||||
| (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
|
||||
|
||||
ads->ds_ctl6 = SM(keyType, AR_EncrType);
|
||||
|
||||
if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
|
||||
ads->ds_ctl8 = 0;
|
||||
ads->ds_ctl9 = 0;
|
||||
ads->ds_ctl10 = 0;
|
||||
ads->ds_ctl11 = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
|
||||
void *lastds,
|
||||
u32 durUpdateEn, u32 rtsctsRate,
|
||||
u32 rtsctsDuration,
|
||||
struct ath9k_11n_rate_series series[],
|
||||
u32 nseries, u32 flags)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
struct ar5416_desc *last_ads = AR5416DESC(lastds);
|
||||
u32 ds_ctl0;
|
||||
|
||||
if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
|
||||
ds_ctl0 = ads->ds_ctl0;
|
||||
|
||||
if (flags & ATH9K_TXDESC_RTSENA) {
|
||||
ds_ctl0 &= ~AR_CTSEnable;
|
||||
ds_ctl0 |= AR_RTSEnable;
|
||||
} else {
|
||||
ds_ctl0 &= ~AR_RTSEnable;
|
||||
ds_ctl0 |= AR_CTSEnable;
|
||||
}
|
||||
|
||||
ads->ds_ctl0 = ds_ctl0;
|
||||
} else {
|
||||
ads->ds_ctl0 =
|
||||
(ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
|
||||
}
|
||||
|
||||
ads->ds_ctl2 = set11nTries(series, 0)
|
||||
| set11nTries(series, 1)
|
||||
| set11nTries(series, 2)
|
||||
| set11nTries(series, 3)
|
||||
| (durUpdateEn ? AR_DurUpdateEna : 0)
|
||||
| SM(0, AR_BurstDur);
|
||||
|
||||
ads->ds_ctl3 = set11nRate(series, 0)
|
||||
| set11nRate(series, 1)
|
||||
| set11nRate(series, 2)
|
||||
| set11nRate(series, 3);
|
||||
|
||||
ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
|
||||
| set11nPktDurRTSCTS(series, 1);
|
||||
|
||||
ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
|
||||
| set11nPktDurRTSCTS(series, 3);
|
||||
|
||||
ads->ds_ctl7 = set11nRateFlags(series, 0)
|
||||
| set11nRateFlags(series, 1)
|
||||
| set11nRateFlags(series, 2)
|
||||
| set11nRateFlags(series, 3)
|
||||
| SM(rtsctsRate, AR_RTSCTSRate);
|
||||
last_ads->ds_ctl2 = ads->ds_ctl2;
|
||||
last_ads->ds_ctl3 = ads->ds_ctl3;
|
||||
}
|
||||
|
||||
static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
|
||||
u32 aggrLen)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
|
||||
ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
|
||||
ads->ds_ctl6 &= ~AR_AggrLen;
|
||||
ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
|
||||
}
|
||||
|
||||
static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
|
||||
u32 numDelims)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
unsigned int ctl6;
|
||||
|
||||
ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
|
||||
|
||||
ctl6 = ads->ds_ctl6;
|
||||
ctl6 &= ~AR_PadDelim;
|
||||
ctl6 |= SM(numDelims, AR_PadDelim);
|
||||
ads->ds_ctl6 = ctl6;
|
||||
}
|
||||
|
||||
static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
|
||||
ads->ds_ctl1 |= AR_IsAggr;
|
||||
ads->ds_ctl1 &= ~AR_MoreAggr;
|
||||
ads->ds_ctl6 &= ~AR_PadDelim;
|
||||
}
|
||||
|
||||
static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
|
||||
ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
|
||||
}
|
||||
|
||||
static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
|
||||
u32 burstDuration)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
|
||||
ads->ds_ctl2 &= ~AR_BurstDur;
|
||||
ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
|
||||
}
|
||||
|
||||
static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
|
||||
u32 vmf)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
|
||||
if (vmf)
|
||||
ads->ds_ctl0 |= AR_VirtMoreFrag;
|
||||
else
|
||||
ads->ds_ctl0 &= ~AR_VirtMoreFrag;
|
||||
}
|
||||
|
||||
void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
|
||||
u32 size, u32 flags)
|
||||
{
|
||||
struct ar5416_desc *ads = AR5416DESC(ds);
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
|
||||
ads->ds_ctl1 = size & AR_BufLen;
|
||||
if (flags & ATH9K_RXDESC_INTREQ)
|
||||
ads->ds_ctl1 |= AR_RxIntrReq;
|
||||
|
||||
ads->ds_rxstatus8 &= ~AR_RxDone;
|
||||
if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
|
||||
memset(&(ads->u), 0, sizeof(ads->u));
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
|
||||
|
||||
void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
|
||||
{
|
||||
struct ath_hw_ops *ops = ath9k_hw_ops(ah);
|
||||
|
||||
ops->rx_enable = ar9002_hw_rx_enable;
|
||||
ops->set_desc_link = ar9002_hw_set_desc_link;
|
||||
ops->get_desc_link = ar9002_hw_get_desc_link;
|
||||
ops->get_isr = ar9002_hw_get_isr;
|
||||
ops->fill_txdesc = ar9002_hw_fill_txdesc;
|
||||
ops->proc_txdesc = ar9002_hw_proc_txdesc;
|
||||
ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
|
||||
ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
|
||||
ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
|
||||
ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
|
||||
ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
|
||||
ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
|
||||
ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
|
||||
ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,323 @@
|
||||
#ifndef AR9003_EEPROM_H
|
||||
#define AR9003_EEPROM_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define AR9300_EEP_VER 0xD000
|
||||
#define AR9300_EEP_VER_MINOR_MASK 0xFFF
|
||||
#define AR9300_EEP_MINOR_VER_1 0x1
|
||||
#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
|
||||
|
||||
/* 16-bit offset location start of calibration struct */
|
||||
#define AR9300_EEP_START_LOC 256
|
||||
#define AR9300_NUM_5G_CAL_PIERS 8
|
||||
#define AR9300_NUM_2G_CAL_PIERS 3
|
||||
#define AR9300_NUM_5G_20_TARGET_POWERS 8
|
||||
#define AR9300_NUM_5G_40_TARGET_POWERS 8
|
||||
#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
|
||||
#define AR9300_NUM_2G_20_TARGET_POWERS 3
|
||||
#define AR9300_NUM_2G_40_TARGET_POWERS 3
|
||||
/* #define AR9300_NUM_CTLS 21 */
|
||||
#define AR9300_NUM_CTLS_5G 9
|
||||
#define AR9300_NUM_CTLS_2G 12
|
||||
#define AR9300_CTL_MODE_M 0xF
|
||||
#define AR9300_NUM_BAND_EDGES_5G 8
|
||||
#define AR9300_NUM_BAND_EDGES_2G 4
|
||||
#define AR9300_NUM_PD_GAINS 4
|
||||
#define AR9300_PD_GAINS_IN_MASK 4
|
||||
#define AR9300_PD_GAIN_ICEPTS 5
|
||||
#define AR9300_EEPROM_MODAL_SPURS 5
|
||||
#define AR9300_MAX_RATE_POWER 63
|
||||
#define AR9300_NUM_PDADC_VALUES 128
|
||||
#define AR9300_NUM_RATES 16
|
||||
#define AR9300_BCHAN_UNUSED 0xFF
|
||||
#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
|
||||
#define AR9300_OPFLAGS_11A 0x01
|
||||
#define AR9300_OPFLAGS_11G 0x02
|
||||
#define AR9300_OPFLAGS_5G_HT40 0x04
|
||||
#define AR9300_OPFLAGS_2G_HT40 0x08
|
||||
#define AR9300_OPFLAGS_5G_HT20 0x10
|
||||
#define AR9300_OPFLAGS_2G_HT20 0x20
|
||||
#define AR9300_EEPMISC_BIG_ENDIAN 0x01
|
||||
#define AR9300_EEPMISC_WOW 0x02
|
||||
#define AR9300_CUSTOMER_DATA_SIZE 20
|
||||
|
||||
#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
|
||||
#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
|
||||
#define AR9300_MAX_CHAINS 3
|
||||
#define AR9300_ANT_16S 25
|
||||
#define AR9300_FUTURE_MODAL_SZ 6
|
||||
|
||||
#define AR9300_NUM_ANT_CHAIN_FIELDS 7
|
||||
#define AR9300_NUM_ANT_COMMON_FIELDS 4
|
||||
#define AR9300_SIZE_ANT_CHAIN_FIELD 3
|
||||
#define AR9300_SIZE_ANT_COMMON_FIELD 4
|
||||
#define AR9300_ANT_CHAIN_MASK 0x7
|
||||
#define AR9300_ANT_COMMON_MASK 0xf
|
||||
#define AR9300_CHAIN_0_IDX 0
|
||||
#define AR9300_CHAIN_1_IDX 1
|
||||
#define AR9300_CHAIN_2_IDX 2
|
||||
|
||||
#define AR928X_NUM_ANT_CHAIN_FIELDS 6
|
||||
#define AR928X_SIZE_ANT_CHAIN_FIELD 2
|
||||
#define AR928X_ANT_CHAIN_MASK 0x3
|
||||
|
||||
/* Delta from which to start power to pdadc table */
|
||||
/* This offset is used in both open loop and closed loop power control
|
||||
* schemes. In open loop power control, it is not really needed, but for
|
||||
* the "sake of consistency" it was kept. For certain AP designs, this
|
||||
* value is overwritten by the value in the flag "pwrTableOffset" just
|
||||
* before writing the pdadc vs pwr into the chip registers.
|
||||
*/
|
||||
#define AR9300_PWR_TABLE_OFFSET 0
|
||||
|
||||
/* enable flags for voltage and temp compensation */
|
||||
#define ENABLE_TEMP_COMPENSATION 0x01
|
||||
#define ENABLE_VOLT_COMPENSATION 0x02
|
||||
/* byte addressable */
|
||||
#define AR9300_EEPROM_SIZE (16*1024)
|
||||
#define FIXED_CCA_THRESHOLD 15
|
||||
|
||||
#define AR9300_BASE_ADDR 0x3ff
|
||||
|
||||
enum targetPowerHTRates {
|
||||
HT_TARGET_RATE_0_8_16,
|
||||
HT_TARGET_RATE_1_3_9_11_17_19,
|
||||
HT_TARGET_RATE_4,
|
||||
HT_TARGET_RATE_5,
|
||||
HT_TARGET_RATE_6,
|
||||
HT_TARGET_RATE_7,
|
||||
HT_TARGET_RATE_12,
|
||||
HT_TARGET_RATE_13,
|
||||
HT_TARGET_RATE_14,
|
||||
HT_TARGET_RATE_15,
|
||||
HT_TARGET_RATE_20,
|
||||
HT_TARGET_RATE_21,
|
||||
HT_TARGET_RATE_22,
|
||||
HT_TARGET_RATE_23
|
||||
};
|
||||
|
||||
enum targetPowerLegacyRates {
|
||||
LEGACY_TARGET_RATE_6_24,
|
||||
LEGACY_TARGET_RATE_36,
|
||||
LEGACY_TARGET_RATE_48,
|
||||
LEGACY_TARGET_RATE_54
|
||||
};
|
||||
|
||||
enum targetPowerCckRates {
|
||||
LEGACY_TARGET_RATE_1L_5L,
|
||||
LEGACY_TARGET_RATE_5S,
|
||||
LEGACY_TARGET_RATE_11L,
|
||||
LEGACY_TARGET_RATE_11S
|
||||
};
|
||||
|
||||
enum ar9300_Rates {
|
||||
ALL_TARGET_LEGACY_6_24,
|
||||
ALL_TARGET_LEGACY_36,
|
||||
ALL_TARGET_LEGACY_48,
|
||||
ALL_TARGET_LEGACY_54,
|
||||
ALL_TARGET_LEGACY_1L_5L,
|
||||
ALL_TARGET_LEGACY_5S,
|
||||
ALL_TARGET_LEGACY_11L,
|
||||
ALL_TARGET_LEGACY_11S,
|
||||
ALL_TARGET_HT20_0_8_16,
|
||||
ALL_TARGET_HT20_1_3_9_11_17_19,
|
||||
ALL_TARGET_HT20_4,
|
||||
ALL_TARGET_HT20_5,
|
||||
ALL_TARGET_HT20_6,
|
||||
ALL_TARGET_HT20_7,
|
||||
ALL_TARGET_HT20_12,
|
||||
ALL_TARGET_HT20_13,
|
||||
ALL_TARGET_HT20_14,
|
||||
ALL_TARGET_HT20_15,
|
||||
ALL_TARGET_HT20_20,
|
||||
ALL_TARGET_HT20_21,
|
||||
ALL_TARGET_HT20_22,
|
||||
ALL_TARGET_HT20_23,
|
||||
ALL_TARGET_HT40_0_8_16,
|
||||
ALL_TARGET_HT40_1_3_9_11_17_19,
|
||||
ALL_TARGET_HT40_4,
|
||||
ALL_TARGET_HT40_5,
|
||||
ALL_TARGET_HT40_6,
|
||||
ALL_TARGET_HT40_7,
|
||||
ALL_TARGET_HT40_12,
|
||||
ALL_TARGET_HT40_13,
|
||||
ALL_TARGET_HT40_14,
|
||||
ALL_TARGET_HT40_15,
|
||||
ALL_TARGET_HT40_20,
|
||||
ALL_TARGET_HT40_21,
|
||||
ALL_TARGET_HT40_22,
|
||||
ALL_TARGET_HT40_23,
|
||||
ar9300RateSize,
|
||||
};
|
||||
|
||||
|
||||
struct eepFlags {
|
||||
u8 opFlags;
|
||||
u8 eepMisc;
|
||||
} __packed;
|
||||
|
||||
enum CompressAlgorithm {
|
||||
_CompressNone = 0,
|
||||
_CompressLzma,
|
||||
_CompressPairs,
|
||||
_CompressBlock,
|
||||
_Compress4,
|
||||
_Compress5,
|
||||
_Compress6,
|
||||
_Compress7,
|
||||
};
|
||||
|
||||
struct ar9300_base_eep_hdr {
|
||||
u16 regDmn[2];
|
||||
/* 4 bits tx and 4 bits rx */
|
||||
u8 txrxMask;
|
||||
struct eepFlags opCapFlags;
|
||||
u8 rfSilent;
|
||||
u8 blueToothOptions;
|
||||
u8 deviceCap;
|
||||
/* takes lower byte in eeprom location */
|
||||
u8 deviceType;
|
||||
/* offset in dB to be added to beginning
|
||||
* of pdadc table in calibration
|
||||
*/
|
||||
int8_t pwrTableOffset;
|
||||
u8 params_for_tuning_caps[2];
|
||||
/*
|
||||
* bit0 - enable tx temp comp
|
||||
* bit1 - enable tx volt comp
|
||||
* bit2 - enable fastClock - default to 1
|
||||
* bit3 - enable doubling - default to 1
|
||||
* bit4 - enable internal regulator - default to 1
|
||||
*/
|
||||
u8 featureEnable;
|
||||
/* misc flags: bit0 - turn down drivestrength */
|
||||
u8 miscConfiguration;
|
||||
u8 eepromWriteEnableGpio;
|
||||
u8 wlanDisableGpio;
|
||||
u8 wlanLedGpio;
|
||||
u8 rxBandSelectGpio;
|
||||
u8 txrxgain;
|
||||
/* SW controlled internal regulator fields */
|
||||
u32 swreg;
|
||||
} __packed;
|
||||
|
||||
struct ar9300_modal_eep_header {
|
||||
/* 4 idle, t1, t2, b (4 bits per setting) */
|
||||
u32 antCtrlCommon;
|
||||
/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
|
||||
u32 antCtrlCommon2;
|
||||
/* 6 idle, t, r, rx1, rx12, b (2 bits each) */
|
||||
u16 antCtrlChain[AR9300_MAX_CHAINS];
|
||||
/* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
|
||||
u8 xatten1DB[AR9300_MAX_CHAINS];
|
||||
/* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
|
||||
u8 xatten1Margin[AR9300_MAX_CHAINS];
|
||||
int8_t tempSlope;
|
||||
int8_t voltSlope;
|
||||
/* spur channels in usual fbin coding format */
|
||||
u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
|
||||
/* 3 Check if the register is per chain */
|
||||
int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
|
||||
u8 ob[AR9300_MAX_CHAINS];
|
||||
u8 db_stage2[AR9300_MAX_CHAINS];
|
||||
u8 db_stage3[AR9300_MAX_CHAINS];
|
||||
u8 db_stage4[AR9300_MAX_CHAINS];
|
||||
u8 xpaBiasLvl;
|
||||
u8 txFrameToDataStart;
|
||||
u8 txFrameToPaOn;
|
||||
u8 txClip;
|
||||
int8_t antennaGain;
|
||||
u8 switchSettling;
|
||||
int8_t adcDesiredSize;
|
||||
u8 txEndToXpaOff;
|
||||
u8 txEndToRxOn;
|
||||
u8 txFrameToXpaOn;
|
||||
u8 thresh62;
|
||||
u8 futureModal[32];
|
||||
} __packed;
|
||||
|
||||
struct ar9300_cal_data_per_freq_op_loop {
|
||||
int8_t refPower;
|
||||
/* pdadc voltage at power measurement */
|
||||
u8 voltMeas;
|
||||
/* pcdac used for power measurement */
|
||||
u8 tempMeas;
|
||||
/* range is -60 to -127 create a mapping equation 1db resolution */
|
||||
int8_t rxNoisefloorCal;
|
||||
/*range is same as noisefloor */
|
||||
int8_t rxNoisefloorPower;
|
||||
/* temp measured when noisefloor cal was performed */
|
||||
u8 rxTempMeas;
|
||||
} __packed;
|
||||
|
||||
struct cal_tgt_pow_legacy {
|
||||
u8 tPow2x[4];
|
||||
} __packed;
|
||||
|
||||
struct cal_tgt_pow_ht {
|
||||
u8 tPow2x[14];
|
||||
} __packed;
|
||||
|
||||
struct cal_ctl_edge_pwr {
|
||||
u8 tPower:6,
|
||||
flag:2;
|
||||
} __packed;
|
||||
|
||||
struct cal_ctl_data_2g {
|
||||
struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
|
||||
} __packed;
|
||||
|
||||
struct cal_ctl_data_5g {
|
||||
struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
|
||||
} __packed;
|
||||
|
||||
struct ar9300_eeprom {
|
||||
u8 eepromVersion;
|
||||
u8 templateVersion;
|
||||
u8 macAddr[6];
|
||||
u8 custData[AR9300_CUSTOMER_DATA_SIZE];
|
||||
|
||||
struct ar9300_base_eep_hdr baseEepHeader;
|
||||
|
||||
struct ar9300_modal_eep_header modalHeader2G;
|
||||
u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
|
||||
struct ar9300_cal_data_per_freq_op_loop
|
||||
calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
|
||||
u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
|
||||
u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
|
||||
u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
|
||||
u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
|
||||
struct cal_tgt_pow_legacy
|
||||
calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
|
||||
struct cal_tgt_pow_legacy
|
||||
calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
|
||||
struct cal_tgt_pow_ht
|
||||
calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
|
||||
struct cal_tgt_pow_ht
|
||||
calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
|
||||
u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
|
||||
u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
|
||||
struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
|
||||
struct ar9300_modal_eep_header modalHeader5G;
|
||||
u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
|
||||
struct ar9300_cal_data_per_freq_op_loop
|
||||
calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
|
||||
u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
|
||||
u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
|
||||
u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
|
||||
struct cal_tgt_pow_legacy
|
||||
calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
|
||||
struct cal_tgt_pow_ht
|
||||
calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
|
||||
struct cal_tgt_pow_ht
|
||||
calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
|
||||
u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
|
||||
u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
|
||||
struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
|
||||
} __packed;
|
||||
|
||||
s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
|
||||
s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,205 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2010 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "hw.h"
|
||||
#include "ar9003_mac.h"
|
||||
#include "ar9003_initvals.h"
|
||||
|
||||
/* General hardware code for the AR9003 hadware family */
|
||||
|
||||
static bool ar9003_hw_macversion_supported(u32 macversion)
|
||||
{
|
||||
switch (macversion) {
|
||||
case AR_SREV_VERSION_9300:
|
||||
return true;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
/* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
|
||||
/*
|
||||
* XXX: move TX/RX gain INI to its own init_mode_gain_regs after
|
||||
* ensuring it does not affect hardware bring up
|
||||
*/
|
||||
static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
|
||||
{
|
||||
/* mac */
|
||||
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
|
||||
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
|
||||
ar9300_2p0_mac_core,
|
||||
ARRAY_SIZE(ar9300_2p0_mac_core), 2);
|
||||
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
|
||||
ar9300_2p0_mac_postamble,
|
||||
ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
|
||||
|
||||
/* bb */
|
||||
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
|
||||
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
||||
ar9300_2p0_baseband_core,
|
||||
ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
|
||||
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
||||
ar9300_2p0_baseband_postamble,
|
||||
ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
|
||||
|
||||
/* radio */
|
||||
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
|
||||
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
|
||||
ar9300_2p0_radio_core,
|
||||
ARRAY_SIZE(ar9300_2p0_radio_core), 2);
|
||||
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
|
||||
ar9300_2p0_radio_postamble,
|
||||
ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
|
||||
|
||||
/* soc */
|
||||
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
|
||||
ar9300_2p0_soc_preamble,
|
||||
ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
|
||||
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
|
||||
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
|
||||
ar9300_2p0_soc_postamble,
|
||||
ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
|
||||
|
||||
/* rx/tx gain */
|
||||
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
||||
ar9300Common_rx_gain_table_2p0,
|
||||
ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
|
||||
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
|
||||
ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
|
||||
5);
|
||||
|
||||
/* Load PCIE SERDES settings from INI */
|
||||
|
||||
/* Awake Setting */
|
||||
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
||||
ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
|
||||
ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
|
||||
2);
|
||||
|
||||
/* Sleep Setting */
|
||||
|
||||
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
||||
ar9300PciePhy_clkreq_enable_L1_2p0,
|
||||
ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
|
||||
2);
|
||||
|
||||
/* Fast clock modal settings */
|
||||
INIT_INI_ARRAY(&ah->iniModesAdditional,
|
||||
ar9300Modes_fast_clock_2p0,
|
||||
ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
|
||||
3);
|
||||
}
|
||||
|
||||
static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
|
||||
{
|
||||
switch (ar9003_hw_get_tx_gain_idx(ah)) {
|
||||
case 0:
|
||||
default:
|
||||
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
|
||||
ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
|
||||
5);
|
||||
break;
|
||||
case 1:
|
||||
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
ar9300Modes_high_ob_db_tx_gain_table_2p0,
|
||||
ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
|
||||
5);
|
||||
break;
|
||||
case 2:
|
||||
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
ar9300Modes_low_ob_db_tx_gain_table_2p0,
|
||||
ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
|
||||
5);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
|
||||
{
|
||||
switch (ar9003_hw_get_rx_gain_idx(ah)) {
|
||||
case 0:
|
||||
default:
|
||||
INIT_INI_ARRAY(&ah->iniModesRxGain, ar9300Common_rx_gain_table_2p0,
|
||||
ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
|
||||
2);
|
||||
break;
|
||||
case 1:
|
||||
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
||||
ar9300Common_wo_xlna_rx_gain_table_2p0,
|
||||
ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
|
||||
2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* set gain table pointers according to values read from the eeprom */
|
||||
static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
|
||||
{
|
||||
ar9003_tx_gain_table_apply(ah);
|
||||
ar9003_rx_gain_table_apply(ah);
|
||||
}
|
||||
|
||||
/*
|
||||
* Helper for ASPM support.
|
||||
*
|
||||
* Disable PLL when in L0s as well as receiver clock when in L1.
|
||||
* This power saving option must be enabled through the SerDes.
|
||||
*
|
||||
* Programming the SerDes must go through the same 288 bit serial shift
|
||||
* register as the other analog registers. Hence the 9 writes.
|
||||
*/
|
||||
static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
|
||||
int restore,
|
||||
int power_off)
|
||||
{
|
||||
if (ah->is_pciexpress != true)
|
||||
return;
|
||||
|
||||
/* Do not touch SerDes registers */
|
||||
if (ah->config.pcie_powersave_enable == 2)
|
||||
return;
|
||||
|
||||
/* Nothing to do on restore for 11N */
|
||||
if (!restore) {
|
||||
/* set bit 19 to allow forcing of pcie core into L1 state */
|
||||
REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
|
||||
|
||||
/* Several PCIe massages to ensure proper behaviour */
|
||||
if (ah->config.pcie_waen)
|
||||
REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
|
||||
}
|
||||
}
|
||||
|
||||
/* Sets up the AR9003 hardware familiy callbacks */
|
||||
void ar9003_hw_attach_ops(struct ath_hw *ah)
|
||||
{
|
||||
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
|
||||
struct ath_hw_ops *ops = ath9k_hw_ops(ah);
|
||||
|
||||
priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
|
||||
priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
|
||||
priv_ops->macversion_supported = ar9003_hw_macversion_supported;
|
||||
|
||||
ops->config_pci_powersave = ar9003_hw_configpcipowersave;
|
||||
|
||||
ar9003_hw_attach_phy_ops(ah);
|
||||
ar9003_hw_attach_calib_ops(ah);
|
||||
ar9003_hw_attach_mac_ops(ah);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user