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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next into for-davem

Browse Source
This commit is contained in:
John W. Linville
2012-07-12 13:44:50 -04:00
parent 391e5c22f5 2f8684ce7a
commit 38a0084063
198 changed files with 4711 additions and 15838 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/nfc/nfc-hci.txt
+33
View File
@@ -178,3 +178,36 @@ ANY_GET_PARAMETER to the reader A gate to get information on the target
that was discovered).
Typically, such an event will be propagated to NFC Core from MSGRXWQ context.
Error management
----------------
Errors that occur synchronously with the execution of an NFC Core request are
simply returned as the execution result of the request. These are easy.
Errors that occur asynchronously (e.g. in a background protocol handling thread)
must be reported such that upper layers don't stay ignorant that something
went wrong below and know that expected events will probably never happen.
Handling of these errors is done as follows:
- driver (pn544) fails to deliver an incoming frame: it stores the error such
that any subsequent call to the driver will result in this error. Then it calls
the standard nfc_shdlc_recv_frame() with a NULL argument to report the problem
above. shdlc stores a EREMOTEIO sticky status, which will trigger SMW to
report above in turn.
- SMW is basically a background thread to handle incoming and outgoing shdlc
frames. This thread will also check the shdlc sticky status and report to HCI
when it discovers it is not able to run anymore because of an unrecoverable
error that happened within shdlc or below. If the problem occurs during shdlc
connection, the error is reported through the connect completion.
- HCI: if an internal HCI error happens (frame is lost), or HCI is reported an
error from a lower layer, HCI will either complete the currently executing
command with that error, or notify NFC Core directly if no command is executing.
- NFC Core: when NFC Core is notified of an error from below and polling is
active, it will send a tag discovered event with an empty tag list to the user
space to let it know that the poll operation will never be able to detect a tag.
If polling is not active and the error was sticky, lower levels will return it
at next invocation.
MAINTAINERS
-8
View File
@@ -3661,14 +3661,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi.git
S: Supported
F: drivers/net/wireless/iwlwifi/
INTEL WIRELESS MULTICOMM 3200 WIFI (iwmc3200wifi)
M: Samuel Ortiz <samuel.ortiz@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org
S: Supported
W: http://wireless.kernel.org/en/users/Drivers/iwmc3200wifi
F: drivers/net/wireless/iwmc3200wifi/
INTEL MANAGEMENT ENGINE (mei)
M: Tomas Winkler <tomas.winkler@intel.com>
L: linux-kernel@vger.kernel.org
drivers/bcma/bcma_private.h
+9
View File
@@ -10,6 +10,15 @@
#define BCMA_CORE_SIZE 0x1000
#define bcma_err(bus, fmt, ...) \
pr_err("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
#define bcma_warn(bus, fmt, ...) \
pr_warn("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
#define bcma_info(bus, fmt, ...) \
pr_info("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
#define bcma_debug(bus, fmt, ...) \
pr_debug("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
struct bcma_bus;
/* main.c */
drivers/bcma/core.c
+5 -5
View File
@@ -75,7 +75,7 @@ void bcma_core_set_clockmode(struct bcma_device *core,
udelay(10);
}
if (i)
pr_err("HT force timeout\n");
bcma_err(core->bus, "HT force timeout\n");
break;
case BCMA_CLKMODE_DYNAMIC:
bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
@@ -102,9 +102,9 @@ void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on)
udelay(10);
}
if (i)
pr_err("PLL enable timeout\n");
bcma_err(core->bus, "PLL enable timeout\n");
} else {
pr_warn("Disabling PLL not supported yet!\n");
bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
}
}
EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
@@ -120,8 +120,8 @@ u32 bcma_core_dma_translation(struct bcma_device *core)
else
return BCMA_DMA_TRANSLATION_DMA32_CMT;
default:
pr_err("DMA translation unknown for host %d\n",
core->bus->hosttype);
bcma_err(core->bus, "DMA translation unknown for host %d\n",
core->bus->hosttype);
}
return BCMA_DMA_TRANSLATION_NONE;
}
drivers/bcma/driver_chipcommon.c
+2 -3
View File
@@ -44,7 +44,7 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
if (cc->capabilities & BCMA_CC_CAP_PMU)
bcma_pmu_init(cc);
if (cc->capabilities & BCMA_CC_CAP_PCTL)
pr_err("Power control not implemented!\n");
bcma_err(cc->core->bus, "Power control not implemented!\n");
if (cc->core->id.rev >= 16) {
if (cc->core->bus->sprom.leddc_on_time &&
@@ -137,8 +137,7 @@ void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
| BCMA_CC_CORECTL_UARTCLKEN);
}
} else {
pr_err("serial not supported on this device ccrev: 0x%x\n",
ccrev);
bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
return;
}
drivers/bcma/driver_chipcommon_pmu.c
+278 -91
View File
@@ -3,7 +3,8 @@
* ChipCommon Power Management Unit driver
*
* Copyright 2009, Michael Buesch <m@bues.ch>
* Copyright 2007, Broadcom Corporation
* Copyright 2007, 2011, Broadcom Corporation
* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
@@ -54,39 +55,19 @@ void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
}
EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
switch (bus->chipinfo.id) {
case 0x4313:
case 0x4331:
case 43224:
case 43225:
break;
default:
pr_err("PLL init unknown for device 0x%04X\n",
bus->chipinfo.id);
}
}
static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
u32 min_msk = 0, max_msk = 0;
switch (bus->chipinfo.id) {
case 0x4313:
case BCMA_CHIP_ID_BCM4313:
min_msk = 0x200D;
max_msk = 0xFFFF;
break;
case 0x4331:
case 43224:
case 43225:
break;
default:
pr_err("PMU resource config unknown for device 0x%04X\n",
bus->chipinfo.id);
bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
bus->chipinfo.id);
}
/* Set the resource masks. */
@@ -94,22 +75,9 @@ static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
if (max_msk)
bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
}
void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
switch (bus->chipinfo.id) {
case 0x4313:
case 0x4331:
case 43224:
case 43225:
break;
default:
pr_err("PMU switch/regulators init unknown for device "
"0x%04X\n", bus->chipinfo.id);
}
/* Add some delay; allow resources to come up and settle. */
mdelay(2);
}
/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
@@ -123,8 +91,11 @@ void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
val |= BCMA_CHIPCTL_4331_EXTPA_EN;
if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
else if (bus->chipinfo.rev > 0)
val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
} else {
val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
}
bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
@@ -135,28 +106,38 @@ void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
struct bcma_bus *bus = cc->core->bus;
switch (bus->chipinfo.id) {
case 0x4313:
bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
case BCMA_CHIP_ID_BCM4313:
/* enable 12 mA drive strenth for 4313 and set chipControl
register bit 1 */
bcma_chipco_chipctl_maskset(cc, 0,
BCMA_CCTRL_4313_12MA_LED_DRIVE,
BCMA_CCTRL_4313_12MA_LED_DRIVE);
break;
case 0x4331:
case 43431:
case BCMA_CHIP_ID_BCM4331:
case BCMA_CHIP_ID_BCM43431:
/* Ext PA lines must be enabled for tx on BCM4331 */
bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
break;
case 43224:
case BCMA_CHIP_ID_BCM43224:
case BCMA_CHIP_ID_BCM43421:
/* enable 12 mA drive strenth for 43224 and set chipControl
register bit 15 */
if (bus->chipinfo.rev == 0) {
pr_err("Workarounds for 43224 rev 0 not fully "
"implemented\n");
bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
BCMA_CCTRL_43224_GPIO_TOGGLE,
BCMA_CCTRL_43224_GPIO_TOGGLE);
bcma_chipco_chipctl_maskset(cc, 0,
BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
} else {
bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
bcma_chipco_chipctl_maskset(cc, 0,
BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
}
break;
case 43225:
break;
default:
pr_err("Workarounds unknown for device 0x%04X\n",
bus->chipinfo.id);
bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
bus->chipinfo.id);
}
}
@@ -167,8 +148,8 @@ void bcma_pmu_init(struct bcma_drv_cc *cc)
pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
pmucap);
bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
cc->pmu.rev, pmucap);
if (cc->pmu.rev == 1)
bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
@@ -177,12 +158,7 @@ void bcma_pmu_init(struct bcma_drv_cc *cc)
bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
BCMA_CC_PMU_CTL_NOILPONW);
if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
bcma_pmu_pll_init(cc);
bcma_pmu_resources_init(cc);
bcma_pmu_swreg_init(cc);
bcma_pmu_workarounds(cc);
}
@@ -191,23 +167,22 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
struct bcma_bus *bus = cc->core->bus;
switch (bus->chipinfo.id) {
case 0x4716:
case 0x4748:
case 47162:
case 0x4313:
case 0x5357:
case 0x4749:
case 53572:
case BCMA_CHIP_ID_BCM4716:
case BCMA_CHIP_ID_BCM4748:
case BCMA_CHIP_ID_BCM47162:
case BCMA_CHIP_ID_BCM4313:
case BCMA_CHIP_ID_BCM5357:
case BCMA_CHIP_ID_BCM4749:
case BCMA_CHIP_ID_BCM53572:
/* always 20Mhz */
return 20000 * 1000;
case 0x5356:
case 0x5300:
case BCMA_CHIP_ID_BCM5356:
case BCMA_CHIP_ID_BCM4706:
/* always 25Mhz */
return 25000 * 1000;
default:
pr_warn("No ALP clock specified for %04X device, "
"pmu rev. %d, using default %d Hz\n",
bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
}
return BCMA_CC_PMU_ALP_CLOCK;
}
@@ -224,7 +199,8 @@ static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
BUG_ON(!m || m > 4);
if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
/* Detect failure in clock setting */
tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
if (tmp & 0x40000)
@@ -250,33 +226,62 @@ static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
return (fc / div) * 1000000;
}
static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
{
u32 tmp, ndiv, p1div, p2div;
u32 clock;
BUG_ON(!m || m > 4);
/* Get N, P1 and P2 dividers to determine CPU clock */
tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
>> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
>> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
>> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
/* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
clock = (25000000 / 4) * ndiv * p2div / p1div;
else
/* Fixed reference clock 25MHz and m = 2 */
clock = (25000000 / 2) * ndiv * p2div / p1div;
if (m == BCMA_CC_PMU5_MAINPLL_SSB)
clock = clock / 4;
return clock;
}
/* query bus clock frequency for PMU-enabled chipcommon */
u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
switch (bus->chipinfo.id) {
case 0x4716:
case 0x4748:
case 47162:
case BCMA_CHIP_ID_BCM4716:
case BCMA_CHIP_ID_BCM4748:
case BCMA_CHIP_ID_BCM47162:
return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
BCMA_CC_PMU5_MAINPLL_SSB);
case 0x5356:
case BCMA_CHIP_ID_BCM5356:
return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
BCMA_CC_PMU5_MAINPLL_SSB);
case 0x5357:
case 0x4749:
case BCMA_CHIP_ID_BCM5357:
case BCMA_CHIP_ID_BCM4749:
return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
BCMA_CC_PMU5_MAINPLL_SSB);
case 0x5300:
return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
BCMA_CC_PMU5_MAINPLL_SSB);
case 53572:
case BCMA_CHIP_ID_BCM4706:
return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
BCMA_CC_PMU5_MAINPLL_SSB);
case BCMA_CHIP_ID_BCM53572:
return 75000000;
default:
pr_warn("No backplane clock specified for %04X device, "
"pmu rev. %d, using default %d Hz\n",
bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
}
return BCMA_CC_PMU_HT_CLOCK;
}
@@ -286,17 +291,21 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
if (bus->chipinfo.id == 53572)
if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
return 300000000;
if (cc->pmu.rev >= 5) {
u32 pll;
switch (bus->chipinfo.id) {
case 0x5356:
case BCMA_CHIP_ID_BCM4706:
return bcma_pmu_clock_bcm4706(cc,
BCMA_CC_PMU4706_MAINPLL_PLL0,
BCMA_CC_PMU5_MAINPLL_CPU);
case BCMA_CHIP_ID_BCM5356:
pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
break;
case 0x5357:
case 0x4749:
case BCMA_CHIP_ID_BCM5357:
case BCMA_CHIP_ID_BCM4749:
pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
break;
default:
@@ -304,10 +313,188 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
break;
}
/* TODO: if (bus->chipinfo.id == 0x5300)
return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
}
return bcma_pmu_get_clockcontrol(cc);
}
static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
u32 value)
{
bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
}
void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
{
u32 tmp = 0;
u8 phypll_offset = 0;
u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
struct bcma_bus *bus = cc->core->bus;
switch (bus->chipinfo.id) {
case BCMA_CHIP_ID_BCM5357:
case BCMA_CHIP_ID_BCM4749:
case BCMA_CHIP_ID_BCM53572:
/* 5357[ab]0, 43236[ab]0, and 6362b0 */
/* BCM5357 needs to touch PLL1_PLLCTL[02],
so offset PLL0_PLLCTL[02] by 6 */
phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
/* RMW only the P1 divider */
bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
/* RMW only the int feedback divider */
bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
tmp = 1 << 10;
break;
case BCMA_CHIP_ID_BCM4331:
case BCMA_CHIP_ID_BCM43431:
if (spuravoid == 2) {
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0x11500014);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0x0FC00a08);
} else if (spuravoid == 1) {
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0x11500014);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0x0F600a08);
} else {
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0x11100014);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0x03000a08);
}
tmp = 1 << 10;
break;
case BCMA_CHIP_ID_BCM43224:
case BCMA_CHIP_ID_BCM43225:
case BCMA_CHIP_ID_BCM43421:
if (spuravoid == 1) {
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0x11500010);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0x000C0C06);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0x0F600a08);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0x00000000);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0x2001E920);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0x88888815);
} else {
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0x11100010);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0x000c0c06);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0x03000a08);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0x00000000);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0x200005c0);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0x88888815);
}
tmp = 1 << 10;
break;
case BCMA_CHIP_ID_BCM4716:
case BCMA_CHIP_ID_BCM4748:
case BCMA_CHIP_ID_BCM47162:
if (spuravoid == 1) {
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0x11500060);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0x080C0C06);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0x0F600000);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0x00000000);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0x2001E924);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0x88888815);
} else {
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0x11100060);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0x080c0c06);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0x03000000);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0x00000000);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0x200005c0);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0x88888815);
}
tmp = 3 << 9;
break;
case BCMA_CHIP_ID_BCM43227:
case BCMA_CHIP_ID_BCM43228:
case BCMA_CHIP_ID_BCM43428:
/* LCNXN */
/* PLL Settings for spur avoidance on/off mode,
no on2 support for 43228A0 */
if (spuravoid == 1) {
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0x01100014);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0x040C0C06);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0x03140A08);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0x00333333);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0x202C2820);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0x88888815);
} else {
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
0x11100014);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
0x040c0c06);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
0x03000a08);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
0x00000000);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
0x200005c0);
bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
0x88888815);
}
tmp = 1 << 10;
break;
default:
bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
bus->chipinfo.id);
break;
}
tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
}
EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
drivers/bcma/driver_mips.c
+12 -12
View File
@@ -22,15 +22,15 @@
/* The 47162a0 hangs when reading MIPS DMP registers registers */
static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
{
return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
dev->id.id == BCMA_CORE_MIPS_74K;
return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
}
/* The 5357b0 hangs when reading USB20H DMP registers */
static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
{
return (dev->bus->chipinfo.id == 0x5357 ||
dev->bus->chipinfo.id == 0x4749) &&
return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
dev->bus->chipinfo.pkg == 11 &&
dev->id.id == BCMA_CORE_USB20_HOST;
}
@@ -143,8 +143,8 @@ static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
1 << irqflag);
}
pr_info("set_irq: core 0x%04x, irq %d => %d\n",
dev->id.id, oldirq + 2, irq + 2);
bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
dev->id.id, oldirq + 2, irq + 2);
}
static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
@@ -173,7 +173,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
return bcma_pmu_get_clockcpu(&bus->drv_cc);
pr_err("No PMU available, need this to get the cpu clock\n");
bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
return 0;
}
EXPORT_SYMBOL(bcma_cpu_clock);
@@ -185,10 +185,10 @@ static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
case BCMA_CC_FLASHT_STSER:
case BCMA_CC_FLASHT_ATSER:
pr_err("Serial flash not supported.\n");
bcma_err(bus, "Serial flash not supported.\n");
break;
case BCMA_CC_FLASHT_PARA:
pr_info("found parallel flash.\n");
bcma_info(bus, "found parallel flash.\n");
bus->drv_cc.pflash.window = 0x1c000000;
bus->drv_cc.pflash.window_size = 0x02000000;
@@ -199,7 +199,7 @@ static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
bus->drv_cc.pflash.buswidth = 2;
break;
default:
pr_err("flash not supported.\n");
bcma_err(bus, "flash not supported.\n");
}
}
@@ -209,7 +209,7 @@ void bcma_core_mips_init(struct bcma_drv_mips *mcore)
struct bcma_device *core;
bus = mcore->core->bus;
pr_info("Initializing MIPS core...\n");
bcma_info(bus, "Initializing MIPS core...\n");
if (!mcore->setup_done)
mcore->assigned_irqs = 1;
@@ -244,7 +244,7 @@ void bcma_core_mips_init(struct bcma_drv_mips *mcore)
break;
}
}
pr_info("IRQ reconfiguration done\n");
bcma_info(bus, "IRQ reconfiguration done\n");
bcma_core_mips_dump_irq(bus);
if (mcore->setup_done)
drivers/bcma/driver_pci_host.c
+11 -7
View File
@@ -36,7 +36,7 @@ bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
return false;
if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
pr_info("This PCI core is disabled and not working\n");
bcma_info(bus, "This PCI core is disabled and not working\n");
return false;
}
@@ -215,7 +215,8 @@ static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
} else {
writel(val, mmio);
if (chipid == 0x4716 || chipid == 0x4748)
if (chipid == BCMA_CHIP_ID_BCM4716 ||
chipid == BCMA_CHIP_ID_BCM4748)
readl(mmio);
}
@@ -340,6 +341,7 @@ static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
*/
static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
{
struct bcma_bus *bus = pc->core->bus;
u8 cap_ptr, root_ctrl, root_cap, dev;
u16 val16;
int i;
@@ -378,7 +380,8 @@ static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
udelay(10);
}
if (val16 == 0x1)
pr_err("PCI: Broken device in slot %d\n", dev);
bcma_err(bus, "PCI: Broken device in slot %d\n",
dev);
}
}
}
@@ -391,11 +394,11 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
u32 pci_membase_1G;
unsigned long io_map_base;
pr_info("PCIEcore in host mode found\n");
bcma_info(bus, "PCIEcore in host mode found\n");
pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
if (!pc_host) {
pr_err("can not allocate memory");
bcma_err(bus, "can not allocate memory");
return;
}
@@ -434,13 +437,14 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
* as mips can't generate 64-bit address on the
* backplane.
*/
if (bus->chipinfo.id == 0x4716 || bus->chipinfo.id == 0x4748) {
if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
BCMA_SOC_PCI_MEM_SZ - 1;
pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
} else if (bus->chipinfo.id == 0x5300) {
} else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
drivers/bcma/host_pci.c
+3 -2
View File
@@ -18,7 +18,7 @@ static void bcma_host_pci_switch_core(struct bcma_device *core)
pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
core->wrap);
core->bus->mapped_core = core;
pr_debug("Switched to core: 0x%X\n", core->id.id);
bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
}
/* Provides access to the requested core. Returns base offset that has to be
@@ -188,7 +188,7 @@ static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
/* SSB needed additional powering up, do we have any AMBA PCI cards? */
if (!pci_is_pcie(dev))
pr_err("PCI card detected, report problems.\n");
bcma_err(bus, "PCI card detected, report problems.\n");
/* Map MMIO */
err = -ENOMEM;
@@ -268,6 +268,7 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bcma_host_pci_suspend,
static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
drivers/bcma/main.c
+10 -9
View File
@@ -118,8 +118,9 @@ static int bcma_register_cores(struct bcma_bus *bus)
err = device_register(&core->dev);
if (err) {
pr_err("Could not register dev for core 0x%03X\n",
core->id.id);
bcma_err(bus,
"Could not register dev for core 0x%03X\n",
core->id.id);
continue;
}
core->dev_registered = true;
@@ -151,7 +152,7 @@ int __devinit bcma_bus_register(struct bcma_bus *bus)
/* Scan for devices (cores) */
err = bcma_bus_scan(bus);
if (err) {
pr_err("Failed to scan: %d\n", err);
bcma_err(bus, "Failed to scan: %d\n", err);
return -1;
}
@@ -179,14 +180,14 @@ int __devinit bcma_bus_register(struct bcma_bus *bus)
/* Try to get SPROM */
err = bcma_sprom_get(bus);
if (err == -ENOENT) {
pr_err("No SPROM available\n");
bcma_err(bus, "No SPROM available\n");
} else if (err)
pr_err("Failed to get SPROM: %d\n", err);
bcma_err(bus, "Failed to get SPROM: %d\n", err);
/* Register found cores */
bcma_register_cores(bus);
pr_info("Bus registered\n");
bcma_info(bus, "Bus registered\n");
return 0;
}
@@ -214,7 +215,7 @@ int __init bcma_bus_early_register(struct bcma_bus *bus,
/* Scan for chip common core */
err = bcma_bus_scan_early(bus, &match, core_cc);
if (err) {
pr_err("Failed to scan for common core: %d\n", err);
bcma_err(bus, "Failed to scan for common core: %d\n", err);
return -1;
}
@@ -226,7 +227,7 @@ int __init bcma_bus_early_register(struct bcma_bus *bus,
/* Scan for mips core */
err = bcma_bus_scan_early(bus, &match, core_mips);
if (err) {
pr_err("Failed to scan for mips core: %d\n", err);
bcma_err(bus, "Failed to scan for mips core: %d\n", err);
return -1;
}
@@ -244,7 +245,7 @@ int __init bcma_bus_early_register(struct bcma_bus *bus,
bcma_core_mips_init(&bus->drv_mips);
}
pr_info("Early bus registered\n");
bcma_info(bus, "Early bus registered\n");
return 0;
}
drivers/bcma/scan.c
+11 -13
View File
@@ -340,7 +340,7 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
if (tmp <= 0) {
return -EILSEQ;
} else {
pr_info("Bridge found\n");
bcma_info(bus, "Bridge found\n");
return -ENXIO;
}
}
@@ -427,8 +427,8 @@ void bcma_init_bus(struct bcma_bus *bus)
chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
pr_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
chipinfo->id, chipinfo->rev, chipinfo->pkg);
bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
chipinfo->id, chipinfo->rev, chipinfo->pkg);
bus->init_done = true;
}
@@ -482,11 +482,10 @@ int bcma_bus_scan(struct bcma_bus *bus)
other_core = bcma_find_core_reverse(bus, core->id.id);
core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
pr_info("Core %d found: %s "
"(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
core->core_index, bcma_device_name(&core->id),
core->id.manuf, core->id.id, core->id.rev,
core->id.class);
bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
core->core_index, bcma_device_name(&core->id),
core->id.manuf, core->id.id, core->id.rev,
core->id.class);
list_add(&core->list, &bus->cores);
}
@@ -538,11 +537,10 @@ int __init bcma_bus_scan_early(struct bcma_bus *bus,
core->core_index = core_num++;
bus->nr_cores++;
pr_info("Core %d found: %s "
"(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
core->core_index, bcma_device_name(&core->id),
core->id.manuf, core->id.id, core->id.rev,
core->id.class);
bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
core->core_index, bcma_device_name(&core->id),
core->id.manuf, core->id.id, core->id.rev,
core->id.class);
list_add(&core->list, &bus->cores);
err = 0;
drivers/bcma/sprom.c
+14 -12
View File
@@ -60,11 +60,11 @@ static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
if (err)
goto fail;
pr_debug("Using SPROM revision %d provided by"
" platform.\n", bus->sprom.revision);
bcma_debug(bus, "Using SPROM revision %d provided by platform.\n",
bus->sprom.revision);
return 0;
fail:
pr_warn("Using fallback SPROM failed (err %d)\n", err);
bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err);
return err;
}
@@ -468,11 +468,11 @@ static bool bcma_sprom_ext_available(struct bcma_bus *bus)
/* older chipcommon revisions use chip status register */
chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
switch (bus->chipinfo.id) {
case 0x4313:
case BCMA_CHIP_ID_BCM4313:
present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
break;
case 0x4331:
case BCMA_CHIP_ID_BCM4331:
present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
break;
@@ -494,16 +494,16 @@ static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
switch (bus->chipinfo.id) {
case 0x4313:
case BCMA_CHIP_ID_BCM4313:
present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
break;
case 0x4331:
case BCMA_CHIP_ID_BCM4331:
present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
break;
case 43224:
case 43225:
case BCMA_CHIP_ID_BCM43224:
case BCMA_CHIP_ID_BCM43225:
/* for these chips OTP is always available */
present = true;
break;
@@ -579,13 +579,15 @@ int bcma_sprom_get(struct bcma_bus *bus)
if (!sprom)
return -ENOMEM;
if (bus->chipinfo.id == 0x4331 || bus->chipinfo.id == 43431)
if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
pr_debug("SPROM offset 0x%x\n", offset);
bcma_debug(bus, "SPROM offset 0x%x\n", offset);
bcma_sprom_read(bus, offset, sprom);
if (bus->chipinfo.id == 0x4331 || bus->chipinfo.id == 43431)
if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
err = bcma_sprom_valid(sprom);
drivers/misc/Kconfig
-1
View File
@@ -511,7 +511,6 @@ config USB_SWITCH_FSA9480
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
source "drivers/misc/iwmc3200top/Kconfig"
source "drivers/misc/ti-st/Kconfig"
source "drivers/misc/lis3lv02d/Kconfig"
source "drivers/misc/carma/Kconfig"
drivers/misc/Makefile
-1
View File
@@ -36,7 +36,6 @@ obj-$(CONFIG_EP93XX_PWM) += ep93xx_pwm.o
obj-$(CONFIG_DS1682) += ds1682.o
obj-$(CONFIG_TI_DAC7512) += ti_dac7512.o
obj-$(CONFIG_C2PORT) += c2port/
obj-$(CONFIG_IWMC3200TOP) += iwmc3200top/
obj-$(CONFIG_HMC6352) += hmc6352.o
obj-y += eeprom/
obj-y += cb710/
drivers/misc/iwmc3200top/Kconfig
-20
View File
@@ -1,20 +0,0 @@
config IWMC3200TOP
tristate "Intel Wireless MultiCom Top Driver"
depends on MMC && EXPERIMENTAL
select FW_LOADER
---help---
Intel Wireless MultiCom 3200 Top driver is responsible for
for firmware load and enabled coms enumeration
config IWMC3200TOP_DEBUG
bool "Enable full debug output of iwmc3200top Driver"
depends on IWMC3200TOP
---help---
Enable full debug output of iwmc3200top Driver
config IWMC3200TOP_DEBUGFS
bool "Enable Debugfs debugging interface for iwmc3200top"
depends on IWMC3200TOP
---help---
Enable creation of debugfs files for iwmc3200top
drivers/misc/iwmc3200top/Makefile
-29
View File
@@ -1,29 +0,0 @@
# iwmc3200top - Intel Wireless MultiCom 3200 Top Driver
# drivers/misc/iwmc3200top/Makefile
#
# Copyright (C) 2009 Intel Corporation. All rights reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License version
# 2 as published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
#
#
# Author Name: Maxim Grabarnik <maxim.grabarnink@intel.com>
# -
#
#
obj-$(CONFIG_IWMC3200TOP) += iwmc3200top.o
iwmc3200top-objs := main.o fw-download.o
iwmc3200top-$(CONFIG_IWMC3200TOP_DEBUG) += log.o
iwmc3200top-$(CONFIG_IWMC3200TOP_DEBUGFS) += debugfs.o
drivers/misc/iwmc3200top/debugfs.c
-137
View File
@@ -1,137 +0,0 @@
/*
* iwmc3200top - Intel Wireless MultiCom 3200 Top Driver
* drivers/misc/iwmc3200top/debufs.c
*
* Copyright (C) 2009 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*
* Author Name: Maxim Grabarnik <maxim.grabarnink@intel.com>
* -
*
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/sdio.h>
#include <linux/debugfs.h>
#include "iwmc3200top.h"
#include "fw-msg.h"
#include "log.h"
#include "debugfs.h"
/* Constants definition */
#define HEXADECIMAL_RADIX 16
/* Functions definition */
#define DEBUGFS_ADD(name, parent) do { \
dbgfs->dbgfs_##parent##_files.file_##name = \
debugfs_create_file(#name, 0644, dbgfs->dir_##parent, priv, \
&iwmct_dbgfs_##name##_ops); \
} while (0)
#define DEBUGFS_RM(name) do { \
debugfs_remove(name); \
name = NULL; \
} while (0)
#define DEBUGFS_READ_FUNC(name) \
ssize_t iwmct_dbgfs_##name##_read(struct file *file, \
char __user *user_buf, \
size_t count, loff_t *ppos);
#define DEBUGFS_WRITE_FUNC(name) \
ssize_t iwmct_dbgfs_##name##_write(struct file *file, \
const char __user *user_buf, \
size_t count, loff_t *ppos);
#define DEBUGFS_READ_FILE_OPS(name) \
DEBUGFS_READ_FUNC(name) \
static const struct file_operations iwmct_dbgfs_##name##_ops = { \
.read = iwmct_dbgfs_##name##_read, \
.open = iwmct_dbgfs_open_file_generic, \
.llseek = generic_file_llseek, \
};
#define DEBUGFS_WRITE_FILE_OPS(name) \
DEBUGFS_WRITE_FUNC(name) \
static const struct file_operations iwmct_dbgfs_##name##_ops = { \
.write = iwmct_dbgfs_##name##_write, \
.open = iwmct_dbgfs_open_file_generic, \
.llseek = generic_file_llseek, \
};
#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
DEBUGFS_READ_FUNC(name) \
DEBUGFS_WRITE_FUNC(name) \
static const struct file_operations iwmct_dbgfs_##name##_ops = {\
.write = iwmct_dbgfs_##name##_write, \
.read = iwmct_dbgfs_##name##_read, \
.open = iwmct_dbgfs_open_file_generic, \
.llseek = generic_file_llseek, \
};
/* Debugfs file ops definitions */
/*
* Create the debugfs files and directories
*
*/
void iwmct_dbgfs_register(struct iwmct_priv *priv, const char *name)
{
struct iwmct_debugfs *dbgfs;
dbgfs = kzalloc(sizeof(struct iwmct_debugfs), GFP_KERNEL);
if (!dbgfs) {
LOG_ERROR(priv, DEBUGFS, "failed to allocate %zd bytes\n",
sizeof(struct iwmct_debugfs));
return;
}
priv->dbgfs = dbgfs;
dbgfs->name = name;
dbgfs->dir_drv = debugfs_create_dir(name, NULL);
if (!dbgfs->dir_drv) {
LOG_ERROR(priv, DEBUGFS, "failed to create debugfs dir\n");
return;
}
return;
}
/**
* Remove the debugfs files and directories
*
*/
void iwmct_dbgfs_unregister(struct iwmct_debugfs *dbgfs)
{
if (!dbgfs)
return;
DEBUGFS_RM(dbgfs->dir_drv);
kfree(dbgfs);
dbgfs = NULL;
}
drivers/misc/iwmc3200top/debugfs.h
-58
View File
@@ -1,58 +0,0 @@
/*
* iwmc3200top - Intel Wireless MultiCom 3200 Top Driver
* drivers/misc/iwmc3200top/debufs.h
*
* Copyright (C) 2009 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*
* Author Name: Maxim Grabarnik <maxim.grabarnink@intel.com>
* -
*
*/
#ifndef __DEBUGFS_H__
#define __DEBUGFS_H__
#ifdef CONFIG_IWMC3200TOP_DEBUGFS
struct iwmct_debugfs {
const char *name;
struct dentry *dir_drv;
struct dir_drv_files {
} dbgfs_drv_files;
};
void iwmct_dbgfs_register(struct iwmct_priv *priv, const char *name);
void iwmct_dbgfs_unregister(struct iwmct_debugfs *dbgfs);
#else /* CONFIG_IWMC3200TOP_DEBUGFS */
struct iwmct_debugfs;
static inline void
iwmct_dbgfs_register(struct iwmct_priv *priv, const char *name)
{}
static inline void
iwmct_dbgfs_unregister(struct iwmct_debugfs *dbgfs)
{}
#endif /* CONFIG_IWMC3200TOP_DEBUGFS */
#endif /* __DEBUGFS_H__ */
drivers/misc/iwmc3200top/fw-download.c
-358
View File
@@ -1,358 +0,0 @@
/*
* iwmc3200top - Intel Wireless MultiCom 3200 Top Driver
* drivers/misc/iwmc3200top/fw-download.c
*
* Copyright (C) 2009 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*
* Author Name: Maxim Grabarnik <maxim.grabarnink@intel.com>
* -
*
*/
#include <linux/firmware.h>
#include <linux/mmc/sdio_func.h>
#include <linux/slab.h>
#include <asm/unaligned.h>
#include "iwmc3200top.h"
#include "log.h"
#include "fw-msg.h"
#define CHECKSUM_BYTES_NUM sizeof(u32)
/**
init parser struct with file
*/
static int iwmct_fw_parser_init(struct iwmct_priv *priv, const u8 *file,
size_t file_size, size_t block_size)
{
struct iwmct_parser *parser = &priv->parser;
struct iwmct_fw_hdr *fw_hdr = &parser->versions;
LOG_TRACE(priv, FW_DOWNLOAD, "-->\n");
LOG_INFO(priv, FW_DOWNLOAD, "file_size=%zd\n", file_size);
parser->file = file;
parser->file_size = file_size;
parser->cur_pos = 0;
parser->entry_point = 0;
parser->buf = kzalloc(block_size, GFP_KERNEL);
if (!parser->buf) {
LOG_ERROR(priv, FW_DOWNLOAD, "kzalloc error\n");
return -ENOMEM;
}
parser->buf_size = block_size;
/* extract fw versions */
memcpy(fw_hdr, parser->file, sizeof(struct iwmct_fw_hdr));
LOG_INFO(priv, FW_DOWNLOAD, "fw versions are:\n"
"top %u.%u.%u gps %u.%u.%u bt %u.%u.%u tic %s\n",
fw_hdr->top_major, fw_hdr->top_minor, fw_hdr->top_revision,
fw_hdr->gps_major, fw_hdr->gps_minor, fw_hdr->gps_revision,
fw_hdr->bt_major, fw_hdr->bt_minor, fw_hdr->bt_revision,
fw_hdr->tic_name);
parser->cur_pos += sizeof(struct iwmct_fw_hdr);
LOG_TRACE(priv, FW_DOWNLOAD, "<--\n");
return 0;
}
static bool iwmct_checksum(struct iwmct_priv *priv)
{
struct iwmct_parser *parser = &priv->parser;
__le32 *file = (__le32 *)parser->file;
int i, pad, steps;
u32 accum = 0;
u32 checksum;
u32 mask = 0xffffffff;
pad = (parser->file_size - CHECKSUM_BYTES_NUM) % 4;
steps = (parser->file_size - CHECKSUM_BYTES_NUM) / 4;
LOG_INFO(priv, FW_DOWNLOAD, "pad=%d steps=%d\n", pad, steps);
for (i = 0; i < steps; i++)
accum += le32_to_cpu(file[i]);
if (pad) {
mask <<= 8 * (4 - pad);
accum += le32_to_cpu(file[steps]) & mask;
}
checksum = get_unaligned_le32((__le32 *)(parser->file +
parser->file_size - CHECKSUM_BYTES_NUM));
LOG_INFO(priv, FW_DOWNLOAD,
"compare checksum accum=0x%x to checksum=0x%x\n",
accum, checksum);
return checksum == accum;
}
static int iwmct_parse_next_section(struct iwmct_priv *priv, const u8 **p_sec,
size_t *sec_size, __le32 *sec_addr)
{
struct iwmct_parser *parser = &priv->parser;
struct iwmct_dbg *dbg = &priv->dbg;
struct iwmct_fw_sec_hdr *sec_hdr;
LOG_TRACE(priv, FW_DOWNLOAD, "-->\n");
while (parser->cur_pos + sizeof(struct iwmct_fw_sec_hdr)
<= parser->file_size) {
sec_hdr = (struct iwmct_fw_sec_hdr *)
(parser->file + parser->cur_pos);
parser->cur_pos += sizeof(struct iwmct_fw_sec_hdr);
LOG_INFO(priv, FW_DOWNLOAD,
"sec hdr: type=%s addr=0x%x size=%d\n",
sec_hdr->type, sec_hdr->target_addr,
sec_hdr->data_size);
if (strcmp(sec_hdr->type, "ENT") == 0)
parser->entry_point = le32_to_cpu(sec_hdr->target_addr);
else if (strcmp(sec_hdr->type, "LBL") == 0)
strcpy(dbg->label_fw, parser->file + parser->cur_pos);
else if (((strcmp(sec_hdr->type, "TOP") == 0) &&
(priv->barker & BARKER_DNLOAD_TOP_MSK)) ||
((strcmp(sec_hdr->type, "GPS") == 0) &&
(priv->barker & BARKER_DNLOAD_GPS_MSK)) ||
((strcmp(sec_hdr->type, "BTH") == 0) &&
(priv->barker & BARKER_DNLOAD_BT_MSK))) {
*sec_addr = sec_hdr->target_addr;
*sec_size = le32_to_cpu(sec_hdr->data_size);
*p_sec = parser->file + parser->cur_pos;
parser->cur_pos += le32_to_cpu(sec_hdr->data_size);
return 1;
} else if (strcmp(sec_hdr->type, "LOG") != 0)
LOG_WARNING(priv, FW_DOWNLOAD,
"skipping section type %s\n",
sec_hdr->type);
parser->cur_pos += le32_to_cpu(sec_hdr->data_size);
LOG_INFO(priv, FW_DOWNLOAD,
"finished with section cur_pos=%zd\n", parser->cur_pos);
}
LOG_TRACE(priv, INIT, "<--\n");
return 0;
}
static int iwmct_download_section(struct iwmct_priv *priv, const u8 *p_sec,
size_t sec_size, __le32 addr)
{
struct iwmct_parser *parser = &priv->parser;
struct iwmct_fw_load_hdr *hdr = (struct iwmct_fw_load_hdr *)parser->buf;
const u8 *cur_block = p_sec;
size_t sent = 0;
int cnt = 0;
int ret = 0;
u32 cmd = 0;
LOG_TRACE(priv, FW_DOWNLOAD, "-->\n");
LOG_INFO(priv, FW_DOWNLOAD, "Download address 0x%x size 0x%zx\n",
addr, sec_size);
while (sent < sec_size) {
int i;
u32 chksm = 0;
u32 reset = atomic_read(&priv->reset);
/* actual FW data */
u32 data_size = min(parser->buf_size - sizeof(*hdr),
sec_size - sent);
/* Pad to block size */
u32 trans_size = (data_size + sizeof(*hdr) +
IWMC_SDIO_BLK_SIZE - 1) &
~(IWMC_SDIO_BLK_SIZE - 1);
++cnt;
/* in case of reset, interrupt FW DOWNLAOD */
if (reset) {
LOG_INFO(priv, FW_DOWNLOAD,
"Reset detected. Abort FW download!!!");
ret = -ECANCELED;
goto exit;
}
memset(parser->buf, 0, parser->buf_size);
cmd |= IWMC_OPCODE_WRITE << CMD_HDR_OPCODE_POS;
cmd |= IWMC_CMD_SIGNATURE << CMD_HDR_SIGNATURE_POS;
cmd |= (priv->dbg.direct ? 1 : 0) << CMD_HDR_DIRECT_ACCESS_POS;
cmd |= (priv->dbg.checksum ? 1 : 0) << CMD_HDR_USE_CHECKSUM_POS;
hdr->data_size = cpu_to_le32(data_size);
hdr->target_addr = addr;
/* checksum is allowed for sizes divisible by 4 */
if (data_size & 0x3)
cmd &= ~CMD_HDR_USE_CHECKSUM_MSK;
memcpy(hdr->data, cur_block, data_size);
if (cmd & CMD_HDR_USE_CHECKSUM_MSK) {
chksm = data_size + le32_to_cpu(addr) + cmd;
for (i = 0; i < data_size >> 2; i++)
chksm += ((u32 *)cur_block)[i];
hdr->block_chksm = cpu_to_le32(chksm);
LOG_INFO(priv, FW_DOWNLOAD, "Checksum = 0x%X\n",
hdr->block_chksm);
}
LOG_INFO(priv, FW_DOWNLOAD, "trans#%d, len=%d, sent=%zd, "
"sec_size=%zd, startAddress 0x%X\n",
cnt, trans_size, sent, sec_size, addr);
if (priv->dbg.dump)
LOG_HEXDUMP(FW_DOWNLOAD, parser->buf, trans_size);
hdr->cmd = cpu_to_le32(cmd);
/* send it down */
/* TODO: add more proper sending and error checking */
ret = iwmct_tx(priv, parser->buf, trans_size);
if (ret != 0) {
LOG_INFO(priv, FW_DOWNLOAD,
"iwmct_tx returned %d\n", ret);
goto exit;
}
addr = cpu_to_le32(le32_to_cpu(addr) + data_size);
sent += data_size;
cur_block = p_sec + sent;
if (priv->dbg.blocks && (cnt + 1) >= priv->dbg.blocks) {
LOG_INFO(priv, FW_DOWNLOAD,
"Block number limit is reached [%d]\n",
priv->dbg.blocks);
break;
}
}
if (sent < sec_size)
ret = -EINVAL;
exit:
LOG_TRACE(priv, FW_DOWNLOAD, "<--\n");
return ret;
}
static int iwmct_kick_fw(struct iwmct_priv *priv, bool jump)
{
struct iwmct_parser *parser = &priv->parser;
struct iwmct_fw_load_hdr *hdr = (struct iwmct_fw_load_hdr *)parser->buf;
int ret;
u32 cmd;
LOG_TRACE(priv, FW_DOWNLOAD, "-->\n");
memset(parser->buf, 0, parser->buf_size);
cmd = IWMC_CMD_SIGNATURE << CMD_HDR_SIGNATURE_POS;
if (jump) {
cmd |= IWMC_OPCODE_JUMP << CMD_HDR_OPCODE_POS;
hdr->target_addr = cpu_to_le32(parser->entry_point);
LOG_INFO(priv, FW_DOWNLOAD, "jump address 0x%x\n",
parser->entry_point);
} else {
cmd |= IWMC_OPCODE_LAST_COMMAND << CMD_HDR_OPCODE_POS;
LOG_INFO(priv, FW_DOWNLOAD, "last command\n");
}
hdr->cmd = cpu_to_le32(cmd);
LOG_HEXDUMP(FW_DOWNLOAD, parser->buf, sizeof(*hdr));
/* send it down */
/* TODO: add more proper sending and error checking */
ret = iwmct_tx(priv, parser->buf, IWMC_SDIO_BLK_SIZE);
if (ret)
LOG_INFO(priv, FW_DOWNLOAD, "iwmct_tx returned %d", ret);
LOG_TRACE(priv, FW_DOWNLOAD, "<--\n");
return 0;
}
int iwmct_fw_load(struct iwmct_priv *priv)
{
const u8 *fw_name = FW_NAME(FW_API_VER);
const struct firmware *raw;
const u8 *pdata;
size_t len;
__le32 addr;
int ret;
LOG_INFO(priv, FW_DOWNLOAD, "barker download request 0x%x is:\n",
priv->barker);
LOG_INFO(priv, FW_DOWNLOAD, "******* Top FW %s requested ********\n",
(priv->barker & BARKER_DNLOAD_TOP_MSK) ? "was" : "not");
LOG_INFO(priv, FW_DOWNLOAD, "******* GPS FW %s requested ********\n",
(priv->barker & BARKER_DNLOAD_GPS_MSK) ? "was" : "not");
LOG_INFO(priv, FW_DOWNLOAD, "******* BT FW %s requested ********\n",
(priv->barker & BARKER_DNLOAD_BT_MSK) ? "was" : "not");
/* get the firmware */
ret = request_firmware(&raw, fw_name, &priv->func->dev);
if (ret < 0) {
LOG_ERROR(priv, FW_DOWNLOAD, "%s request_firmware failed %d\n",
fw_name, ret);
goto exit;
}
if (raw->size < sizeof(struct iwmct_fw_sec_hdr)) {
LOG_ERROR(priv, FW_DOWNLOAD, "%s smaller then (%zd) (%zd)\n",
fw_name, sizeof(struct iwmct_fw_sec_hdr), raw->size);
goto exit;
}
LOG_INFO(priv, FW_DOWNLOAD, "Read firmware '%s'\n", fw_name);
/* clear parser struct */
ret = iwmct_fw_parser_init(priv, raw->data, raw->size, priv->trans_len);
if (ret < 0) {
LOG_ERROR(priv, FW_DOWNLOAD,
"iwmct_parser_init failed: Reason %d\n", ret);
goto exit;
}
if (!iwmct_checksum(priv)) {
LOG_ERROR(priv, FW_DOWNLOAD, "checksum error\n");
ret = -EINVAL;
goto exit;
}
/* download firmware to device */
while (iwmct_parse_next_section(priv, &pdata, &len, &addr)) {
ret = iwmct_download_section(priv, pdata, len, addr);
if (ret) {
LOG_ERROR(priv, FW_DOWNLOAD,
"%s download section failed\n", fw_name);
goto exit;
}
}
ret = iwmct_kick_fw(priv, !!(priv->barker & BARKER_DNLOAD_JUMP_MSK));
exit:
kfree(priv->parser.buf);
release_firmware(raw);
return ret;
}
drivers/misc/iwmc3200top/fw-msg.h
-113
View File
@@ -1,113 +0,0 @@
/*
* iwmc3200top - Intel Wireless MultiCom 3200 Top Driver
* drivers/misc/iwmc3200top/fw-msg.h
*
* Copyright (C) 2009 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*
* Author Name: Maxim Grabarnik <maxim.grabarnink@intel.com>
* -
*
*/
#ifndef __FWMSG_H__
#define __FWMSG_H__
#define COMM_TYPE_D2H 0xFF
#define COMM_TYPE_H2D 0xEE
#define COMM_CATEGORY_OPERATIONAL 0x00
#define COMM_CATEGORY_DEBUG 0x01
#define COMM_CATEGORY_TESTABILITY 0x02
#define COMM_CATEGORY_DIAGNOSTICS 0x03
#define OP_DBG_ZSTR_MSG cpu_to_le16(0x1A)
#define FW_LOG_SRC_MAX 32
#define FW_LOG_SRC_ALL 255
#define FW_STRING_TABLE_ADDR cpu_to_le32(0x0C000000)
#define CMD_DBG_LOG_LEVEL cpu_to_le16(0x0001)
#define CMD_TST_DEV_RESET cpu_to_le16(0x0060)
#define CMD_TST_FUNC_RESET cpu_to_le16(0x0062)
#define CMD_TST_IFACE_RESET cpu_to_le16(0x0064)
#define CMD_TST_CPU_UTILIZATION cpu_to_le16(0x0065)
#define CMD_TST_TOP_DEEP_SLEEP cpu_to_le16(0x0080)
#define CMD_TST_WAKEUP cpu_to_le16(0x0081)
#define CMD_TST_FUNC_WAKEUP cpu_to_le16(0x0082)
#define CMD_TST_FUNC_DEEP_SLEEP_REQUEST cpu_to_le16(0x0083)
#define CMD_TST_GET_MEM_DUMP cpu_to_le16(0x0096)
#define OP_OPR_ALIVE cpu_to_le16(0x0010)
#define OP_OPR_CMD_ACK cpu_to_le16(0x001F)
#define OP_OPR_CMD_NACK cpu_to_le16(0x0020)
#define OP_TST_MEM_DUMP cpu_to_le16(0x0043)
#define CMD_FLAG_PADDING_256 0x80
#define FW_HCMD_BLOCK_SIZE 256
struct msg_hdr {
u8 type;
u8 category;
__le16 opcode;
u8 seqnum;
u8 flags;
__le16 length;
} __attribute__((__packed__));
struct log_hdr {
__le32 timestamp;
u8 severity;
u8 logsource;
__le16 reserved;
} __attribute__((__packed__));
struct mdump_hdr {
u8 dmpid;
u8 frag;
__le16 size;
__le32 addr;
} __attribute__((__packed__));
struct top_msg {
struct msg_hdr hdr;
union {
/* D2H messages */
struct {
struct log_hdr log_hdr;
u8 data[1];
} __attribute__((__packed__)) log;
struct {
struct log_hdr log_hdr;
struct mdump_hdr md_hdr;
u8 data[1];
} __attribute__((__packed__)) mdump;
/* H2D messages */
struct {
u8 logsource;
u8 sevmask;
} __attribute__((__packed__)) logdefs[FW_LOG_SRC_MAX];
struct mdump_hdr mdump_req;
} u;
} __attribute__((__packed__));
#endif /* __FWMSG_H__ */

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