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Merge branch 'powerpc-next' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc
This commit is contained in:
Paul Mackerras
@@ -17,7 +17,13 @@
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#include <asm/cache.h>
|
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|
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_GLOBAL(__setup_cpu_603)
|
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b setup_common_caches
|
||||
mflr r4
|
||||
BEGIN_FTR_SECTION
|
||||
bl __init_fpu_registers
|
||||
END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
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||||
bl setup_common_caches
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mtlr r4
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blr
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_GLOBAL(__setup_cpu_604)
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mflr r4
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bl setup_common_caches
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@@ -165,9 +165,6 @@ static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
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#ifdef CONFIG_SBC82xx
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#define F1_RXCLK 9
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#define F1_TXCLK 10
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#elif defined(CONFIG_ADS8272)
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#define F1_RXCLK 11
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#define F1_TXCLK 10
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#else
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#define F1_RXCLK 12
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#define F1_TXCLK 11
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@@ -175,13 +172,8 @@ static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
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/* FCC2 Clock Source Configuration. There are board specific.
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Can only choose from CLK13-16 */
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#ifdef CONFIG_ADS8272
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#define F2_RXCLK 15
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#define F2_TXCLK 16
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#else
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#define F2_RXCLK 13
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#define F2_TXCLK 14
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#endif
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||||
|
||||
/* FCC3 Clock Source Configuration. There are board specific.
|
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Can only choose from CLK13-16 */
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@@ -289,10 +281,7 @@ static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
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/* TQM8260 has MDIO and MDCK on PC30 and PC31 respectively */
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#define PC_MDIO ((uint)0x00000002)
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#define PC_MDCK ((uint)0x00000001)
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#elif defined(CONFIG_ADS8272)
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#define PC_MDIO ((uint)0x00002000)
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#define PC_MDCK ((uint)0x00001000)
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#elif defined(CONFIG_EST8260) || defined(CONFIG_ADS8260) || defined(CONFIG_PQ2FADS)
|
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#elif defined(CONFIG_EST8260) || defined(CONFIG_ADS8260)
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#define PC_MDIO ((uint)0x00400000)
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#define PC_MDCK ((uint)0x00200000)
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#else
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@@ -2118,11 +2107,6 @@ init_fcc_startup(fcc_info_t *fip, struct net_device *dev)
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printk("Can't get FCC IRQ %d\n", fip->fc_interrupt);
|
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#ifdef PHY_INTERRUPT
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#ifdef CONFIG_ADS8272
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if (request_irq(PHY_INTERRUPT, mii_link_interrupt, IRQF_SHARED,
|
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"mii", dev) < 0)
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printk(KERN_CRIT "Can't get MII IRQ %d\n", PHY_INTERRUPT);
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#else
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/* Make IRQn edge triggered. This does not work if PHY_INTERRUPT is
|
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* on Port C.
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*/
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@@ -2132,7 +2116,6 @@ init_fcc_startup(fcc_info_t *fip, struct net_device *dev)
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if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0,
|
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"mii", dev) < 0)
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printk(KERN_CRIT "Can't get MII IRQ %d\n", PHY_INTERRUPT);
|
||||
#endif
|
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#endif /* PHY_INTERRUPT */
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/* Set GFMR to enable Ethernet operating mode.
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@@ -946,29 +946,6 @@ static int __init scc_enet_init(void)
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*((volatile uint *)BCSR1) &= ~BCSR1_ETHEN;
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#endif
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#ifdef CONFIG_MPC885ADS
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/* Deassert PHY reset and enable the PHY.
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*/
|
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{
|
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volatile uint __iomem *bcsr = ioremap(BCSR_ADDR, BCSR_SIZE);
|
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uint tmp;
|
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|
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tmp = in_be32(bcsr + 1 /* BCSR1 */);
|
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tmp |= BCSR1_ETHEN;
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out_be32(bcsr + 1, tmp);
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tmp = in_be32(bcsr + 4 /* BCSR4 */);
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tmp |= BCSR4_ETH10_RST;
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out_be32(bcsr + 4, tmp);
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iounmap(bcsr);
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}
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/* On MPC885ADS SCC ethernet PHY defaults to the full duplex mode
|
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* upon reset. SCC is set to half duplex by default. So this
|
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* inconsistency should be better fixed by the software.
|
||||
*/
|
||||
#endif
|
||||
|
||||
dev->base_addr = (unsigned long)ep;
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#if 0
|
||||
dev->name = "CPM_ENET";
|
||||
|
||||
+1
-81
@@ -372,22 +372,6 @@ config MPC8XXFADS
|
||||
bool "FADS"
|
||||
select FADS
|
||||
|
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config MPC86XADS
|
||||
bool "MPC86XADS"
|
||||
help
|
||||
MPC86x Application Development System by Freescale Semiconductor.
|
||||
The MPC86xADS is meant to serve as a platform for s/w and h/w
|
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development around the MPC86X processor families.
|
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select FADS
|
||||
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config MPC885ADS
|
||||
bool "MPC885ADS"
|
||||
help
|
||||
Freescale Semiconductor MPC885 Application Development System (ADS).
|
||||
Also known as DUET.
|
||||
The MPC885ADS is meant to serve as a platform for s/w and h/w
|
||||
development around the MPC885 processor family.
|
||||
|
||||
config TQM823L
|
||||
bool "TQM823L"
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help
|
||||
@@ -479,53 +463,6 @@ config WINCEPT
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endchoice
|
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menu "Freescale Ethernet driver platform-specific options"
|
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depends on FS_ENET
|
||||
|
||||
config MPC8xx_SECOND_ETH
|
||||
bool "Second Ethernet channel"
|
||||
depends on (MPC885ADS || MPC86XADS)
|
||||
default y
|
||||
help
|
||||
This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
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The latter will use SCC1, for 885ADS you can select it below.
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choice
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prompt "Second Ethernet channel"
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depends on MPC8xx_SECOND_ETH
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default MPC8xx_SECOND_ETH_FEC2
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config MPC8xx_SECOND_ETH_FEC2
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bool "FEC2"
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depends on MPC885ADS
|
||||
help
|
||||
Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
|
||||
(often 2-nd UART) will not work if this is enabled.
|
||||
|
||||
config MPC8xx_SECOND_ETH_SCC1
|
||||
bool "SCC1"
|
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depends on MPC86XADS
|
||||
select MPC8xx_SCC_ENET_FIXED
|
||||
help
|
||||
Enable SCC1 to serve as 2-nd Ethernet channel. Note that SMC1
|
||||
(often 1-nd UART) will not work if this is enabled.
|
||||
|
||||
config MPC8xx_SECOND_ETH_SCC3
|
||||
bool "SCC3"
|
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depends on MPC885ADS
|
||||
help
|
||||
Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
|
||||
(often 1-nd UART) will not work if this is enabled.
|
||||
|
||||
endchoice
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||||
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config MPC8xx_SCC_ENET_FIXED
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depends on MPC8xx_SECOND_ETH_SCC
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||||
default n
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bool "Use fixed MII-less mode for SCC Ethernet"
|
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endmenu
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|
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choice
|
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prompt "Machine Type"
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||||
depends on 6xx
|
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@@ -666,9 +603,6 @@ config TQM8260
|
||||
End of Life: not yet :-)
|
||||
URL: <http://www.denx.de/PDF/TQM82xx_SPEC_Rev005.pdf>
|
||||
|
||||
config ADS8272
|
||||
bool "ADS8272"
|
||||
|
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config PQ2FADS
|
||||
bool "Freescale-PQ2FADS"
|
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help
|
||||
@@ -698,11 +632,6 @@ config EV64360
|
||||
platform.
|
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endchoice
|
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config PQ2ADS
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bool
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depends on ADS8272
|
||||
default y
|
||||
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config TQM8xxL
|
||||
bool
|
||||
depends on 8xx && (TQM823L || TQM850L || FPS850L || TQM855L || TQM860L)
|
||||
@@ -725,15 +654,6 @@ config 8260
|
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this option means that you wish to build a kernel for a machine with
|
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an 8260 class CPU.
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config 8272
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bool
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depends on 6xx
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default y if ADS8272
|
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select 8260
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help
|
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The MPC8272 CPM has a different internal dpram setup than other CPM2
|
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devices
|
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|
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config CPM1
|
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bool
|
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depends on 8xx
|
||||
@@ -1069,7 +989,7 @@ config PCI_8260
|
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config 8260_PCI9
|
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bool "Enable workaround for MPC826x erratum PCI 9"
|
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depends on PCI_8260 && !ADS8272
|
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depends on PCI_8260
|
||||
default y
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||||
|
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choice
|
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|
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -4,7 +4,6 @@
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obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o
|
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obj-$(CONFIG_PREP_RESIDUAL) += residual.o
|
||||
obj-$(CONFIG_PQ2ADS) += pq2ads.o
|
||||
obj-$(CONFIG_TQM8260) += tqm8260_setup.o
|
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obj-$(CONFIG_CPCI690) += cpci690.o
|
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obj-$(CONFIG_EV64260) += ev64260.o
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@@ -24,6 +23,3 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o
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obj-$(CONFIG_SPRUCE) += spruce.o
|
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obj-$(CONFIG_LITE5200) += lite5200.o
|
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obj-$(CONFIG_EV64360) += ev64360.o
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obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o
|
||||
obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
|
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obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o
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@@ -22,29 +22,6 @@
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||||
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||||
#include <asm/ppcboot.h>
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#if defined(CONFIG_MPC86XADS)
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||||
#define BOARD_CHIP_NAME "MPC86X"
|
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|
||||
/* U-Boot maps BCSR to 0xff080000 */
|
||||
#define BCSR_ADDR ((uint)0xff080000)
|
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|
||||
/* MPC86XADS has one more CPLD and an additional BCSR.
|
||||
*/
|
||||
#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
|
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#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
|
||||
|
||||
#define BCSR5_T1_RST 0x10
|
||||
#define BCSR5_ATM155_RST 0x08
|
||||
#define BCSR5_ATM25_RST 0x04
|
||||
#define BCSR5_MII1_EN 0x02
|
||||
#define BCSR5_MII1_RST 0x01
|
||||
|
||||
/* There is no PHY link change interrupt */
|
||||
#define PHY_INTERRUPT (-1)
|
||||
|
||||
#else /* FADS */
|
||||
|
||||
/* Memory map is configured by the PROM startup.
|
||||
* I tried to follow the FADS manual, although the startup PROM
|
||||
* dictates this and we simply have to move some of the physical
|
||||
@@ -55,8 +32,6 @@
|
||||
/* PHY link change interrupt */
|
||||
#define PHY_INTERRUPT SIU_IRQ2
|
||||
|
||||
#endif /* CONFIG_MPC86XADS */
|
||||
|
||||
#define BCSR_SIZE ((uint)(64 * 1024))
|
||||
#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
|
||||
#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
|
||||
|
||||
@@ -1,367 +0,0 @@
|
||||
/*
|
||||
* arch/ppc/platforms/mpc8272ads_setup.c
|
||||
*
|
||||
* MPC82xx Board-specific PlatformDevice descriptions
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc.
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/fs_enet_pd.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/mpc8260.h>
|
||||
#include <asm/cpm2.h>
|
||||
#include <asm/immap_cpm2.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/ppc_sys.h>
|
||||
#include <asm/ppcboot.h>
|
||||
#include <linux/fs_uart_pd.h>
|
||||
|
||||
#include "pq2ads_pd.h"
|
||||
|
||||
static void init_fcc1_ioports(struct fs_platform_info*);
|
||||
static void init_fcc2_ioports(struct fs_platform_info*);
|
||||
static void init_scc1_uart_ioports(struct fs_uart_platform_info*);
|
||||
static void init_scc4_uart_ioports(struct fs_uart_platform_info*);
|
||||
|
||||
static struct fs_uart_platform_info mpc8272_uart_pdata[] = {
|
||||
[fsid_scc1_uart] = {
|
||||
.init_ioports = init_scc1_uart_ioports,
|
||||
.fs_no = fsid_scc1_uart,
|
||||
.brg = 1,
|
||||
.tx_num_fifo = 4,
|
||||
.tx_buf_size = 32,
|
||||
.rx_num_fifo = 4,
|
||||
.rx_buf_size = 32,
|
||||
},
|
||||
[fsid_scc4_uart] = {
|
||||
.init_ioports = init_scc4_uart_ioports,
|
||||
.fs_no = fsid_scc4_uart,
|
||||
.brg = 4,
|
||||
.tx_num_fifo = 4,
|
||||
.tx_buf_size = 32,
|
||||
.rx_num_fifo = 4,
|
||||
.rx_buf_size = 32,
|
||||
},
|
||||
};
|
||||
|
||||
static struct fs_mii_bb_platform_info m82xx_mii_bb_pdata = {
|
||||
.mdio_dat.bit = 18,
|
||||
.mdio_dir.bit = 18,
|
||||
.mdc_dat.bit = 19,
|
||||
.delay = 1,
|
||||
};
|
||||
|
||||
static struct fs_platform_info mpc82xx_enet_pdata[] = {
|
||||
[fsid_fcc1] = {
|
||||
.fs_no = fsid_fcc1,
|
||||
.cp_page = CPM_CR_FCC1_PAGE,
|
||||
.cp_block = CPM_CR_FCC1_SBLOCK,
|
||||
|
||||
.clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
|
||||
.clk_route = CMX1_CLK_ROUTE,
|
||||
.clk_mask = CMX1_CLK_MASK,
|
||||
.init_ioports = init_fcc1_ioports,
|
||||
|
||||
.mem_offset = FCC1_MEM_OFFSET,
|
||||
|
||||
.rx_ring = 32,
|
||||
.tx_ring = 32,
|
||||
.rx_copybreak = 240,
|
||||
.use_napi = 0,
|
||||
.napi_weight = 17,
|
||||
.bus_id = "0:00",
|
||||
},
|
||||
[fsid_fcc2] = {
|
||||
.fs_no = fsid_fcc2,
|
||||
.cp_page = CPM_CR_FCC2_PAGE,
|
||||
.cp_block = CPM_CR_FCC2_SBLOCK,
|
||||
.clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
|
||||
.clk_route = CMX2_CLK_ROUTE,
|
||||
.clk_mask = CMX2_CLK_MASK,
|
||||
.init_ioports = init_fcc2_ioports,
|
||||
|
||||
.mem_offset = FCC2_MEM_OFFSET,
|
||||
|
||||
.rx_ring = 32,
|
||||
.tx_ring = 32,
|
||||
.rx_copybreak = 240,
|
||||
.use_napi = 0,
|
||||
.napi_weight = 17,
|
||||
.bus_id = "0:03",
|
||||
},
|
||||
};
|
||||
|
||||
static void init_fcc1_ioports(struct fs_platform_info* pdata)
|
||||
{
|
||||
struct io_port *io;
|
||||
u32 tempval;
|
||||
cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
|
||||
u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32));
|
||||
|
||||
io = &immap->im_ioport;
|
||||
|
||||
/* Enable the PHY */
|
||||
clrbits32(bcsr, BCSR1_FETHIEN);
|
||||
setbits32(bcsr, BCSR1_FETH_RST);
|
||||
|
||||
/* FCC1 pins are on port A/C. */
|
||||
/* Configure port A and C pins for FCC1 Ethernet. */
|
||||
|
||||
tempval = in_be32(&io->iop_pdira);
|
||||
tempval &= ~PA1_DIRA0;
|
||||
tempval |= PA1_DIRA1;
|
||||
out_be32(&io->iop_pdira, tempval);
|
||||
|
||||
tempval = in_be32(&io->iop_psora);
|
||||
tempval &= ~PA1_PSORA0;
|
||||
tempval |= PA1_PSORA1;
|
||||
out_be32(&io->iop_psora, tempval);
|
||||
|
||||
setbits32(&io->iop_ppara,PA1_DIRA0 | PA1_DIRA1);
|
||||
|
||||
/* Alter clocks */
|
||||
tempval = PC_F1TXCLK|PC_F1RXCLK;
|
||||
|
||||
clrbits32(&io->iop_psorc, tempval);
|
||||
clrbits32(&io->iop_pdirc, tempval);
|
||||
setbits32(&io->iop_pparc, tempval);
|
||||
|
||||
clrbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_MASK);
|
||||
setbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_ROUTE);
|
||||
iounmap(bcsr);
|
||||
iounmap(immap);
|
||||
}
|
||||
|
||||
static void init_fcc2_ioports(struct fs_platform_info* pdata)
|
||||
{
|
||||
cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
|
||||
u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32));
|
||||
|
||||
struct io_port *io;
|
||||
u32 tempval;
|
||||
|
||||
immap = cpm2_immr;
|
||||
|
||||
io = &immap->im_ioport;
|
||||
|
||||
/* Enable the PHY */
|
||||
clrbits32(bcsr, BCSR3_FETHIEN2);
|
||||
setbits32(bcsr, BCSR3_FETH2_RST);
|
||||
|
||||
/* FCC2 are port B/C. */
|
||||
/* Configure port A and C pins for FCC2 Ethernet. */
|
||||
|
||||
tempval = in_be32(&io->iop_pdirb);
|
||||
tempval &= ~PB2_DIRB0;
|
||||
tempval |= PB2_DIRB1;
|
||||
out_be32(&io->iop_pdirb, tempval);
|
||||
|
||||
tempval = in_be32(&io->iop_psorb);
|
||||
tempval &= ~PB2_PSORB0;
|
||||
tempval |= PB2_PSORB1;
|
||||
out_be32(&io->iop_psorb, tempval);
|
||||
|
||||
setbits32(&io->iop_pparb,PB2_DIRB0 | PB2_DIRB1);
|
||||
|
||||
tempval = PC_F2RXCLK|PC_F2TXCLK;
|
||||
|
||||
/* Alter clocks */
|
||||
clrbits32(&io->iop_psorc,tempval);
|
||||
clrbits32(&io->iop_pdirc,tempval);
|
||||
setbits32(&io->iop_pparc,tempval);
|
||||
|
||||
clrbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_MASK);
|
||||
setbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_ROUTE);
|
||||
|
||||
iounmap(bcsr);
|
||||
iounmap(immap);
|
||||
}
|
||||
|
||||
|
||||
static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev,
|
||||
int idx)
|
||||
{
|
||||
bd_t* bi = (void*)__res;
|
||||
int fs_no = fsid_fcc1+pdev->id-1;
|
||||
|
||||
if(fs_no >= ARRAY_SIZE(mpc82xx_enet_pdata)) {
|
||||
return;
|
||||
}
|
||||
|
||||
mpc82xx_enet_pdata[fs_no].dpram_offset=
|
||||
(u32)cpm2_immr->im_dprambase;
|
||||
mpc82xx_enet_pdata[fs_no].fcc_regs_c =
|
||||
(u32)cpm2_immr->im_fcc_c;
|
||||
memcpy(&mpc82xx_enet_pdata[fs_no].macaddr,bi->bi_enetaddr,6);
|
||||
|
||||
/* prevent dup mac */
|
||||
if(fs_no == fsid_fcc2)
|
||||
mpc82xx_enet_pdata[fs_no].macaddr[5] ^= 1;
|
||||
|
||||
pdev->dev.platform_data = &mpc82xx_enet_pdata[fs_no];
|
||||
}
|
||||
|
||||
static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev,
|
||||
int idx)
|
||||
{
|
||||
bd_t *bd = (bd_t *) __res;
|
||||
struct fs_uart_platform_info *pinfo;
|
||||
int num = ARRAY_SIZE(mpc8272_uart_pdata);
|
||||
int id = fs_uart_id_scc2fsid(idx);
|
||||
|
||||
/* no need to alter anything if console */
|
||||
if ((id < num) && (!pdev->dev.platform_data)) {
|
||||
pinfo = &mpc8272_uart_pdata[id];
|
||||
pinfo->uart_clk = bd->bi_intfreq;
|
||||
pdev->dev.platform_data = pinfo;
|
||||
}
|
||||
}
|
||||
|
||||
static void init_scc1_uart_ioports(struct fs_uart_platform_info* pdata)
|
||||
{
|
||||
cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
|
||||
|
||||
/* SCC1 is only on port D */
|
||||
setbits32(&immap->im_ioport.iop_ppard,0x00000003);
|
||||
clrbits32(&immap->im_ioport.iop_psord,0x00000001);
|
||||
setbits32(&immap->im_ioport.iop_psord,0x00000002);
|
||||
clrbits32(&immap->im_ioport.iop_pdird,0x00000001);
|
||||
setbits32(&immap->im_ioport.iop_pdird,0x00000002);
|
||||
|
||||
/* Wire BRG1 to SCC1 */
|
||||
clrbits32(&immap->im_cpmux.cmx_scr,0x00ffffff);
|
||||
|
||||
iounmap(immap);
|
||||
}
|
||||
|
||||
static void init_scc4_uart_ioports(struct fs_uart_platform_info* pdata)
|
||||
{
|
||||
cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
|
||||
|
||||
setbits32(&immap->im_ioport.iop_ppard,0x00000600);
|
||||
clrbits32(&immap->im_ioport.iop_psord,0x00000600);
|
||||
clrbits32(&immap->im_ioport.iop_pdird,0x00000200);
|
||||
setbits32(&immap->im_ioport.iop_pdird,0x00000400);
|
||||
|
||||
/* Wire BRG4 to SCC4 */
|
||||
clrbits32(&immap->im_cpmux.cmx_scr,0x000000ff);
|
||||
setbits32(&immap->im_cpmux.cmx_scr,0x0000001b);
|
||||
|
||||
iounmap(immap);
|
||||
}
|
||||
|
||||
static void __init mpc8272ads_fixup_mdio_pdata(struct platform_device *pdev,
|
||||
int idx)
|
||||
{
|
||||
m82xx_mii_bb_pdata.irq[0] = PHY_INTERRUPT;
|
||||
m82xx_mii_bb_pdata.irq[1] = PHY_POLL;
|
||||
m82xx_mii_bb_pdata.irq[2] = PHY_POLL;
|
||||
m82xx_mii_bb_pdata.irq[3] = PHY_INTERRUPT;
|
||||
m82xx_mii_bb_pdata.irq[31] = PHY_POLL;
|
||||
|
||||
|
||||
m82xx_mii_bb_pdata.mdio_dat.offset =
|
||||
(u32)&cpm2_immr->im_ioport.iop_pdatc;
|
||||
|
||||
m82xx_mii_bb_pdata.mdio_dir.offset =
|
||||
(u32)&cpm2_immr->im_ioport.iop_pdirc;
|
||||
|
||||
m82xx_mii_bb_pdata.mdc_dat.offset =
|
||||
(u32)&cpm2_immr->im_ioport.iop_pdatc;
|
||||
|
||||
|
||||
pdev->dev.platform_data = &m82xx_mii_bb_pdata;
|
||||
}
|
||||
|
||||
static int mpc8272ads_platform_notify(struct device *dev)
|
||||
{
|
||||
static const struct platform_notify_dev_map dev_map[] = {
|
||||
{
|
||||
.bus_id = "fsl-cpm-fcc",
|
||||
.rtn = mpc8272ads_fixup_enet_pdata,
|
||||
},
|
||||
{
|
||||
.bus_id = "fsl-cpm-scc:uart",
|
||||
.rtn = mpc8272ads_fixup_uart_pdata,
|
||||
},
|
||||
{
|
||||
.bus_id = "fsl-bb-mdio",
|
||||
.rtn = mpc8272ads_fixup_mdio_pdata,
|
||||
},
|
||||
{
|
||||
.bus_id = NULL
|
||||
}
|
||||
};
|
||||
platform_notify_map(dev_map,dev);
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
int __init mpc8272ads_init(void)
|
||||
{
|
||||
printk(KERN_NOTICE "mpc8272ads: Init\n");
|
||||
|
||||
platform_notify = mpc8272ads_platform_notify;
|
||||
|
||||
ppc_sys_device_initfunc();
|
||||
|
||||
ppc_sys_device_disable_all();
|
||||
ppc_sys_device_enable(MPC82xx_CPM_FCC1);
|
||||
ppc_sys_device_enable(MPC82xx_CPM_FCC2);
|
||||
|
||||
/* to be ready for console, let's attach pdata here */
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC1
|
||||
ppc_sys_device_setfunc(MPC82xx_CPM_SCC1, PPC_SYS_FUNC_UART);
|
||||
ppc_sys_device_enable(MPC82xx_CPM_SCC1);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC4
|
||||
ppc_sys_device_setfunc(MPC82xx_CPM_SCC4, PPC_SYS_FUNC_UART);
|
||||
ppc_sys_device_enable(MPC82xx_CPM_SCC4);
|
||||
#endif
|
||||
|
||||
ppc_sys_device_enable(MPC82xx_MDIO_BB);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
To prevent confusion, console selection is gross:
|
||||
by 0 assumed SCC1 and by 1 assumed SCC4
|
||||
*/
|
||||
struct platform_device* early_uart_get_pdev(int index)
|
||||
{
|
||||
bd_t *bd = (bd_t *) __res;
|
||||
struct fs_uart_platform_info *pinfo;
|
||||
|
||||
struct platform_device* pdev = NULL;
|
||||
if(index) { /*assume SCC4 here*/
|
||||
pdev = &ppc_sys_platform_devices[MPC82xx_CPM_SCC4];
|
||||
pinfo = &mpc8272_uart_pdata[fsid_scc4_uart];
|
||||
} else { /*over SCC1*/
|
||||
pdev = &ppc_sys_platform_devices[MPC82xx_CPM_SCC1];
|
||||
pinfo = &mpc8272_uart_pdata[fsid_scc1_uart];
|
||||
}
|
||||
|
||||
pinfo->uart_clk = bd->bi_intfreq;
|
||||
pdev->dev.platform_data = pinfo;
|
||||
ppc_sys_fixup_mem_resource(pdev, CPM_MAP_ADDR);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
arch_initcall(mpc8272ads_init);
|
||||
@@ -1,93 +0,0 @@
|
||||
/*
|
||||
* A collection of structures, addresses, and values associated with
|
||||
* the Freescale MPC885ADS board.
|
||||
* Copied from the FADS stuff.
|
||||
*
|
||||
* Author: MontaVista Software, Inc.
|
||||
* source@mvista.com
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is licensed
|
||||
* "as is" without any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __ASM_MPC885ADS_H__
|
||||
#define __ASM_MPC885ADS_H__
|
||||
|
||||
|
||||
#include <asm/ppcboot.h>
|
||||
|
||||
/* U-Boot maps BCSR to 0xff080000 */
|
||||
#define BCSR_ADDR ((uint)0xff080000)
|
||||
#define BCSR_SIZE ((uint)32)
|
||||
#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
|
||||
#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
|
||||
#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
|
||||
#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
|
||||
#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
|
||||
|
||||
#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
|
||||
#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
|
||||
|
||||
#define IMAP_ADDR ((uint)0xff000000)
|
||||
#define IMAP_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define PCMCIA_MEM_ADDR ((uint)0xff020000)
|
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
|
||||
|
||||
/* Bits of interest in the BCSRs.
|
||||
*/
|
||||
#define BCSR1_ETHEN ((uint)0x20000000)
|
||||
#define BCSR1_IRDAEN ((uint)0x10000000)
|
||||
#define BCSR1_RS232EN_1 ((uint)0x01000000)
|
||||
#define BCSR1_PCCEN ((uint)0x00800000)
|
||||
#define BCSR1_PCCVCC0 ((uint)0x00400000)
|
||||
#define BCSR1_PCCVPP0 ((uint)0x00200000)
|
||||
#define BCSR1_PCCVPP1 ((uint)0x00100000)
|
||||
#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
|
||||
#define BCSR1_RS232EN_2 ((uint)0x00040000)
|
||||
#define BCSR1_PCCVCC1 ((uint)0x00010000)
|
||||
#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
|
||||
|
||||
#define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
|
||||
#define BCSR4_USB_LO_SPD ((uint)0x04000000)
|
||||
#define BCSR4_USB_VCC ((uint)0x02000000)
|
||||
#define BCSR4_USB_FULL_SPD ((uint)0x00040000)
|
||||
#define BCSR4_USB_EN ((uint)0x00020000)
|
||||
|
||||
#define BCSR5_MII2_EN 0x40
|
||||
#define BCSR5_MII2_RST 0x20
|
||||
#define BCSR5_T1_RST 0x10
|
||||
#define BCSR5_ATM155_RST 0x08
|
||||
#define BCSR5_ATM25_RST 0x04
|
||||
#define BCSR5_MII1_EN 0x02
|
||||
#define BCSR5_MII1_RST 0x01
|
||||
|
||||
/* Interrupt level assignments */
|
||||
#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
|
||||
#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
|
||||
#define SIU_INT_FEC2 SIU_LEVEL3 /* FEC2 interrupt */
|
||||
#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
|
||||
|
||||
/* We don't use the 8259 */
|
||||
#define NR_8259_INTS 0
|
||||
|
||||
/* CPM Ethernet through SCC3 */
|
||||
#define PA_ENET_RXD ((ushort)0x0040)
|
||||
#define PA_ENET_TXD ((ushort)0x0080)
|
||||
#define PE_ENET_TCLK ((uint)0x00004000)
|
||||
#define PE_ENET_RCLK ((uint)0x00008000)
|
||||
#define PE_ENET_TENA ((uint)0x00000010)
|
||||
#define PC_ENET_CLSN ((ushort)0x0400)
|
||||
#define PC_ENET_RENA ((ushort)0x0800)
|
||||
|
||||
/* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to
|
||||
* SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */
|
||||
#define SICR_ENET_MASK ((uint)0x00ff0000)
|
||||
#define SICR_ENET_CLKRT ((uint)0x002c0000)
|
||||
|
||||
#define BOARD_CHIP_NAME "MPC885"
|
||||
|
||||
#endif /* __ASM_MPC885ADS_H__ */
|
||||
#endif /* __KERNEL__ */
|
||||
@@ -1,476 +0,0 @@
|
||||
/*arch/ppc/platforms/mpc885ads_setup.c
|
||||
*
|
||||
* Platform setup for the Freescale mpc885ads board
|
||||
*
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* Copyright 2005 MontaVista Software Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/param.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
#include <linux/fs_enet_pd.h>
|
||||
#include <linux/fs_uart_pd.h>
|
||||
#include <linux/mii.h>
|
||||
|
||||
#include <asm/delay.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/ppcboot.h>
|
||||
#include <asm/8xx_immap.h>
|
||||
#include <asm/cpm1.h>
|
||||
#include <asm/ppc_sys.h>
|
||||
|
||||
extern unsigned char __res[];
|
||||
static void setup_smc1_ioports(struct fs_uart_platform_info*);
|
||||
static void setup_smc2_ioports(struct fs_uart_platform_info*);
|
||||
|
||||
static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
|
||||
static void setup_fec1_ioports(struct fs_platform_info*);
|
||||
static void setup_fec2_ioports(struct fs_platform_info*);
|
||||
static void setup_scc3_ioports(struct fs_platform_info*);
|
||||
|
||||
static struct fs_uart_platform_info mpc885_uart_pdata[] = {
|
||||
[fsid_smc1_uart] = {
|
||||
.brg = 1,
|
||||
.fs_no = fsid_smc1_uart,
|
||||
.init_ioports = setup_smc1_ioports,
|
||||
.tx_num_fifo = 4,
|
||||
.tx_buf_size = 32,
|
||||
.rx_num_fifo = 4,
|
||||
.rx_buf_size = 32,
|
||||
},
|
||||
[fsid_smc2_uart] = {
|
||||
.brg = 2,
|
||||
.fs_no = fsid_smc2_uart,
|
||||
.init_ioports = setup_smc2_ioports,
|
||||
.tx_num_fifo = 4,
|
||||
.tx_buf_size = 32,
|
||||
.rx_num_fifo = 4,
|
||||
.rx_buf_size = 32,
|
||||
},
|
||||
};
|
||||
|
||||
static struct fs_platform_info mpc8xx_enet_pdata[] = {
|
||||
[fsid_fec1] = {
|
||||
.rx_ring = 128,
|
||||
.tx_ring = 16,
|
||||
.rx_copybreak = 240,
|
||||
|
||||
.use_napi = 1,
|
||||
.napi_weight = 17,
|
||||
|
||||
.init_ioports = setup_fec1_ioports,
|
||||
|
||||
.bus_id = "0:00",
|
||||
.has_phy = 1,
|
||||
},
|
||||
[fsid_fec2] = {
|
||||
.rx_ring = 128,
|
||||
.tx_ring = 16,
|
||||
.rx_copybreak = 240,
|
||||
|
||||
.use_napi = 1,
|
||||
.napi_weight = 17,
|
||||
|
||||
.init_ioports = setup_fec2_ioports,
|
||||
|
||||
.bus_id = "0:01",
|
||||
.has_phy = 1,
|
||||
},
|
||||
[fsid_scc3] = {
|
||||
.rx_ring = 64,
|
||||
.tx_ring = 8,
|
||||
.rx_copybreak = 240,
|
||||
|
||||
.use_napi = 1,
|
||||
.napi_weight = 17,
|
||||
|
||||
.init_ioports = setup_scc3_ioports,
|
||||
#ifdef CONFIG_FIXED_MII_10_FDX
|
||||
.bus_id = "fixed@100:1",
|
||||
#else
|
||||
.bus_id = "0:02",
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
void __init board_init(void)
|
||||
{
|
||||
cpm8xx_t *cp = cpmp;
|
||||
unsigned int *bcsr_io;
|
||||
|
||||
#ifdef CONFIG_FS_ENET
|
||||
immap_t *immap = (immap_t *) IMAP_ADDR;
|
||||
#endif
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR\n");
|
||||
return;
|
||||
}
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC1
|
||||
cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
|
||||
clrbits32(bcsr_io, BCSR1_RS232EN_1);
|
||||
cp->cp_smc[0].smc_smcm |= (SMCM_RX | SMCM_TX);
|
||||
cp->cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
|
||||
#else
|
||||
setbits32(bcsr_io,BCSR1_RS232EN_1);
|
||||
cp->cp_smc[0].smc_smcmr = 0;
|
||||
cp->cp_smc[0].smc_smce = 0;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC2
|
||||
cp->cp_simode &= ~(0xe0000000 >> 1);
|
||||
cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
cp->cp_smc[1].smc_smcm |= (SMCM_RX | SMCM_TX);
|
||||
cp->cp_smc[1].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
|
||||
#else
|
||||
setbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
cp->cp_smc[1].smc_smcmr = 0;
|
||||
cp->cp_smc[1].smc_smce = 0;
|
||||
#endif
|
||||
iounmap(bcsr_io);
|
||||
|
||||
#ifdef CONFIG_FS_ENET
|
||||
/* use MDC for MII (common) */
|
||||
setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
|
||||
clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
|
||||
bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
|
||||
clrbits32(bcsr_io,BCSR5_MII1_EN);
|
||||
clrbits32(bcsr_io,BCSR5_MII1_RST);
|
||||
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
|
||||
clrbits32(bcsr_io,BCSR5_MII2_EN);
|
||||
clrbits32(bcsr_io,BCSR5_MII2_RST);
|
||||
#endif
|
||||
iounmap(bcsr_io);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void setup_fec1_ioports(struct fs_platform_info* pdata)
|
||||
{
|
||||
immap_t *immap = (immap_t *) IMAP_ADDR;
|
||||
|
||||
/* configure FEC1 pins */
|
||||
setbits16(&immap->im_ioport.iop_papar, 0xf830);
|
||||
setbits16(&immap->im_ioport.iop_padir, 0x0830);
|
||||
clrbits16(&immap->im_ioport.iop_padir, 0xf000);
|
||||
setbits32(&immap->im_cpm.cp_pbpar, 0x00001001);
|
||||
|
||||
clrbits32(&immap->im_cpm.cp_pbdir, 0x00001001);
|
||||
setbits16(&immap->im_ioport.iop_pcpar, 0x000c);
|
||||
clrbits16(&immap->im_ioport.iop_pcdir, 0x000c);
|
||||
setbits32(&immap->im_cpm.cp_pepar, 0x00000003);
|
||||
|
||||
setbits32(&immap->im_cpm.cp_pedir, 0x00000003);
|
||||
clrbits32(&immap->im_cpm.cp_peso, 0x00000003);
|
||||
clrbits32(&immap->im_cpm.cp_cptr, 0x00000100);
|
||||
}
|
||||
|
||||
static void setup_fec2_ioports(struct fs_platform_info* pdata)
|
||||
{
|
||||
immap_t *immap = (immap_t *) IMAP_ADDR;
|
||||
|
||||
/* configure FEC2 pins */
|
||||
setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
|
||||
setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
|
||||
clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
|
||||
setbits32(&immap->im_cpm.cp_peso, 0x00037800);
|
||||
clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
|
||||
}
|
||||
|
||||
static void setup_scc3_ioports(struct fs_platform_info* pdata)
|
||||
{
|
||||
immap_t *immap = (immap_t *) IMAP_ADDR;
|
||||
unsigned *bcsr_io;
|
||||
|
||||
bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Enable the PHY.
|
||||
*/
|
||||
clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
|
||||
udelay(1000);
|
||||
setbits32(bcsr_io+4, BCSR4_ETH10_RST);
|
||||
/* Configure port A pins for Txd and Rxd.
|
||||
*/
|
||||
setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
|
||||
clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
|
||||
|
||||
/* Configure port C pins to enable CLSN and RENA.
|
||||
*/
|
||||
clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
|
||||
/* Configure port E for TCLK and RCLK.
|
||||
*/
|
||||
setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
|
||||
clrbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
|
||||
clrbits32(&immap->im_cpm.cp_pedir,
|
||||
PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
|
||||
clrbits32(&immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
|
||||
setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
|
||||
|
||||
/* Configure Serial Interface clock routing.
|
||||
* First, clear all SCC bits to zero, then set the ones we want.
|
||||
*/
|
||||
clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
|
||||
setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
|
||||
|
||||
/* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
|
||||
*/
|
||||
immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
|
||||
/* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
|
||||
* by H/W setting after reset. SCC ethernet controller support only half duplex.
|
||||
* This discrepancy of modes causes a lot of carrier lost errors.
|
||||
*/
|
||||
|
||||
/* In the original SCC enet driver the following code is placed at
|
||||
the end of the initialization */
|
||||
setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
|
||||
clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
|
||||
setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
|
||||
|
||||
setbits32(bcsr_io+4, BCSR1_ETHEN);
|
||||
iounmap(bcsr_io);
|
||||
}
|
||||
|
||||
static int mac_count = 0;
|
||||
|
||||
static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
|
||||
{
|
||||
struct fs_platform_info *fpi;
|
||||
bd_t *bd = (bd_t *) __res;
|
||||
char *e;
|
||||
int i;
|
||||
|
||||
if(fs_no >= ARRAY_SIZE(mpc8xx_enet_pdata)) {
|
||||
printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
|
||||
return;
|
||||
}
|
||||
|
||||
fpi = &mpc8xx_enet_pdata[fs_no];
|
||||
|
||||
switch (fs_no) {
|
||||
case fsid_fec1:
|
||||
fpi->init_ioports = &setup_fec1_ioports;
|
||||
break;
|
||||
case fsid_fec2:
|
||||
fpi->init_ioports = &setup_fec2_ioports;
|
||||
break;
|
||||
case fsid_scc3:
|
||||
fpi->init_ioports = &setup_scc3_ioports;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_WARNING "Device %s is not supported!\n", pdev->name);
|
||||
return;
|
||||
}
|
||||
|
||||
pdev->dev.platform_data = fpi;
|
||||
fpi->fs_no = fs_no;
|
||||
|
||||
e = (unsigned char *)&bd->bi_enetaddr;
|
||||
for (i = 0; i < 6; i++)
|
||||
fpi->macaddr[i] = *e++;
|
||||
|
||||
fpi->macaddr[5] += mac_count++;
|
||||
|
||||
}
|
||||
|
||||
static void mpc885ads_fixup_fec_enet_pdata(struct platform_device *pdev,
|
||||
int idx)
|
||||
{
|
||||
/* This is for FEC devices only */
|
||||
if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
|
||||
return;
|
||||
mpc885ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
|
||||
}
|
||||
|
||||
static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev,
|
||||
int idx)
|
||||
{
|
||||
/* This is for SCC devices only */
|
||||
if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
|
||||
return;
|
||||
|
||||
mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
|
||||
}
|
||||
|
||||
static void setup_smc1_ioports(struct fs_uart_platform_info* pdata)
|
||||
{
|
||||
immap_t *immap = (immap_t *) IMAP_ADDR;
|
||||
unsigned *bcsr_io;
|
||||
unsigned int iobits = 0x000000c0;
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR1\n");
|
||||
return;
|
||||
}
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_1);
|
||||
iounmap(bcsr_io);
|
||||
|
||||
setbits32(&immap->im_cpm.cp_pbpar, iobits);
|
||||
clrbits32(&immap->im_cpm.cp_pbdir, iobits);
|
||||
clrbits16(&immap->im_cpm.cp_pbodr, iobits);
|
||||
}
|
||||
|
||||
static void setup_smc2_ioports(struct fs_uart_platform_info* pdata)
|
||||
{
|
||||
immap_t *immap = (immap_t *) IMAP_ADDR;
|
||||
unsigned *bcsr_io;
|
||||
unsigned int iobits = 0x00000c00;
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR1\n");
|
||||
return;
|
||||
}
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
iounmap(bcsr_io);
|
||||
|
||||
#ifndef CONFIG_SERIAL_CPM_ALT_SMC2
|
||||
setbits32(&immap->im_cpm.cp_pbpar, iobits);
|
||||
clrbits32(&immap->im_cpm.cp_pbdir, iobits);
|
||||
clrbits16(&immap->im_cpm.cp_pbodr, iobits);
|
||||
#else
|
||||
setbits16(&immap->im_ioport.iop_papar, iobits);
|
||||
clrbits16(&immap->im_ioport.iop_padir, iobits);
|
||||
clrbits16(&immap->im_ioport.iop_paodr, iobits);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init mpc885ads_fixup_uart_pdata(struct platform_device *pdev,
|
||||
int idx)
|
||||
{
|
||||
bd_t *bd = (bd_t *) __res;
|
||||
struct fs_uart_platform_info *pinfo;
|
||||
int num = ARRAY_SIZE(mpc885_uart_pdata);
|
||||
|
||||
int id = fs_uart_id_smc2fsid(idx);
|
||||
|
||||
/* no need to alter anything if console */
|
||||
if ((id < num) && (!pdev->dev.platform_data)) {
|
||||
pinfo = &mpc885_uart_pdata[id];
|
||||
pinfo->uart_clk = bd->bi_intfreq;
|
||||
pdev->dev.platform_data = pinfo;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static int mpc885ads_platform_notify(struct device *dev)
|
||||
{
|
||||
|
||||
static const struct platform_notify_dev_map dev_map[] = {
|
||||
{
|
||||
.bus_id = "fsl-cpm-fec",
|
||||
.rtn = mpc885ads_fixup_fec_enet_pdata,
|
||||
},
|
||||
{
|
||||
.bus_id = "fsl-cpm-scc",
|
||||
.rtn = mpc885ads_fixup_scc_enet_pdata,
|
||||
},
|
||||
{
|
||||
.bus_id = "fsl-cpm-smc:uart",
|
||||
.rtn = mpc885ads_fixup_uart_pdata
|
||||
},
|
||||
{
|
||||
.bus_id = NULL
|
||||
}
|
||||
};
|
||||
|
||||
platform_notify_map(dev_map,dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init mpc885ads_init(void)
|
||||
{
|
||||
struct fs_mii_fec_platform_info* fmpi;
|
||||
bd_t *bd = (bd_t *) __res;
|
||||
|
||||
printk(KERN_NOTICE "mpc885ads: Init\n");
|
||||
|
||||
platform_notify = mpc885ads_platform_notify;
|
||||
|
||||
ppc_sys_device_initfunc();
|
||||
ppc_sys_device_disable_all();
|
||||
|
||||
ppc_sys_device_enable(MPC8xx_CPM_FEC1);
|
||||
|
||||
ppc_sys_device_enable(MPC8xx_MDIO_FEC);
|
||||
fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
|
||||
&mpc8xx_mdio_fec_pdata;
|
||||
|
||||
fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
|
||||
|
||||
/* No PHY interrupt line here */
|
||||
fmpi->irq[0xf] = SIU_IRQ7;
|
||||
|
||||
#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
|
||||
ppc_sys_device_enable(MPC8xx_CPM_SCC3);
|
||||
|
||||
#endif
|
||||
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
|
||||
ppc_sys_device_enable(MPC8xx_CPM_FEC2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC1
|
||||
ppc_sys_device_enable(MPC8xx_CPM_SMC1);
|
||||
ppc_sys_device_setfunc(MPC8xx_CPM_SMC1, PPC_SYS_FUNC_UART);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC2
|
||||
ppc_sys_device_enable(MPC8xx_CPM_SMC2);
|
||||
ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(mpc885ads_init);
|
||||
|
||||
/*
|
||||
To prevent confusion, console selection is gross:
|
||||
by 0 assumed SMC1 and by 1 assumed SMC2
|
||||
*/
|
||||
struct platform_device* early_uart_get_pdev(int index)
|
||||
{
|
||||
bd_t *bd = (bd_t *) __res;
|
||||
struct fs_uart_platform_info *pinfo;
|
||||
|
||||
struct platform_device* pdev = NULL;
|
||||
if(index) { /*assume SMC2 here*/
|
||||
pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC2];
|
||||
pinfo = &mpc885_uart_pdata[1];
|
||||
} else { /*over SMC1*/
|
||||
pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC1];
|
||||
pinfo = &mpc885_uart_pdata[0];
|
||||
}
|
||||
|
||||
pinfo->uart_clk = bd->bi_intfreq;
|
||||
pdev->dev.platform_data = pinfo;
|
||||
ppc_sys_fixup_mem_resource(pdev, IMAP_ADDR);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@@ -1,53 +0,0 @@
|
||||
/*
|
||||
* PQ2ADS platform support
|
||||
*
|
||||
* Author: Kumar Gala <galak@kernel.crashing.org>
|
||||
* Derived from: est8260_setup.c by Allen Curtis
|
||||
*
|
||||
* Copyright 2004 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/mpc8260.h>
|
||||
#include <asm/cpm2.h>
|
||||
#include <asm/immap_cpm2.h>
|
||||
|
||||
void __init
|
||||
m82xx_board_setup(void)
|
||||
{
|
||||
cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
|
||||
u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32));
|
||||
|
||||
/* Enable the 2nd UART port */
|
||||
clrbits32(bcsr, BCSR1_RS232_EN2);
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC1
|
||||
clrbits32((u32*)&immap->im_scc[0].scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
|
||||
clrbits32((u32*)&immap->im_scc[0].scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC2
|
||||
clrbits32((u32*)&immap->im_scc[1].scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
|
||||
clrbits32((u32*)&immap->im_scc[1].scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC3
|
||||
clrbits32((u32*)&immap->im_scc[2].scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
|
||||
clrbits32((u32*)&immap->im_scc[2].scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SCC4
|
||||
clrbits32((u32*)&immap->im_scc[3].scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
|
||||
clrbits32((u32*)&immap->im_scc[3].scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
#endif
|
||||
|
||||
iounmap(bcsr);
|
||||
iounmap(immap);
|
||||
}
|
||||
@@ -1,94 +0,0 @@
|
||||
/*
|
||||
* A collection of structures, addresses, and values associated with
|
||||
* the Motorola MPC8260ADS/MPC8266ADS-PCI boards.
|
||||
* Copied from the RPX-Classic and SBS8260 stuff.
|
||||
*
|
||||
* Copyright (c) 2001 Dan Malek (dan@mvista.com)
|
||||
*/
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __MACH_ADS8260_DEFS
|
||||
#define __MACH_ADS8260_DEFS
|
||||
|
||||
|
||||
#include <asm/ppcboot.h>
|
||||
|
||||
#if defined(CONFIG_ADS8272)
|
||||
#define BOARD_CHIP_NAME "8272"
|
||||
#endif
|
||||
|
||||
/* Memory map is configured by the PROM startup.
|
||||
* We just map a few things we need. The CSR is actually 4 byte-wide
|
||||
* registers that can be accessed as 8-, 16-, or 32-bit values.
|
||||
*/
|
||||
#define CPM_MAP_ADDR ((uint)0xf0000000)
|
||||
#define BCSR_ADDR ((uint)0xf4500000)
|
||||
#define BCSR_SIZE ((uint)(32 * 1024))
|
||||
|
||||
#define BOOTROM_RESTART_ADDR ((uint)0xff000104)
|
||||
|
||||
/* For our show_cpuinfo hooks. */
|
||||
#define CPUINFO_VENDOR "Motorola"
|
||||
#define CPUINFO_MACHINE "PQ2 ADS PowerPC"
|
||||
|
||||
/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
|
||||
* only on word boundaries.
|
||||
* Not all are used (yet), or are interesting to us (yet).
|
||||
*/
|
||||
|
||||
/* Things of interest in the CSR.
|
||||
*/
|
||||
#define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */
|
||||
#define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */
|
||||
#define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable */
|
||||
#define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */
|
||||
#define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 == enable */
|
||||
#define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 == enable */
|
||||
#define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable */
|
||||
#define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */
|
||||
|
||||
#define PHY_INTERRUPT SIU_INT_IRQ7
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* PCI interrupt controller */
|
||||
#define PCI_INT_STAT_REG 0xF8200000
|
||||
#define PCI_INT_MASK_REG 0xF8200004
|
||||
#define PIRQA (NR_CPM_INTS + 0)
|
||||
#define PIRQB (NR_CPM_INTS + 1)
|
||||
#define PIRQC (NR_CPM_INTS + 2)
|
||||
#define PIRQD (NR_CPM_INTS + 3)
|
||||
|
||||
/*
|
||||
* PCI memory map definitions for MPC8266ADS-PCI.
|
||||
*
|
||||
* processor view
|
||||
* local address PCI address target
|
||||
* 0x80000000-0x9FFFFFFF 0x80000000-0x9FFFFFFF PCI mem with prefetch
|
||||
* 0xA0000000-0xBFFFFFFF 0xA0000000-0xBFFFFFFF PCI mem w/o prefetch
|
||||
* 0xF4000000-0xF7FFFFFF 0x00000000-0x03FFFFFF PCI IO
|
||||
*
|
||||
* PCI master view
|
||||
* local address PCI address target
|
||||
* 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
|
||||
*/
|
||||
|
||||
/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
|
||||
Here we should redefine what is unique for this board */
|
||||
#define M82xx_PCI_SLAVE_MEM_LOCAL 0x00000000 /* Local base */
|
||||
#define M82xx_PCI_SLAVE_MEM_BUS 0x00000000 /* PCI base */
|
||||
#define M82xx_PCI_SLAVE_MEM_SIZE 0x10000000 /* 256 Mb */
|
||||
|
||||
#define M82xx_PCI_SLAVE_SEC_WND_SIZE ~(0x40000000 - 1U) /* 2 x 512Mb */
|
||||
#define M82xx_PCI_SLAVE_SEC_WND_BASE 0x80000000 /* PCI Memory base */
|
||||
|
||||
#if defined(CONFIG_ADS8272)
|
||||
#define PCI_INT_TO_SIU SIU_INT_IRQ2
|
||||
#elif defined(CONFIG_PQ2FADS)
|
||||
#define PCI_INT_TO_SIU SIU_INT_IRQ6
|
||||
#else
|
||||
#warning PCI Bridge will be without interrupts support
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#endif /* __MACH_ADS8260_DEFS */
|
||||
#endif /* __KERNEL__ */
|
||||
@@ -1,32 +0,0 @@
|
||||
#ifndef __PQ2ADS_PD_H
|
||||
#define __PQ2ADS_PD_H
|
||||
/*
|
||||
* arch/ppc/platforms/82xx/pq2ads_pd.h
|
||||
*
|
||||
* Some defines for MPC82xx board-specific PlatformDevice descriptions
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc.
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/* FCC1 Clock Source Configuration. These can be redefined in the board specific file.
|
||||
Can only choose from CLK9-12 */
|
||||
|
||||
#define F1_RXCLK 11
|
||||
#define F1_TXCLK 10
|
||||
|
||||
/* FCC2 Clock Source Configuration. These can be redefined in the board specific file.
|
||||
Can only choose from CLK13-16 */
|
||||
#define F2_RXCLK 15
|
||||
#define F2_TXCLK 16
|
||||
|
||||
/* FCC3 Clock Source Configuration. These can be redefined in the board specific file.
|
||||
Can only choose from CLK13-16 */
|
||||
#define F3_RXCLK 13
|
||||
#define F3_TXCLK 14
|
||||
|
||||
#endif
|
||||
@@ -175,12 +175,6 @@ m8260_init_IRQ(void)
|
||||
* in case the boot rom changed something on us.
|
||||
*/
|
||||
cpm2_immr->im_intctl.ic_siprr = 0x05309770;
|
||||
|
||||
#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS))
|
||||
/* Initialize stuff for the 82xx CPLD IC and install demux */
|
||||
pq2pci_init_irq();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -150,14 +150,6 @@ pq2pci_init_irq(void)
|
||||
{
|
||||
int irq;
|
||||
volatile cpm2_map_t *immap = cpm2_immr;
|
||||
#if defined CONFIG_ADS8272
|
||||
/* configure chip select for PCI interrupt controller */
|
||||
immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
|
||||
immap->im_memctl.memc_or3 = 0xffff8010;
|
||||
#elif defined CONFIG_PQ2FADS
|
||||
immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
|
||||
immap->im_memctl.memc_or8 = 0xffff8010;
|
||||
#endif
|
||||
for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
|
||||
irq_desc[irq].chip = &pq2pci_ic;
|
||||
|
||||
@@ -222,26 +214,6 @@ pq2ads_setup_pci(struct pci_controller *hose)
|
||||
immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;
|
||||
#endif
|
||||
|
||||
#if defined CONFIG_ADS8272
|
||||
immap->im_siu_conf.siu_82xx.sc_siumcr =
|
||||
(immap->im_siu_conf.siu_82xx.sc_siumcr &
|
||||
~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |
|
||||
SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |
|
||||
SIUMCR_LBPC11 | SIUMCR_APPC11 |
|
||||
SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |
|
||||
SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |
|
||||
SIUMCR_APPC10 | SIUMCR_CS10PC00 |
|
||||
SIUMCR_BCTLC00 | SIUMCR_MMR11 ;
|
||||
|
||||
#elif defined CONFIG_PQ2FADS
|
||||
/*
|
||||
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
|
||||
* and local bus for PCI (SIUMCR [LBPC]).
|
||||
*/
|
||||
immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr &
|
||||
~(SIUMCR_L2CPC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
|
||||
SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10);
|
||||
#endif
|
||||
/* Enable PCI */
|
||||
immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
|
||||
|
||||
@@ -284,12 +256,6 @@ pq2ads_setup_pci(struct pci_controller *hose)
|
||||
immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT);
|
||||
immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT);
|
||||
|
||||
#if defined CONFIG_ADS8272
|
||||
/* PCI int highest prio */
|
||||
immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
|
||||
#elif defined CONFIG_PQ2FADS
|
||||
immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
|
||||
#endif
|
||||
/* park bus on PCI */
|
||||
immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
|
||||
|
||||
@@ -320,10 +286,6 @@ void __init pq2_find_bridges(void)
|
||||
hose->bus_offset = 0;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
#ifdef CONFIG_ADS8272
|
||||
hose->set_cfg_type = 1;
|
||||
#endif
|
||||
|
||||
setup_m8260_indirect_pci(hose,
|
||||
(unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
|
||||
(unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
|
||||
|
||||
@@ -139,16 +139,6 @@ m8xx_setup_arch(void)
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_MPC86XADS) || defined (CONFIG_MPC885ADS)
|
||||
#if defined(CONFIG_MTD_PHYSMAP)
|
||||
physmap_configure(binfo->bi_flashstart, binfo->bi_flashsize,
|
||||
MPC8xxADS_BANK_WIDTH, NULL);
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
physmap_set_partitions(mpc8xxads_partitions, mpc8xxads_part_num);
|
||||
#endif /* CONFIG_MTD_PARTITIONS */
|
||||
#endif /* CONFIG_MTD_PHYSMAP */
|
||||
#endif
|
||||
|
||||
board_init();
|
||||
|
||||
@@ -35,10 +35,6 @@
|
||||
#include <platforms/tqm8260.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PQ2ADS) || defined (CONFIG_PQ2FADS)
|
||||
#include <platforms/pq2ads.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_8260
|
||||
#include <syslib/m82xx_pci.h>
|
||||
#endif
|
||||
|
||||
@@ -63,10 +63,6 @@
|
||||
#include <platforms/lantec.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC885ADS)
|
||||
#include <platforms/mpc885ads.h>
|
||||
#endif
|
||||
|
||||
/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
|
||||
* use the same memory map.
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user