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Staging: rtl8192su: remove dead code

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Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Bartlomiej Zolnierkiewicz
2009-07-03 16:08:32 +02:00
committed by Greg Kroah-Hartman
parent 9f7f00cd28
commit 35c1b46291
25 changed files with 18 additions and 3442 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/staging/rtl8192su/ieee80211/dot11d.c
+1 -4
View File
@@ -34,10 +34,7 @@ Dot11d_Reset(struct ieee80211_device *ieee)
{
u32 i;
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(ieee);
#if 0
if(!pDot11dInfo->bEnabled)
return;
#endif
// Clear old channel map
memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1);
memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1);
drivers/staging/rtl8192su/ieee80211/ieee80211.h
+2 -28
View File
@@ -2119,35 +2119,9 @@ struct ieee80211_device {
// void (*ps_request_tx_ack) (struct net_device *dev);
void (*enter_sleep_state) (struct net_device *dev, u32 th, u32 tl);
short (*ps_is_queue_empty) (struct net_device *dev);
#if 0
/* Typical STA methods */
int (*handle_auth) (struct net_device * dev,
struct ieee80211_auth * auth);
int (*handle_deauth) (struct net_device * dev,
struct ieee80211_deauth * auth);
int (*handle_action) (struct net_device * dev,
struct ieee80211_action * action,
struct ieee80211_rx_stats * stats);
int (*handle_disassoc) (struct net_device * dev,
struct ieee80211_disassoc * assoc);
#endif
int (*handle_beacon) (struct net_device * dev, struct ieee80211_beacon * beacon, struct ieee80211_network * network);
#if 0
int (*handle_probe_response) (struct net_device * dev,
struct ieee80211_probe_response * resp,
struct ieee80211_network * network);
int (*handle_probe_request) (struct net_device * dev,
struct ieee80211_probe_request * req,
struct ieee80211_rx_stats * stats);
#endif
int (*handle_assoc_response) (struct net_device * dev, struct ieee80211_assoc_response_frame * resp, struct ieee80211_network * network);
#if 0
/* Typical AP methods */
int (*handle_assoc_request) (struct net_device * dev);
int (*handle_reassoc_request) (struct net_device * dev,
struct ieee80211_reassoc_request * req);
#endif
int (*handle_beacon) (struct net_device * dev, struct ieee80211_beacon * beacon, struct ieee80211_network * network);
int (*handle_assoc_response) (struct net_device * dev, struct ieee80211_assoc_response_frame * resp, struct ieee80211_network * network);
/* check whether Tx hw resouce available */
short (*check_nic_enough_desc)(struct net_device *dev, int queue_index);
drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c
-12
View File
@@ -327,18 +327,6 @@ static int ieee80211_tkip_encrypt(struct sk_buff *skb, int hdr_len, void *priv)
hdr = (struct ieee80211_hdr_4addr *) skb->data;
#if 0
printk("@@ tkey\n");
printk("%x|", ((u32*)tkey->key)[0]);
printk("%x|", ((u32*)tkey->key)[1]);
printk("%x|", ((u32*)tkey->key)[2]);
printk("%x|", ((u32*)tkey->key)[3]);
printk("%x|", ((u32*)tkey->key)[4]);
printk("%x|", ((u32*)tkey->key)[5]);
printk("%x|", ((u32*)tkey->key)[6]);
printk("%x\n", ((u32*)tkey->key)[7]);
#endif
if (!tcb_desc->bHwSec)
{
if (!tkey->tx_phase1_done) {
drivers/staging/rtl8192su/ieee80211/ieee80211_module.c
+1 -12
View File
@@ -170,9 +170,7 @@ struct net_device *alloc_ieee80211(int sizeof_priv)
HTUpdateDefaultSetting(ieee);
HTInitializeHTInfo(ieee); //may move to other place.
TSInitialize(ieee);
#if 0
INIT_WORK(&ieee->ht_onAssRsp, (void(*)(void*)) HTOnAssocRsp_wq);
#endif
for (i = 0; i < IEEE_IBSS_MAC_HASH_SIZE; i++)
INIT_LIST_HEAD(&ieee->ibss_mac_hash[i]);
@@ -228,15 +226,6 @@ void free_ieee80211(struct net_device *dev)
}
ieee80211_networks_free(ieee);
#if 0
for (i = 0; i < IEEE_IBSS_MAC_HASH_SIZE; i++) {
list_for_each_safe(p, q, &ieee->ibss_mac_hash[i]) {
kfree(list_entry(p, struct ieee_ibss_seq, list));
list_del(p);
}
}
#endif
free_netdev(dev);
}
drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c
-94
View File
@@ -620,10 +620,6 @@ void RxReorderIndicatePacket( struct ieee80211_device *ieee,
u8 index = 0;
bool bMatchWinStart = false, bPktInBuf = false;
IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): Seq is %d,pTS->RxIndicateSeq is %d, WinSize is %d\n",__FUNCTION__,SeqNum,pTS->RxIndicateSeq,WinSize);
#if 0
if(!list_empty(&ieee->RxReorder_Unused_List))
IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): ieee->RxReorder_Unused_List is nut NULL\n");
#endif
/* Rx Reorder initialize condition.*/
if(pTS->RxIndicateSeq == 0xffff) {
pTS->RxIndicateSeq = SeqNum;
@@ -784,14 +780,7 @@ void RxReorderIndicatePacket( struct ieee80211_device *ieee,
// Set new pending timer.
IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): SET rx timeout timer\n", __FUNCTION__);
pTS->RxTimeoutIndicateSeq = pTS->RxIndicateSeq;
#if 0
if(timer_pending(&pTS->RxPktPendingTimer))
del_timer_sync(&pTS->RxPktPendingTimer);
pTS->RxPktPendingTimer.expires = jiffies + MSECS(pHTInfo->RxReorderPendingTime);
add_timer(&pTS->RxPktPendingTimer);
#else
mod_timer(&pTS->RxPktPendingTimer, jiffies + MSECS(pHTInfo->RxReorderPendingTime));
#endif
}
#endif
}
@@ -860,11 +849,6 @@ u8 parse_subframe(struct sk_buff *skb,
nSubframe_Length = (nSubframe_Length>>8) + (nSubframe_Length<<8);
if(skb->len<(ETHERNET_HEADER_SIZE + nSubframe_Length)) {
#if 0//cosa
RT_ASSERT(
(nRemain_Length>=(ETHERNET_HEADER_SIZE + nSubframe_Length)),
("ParseSubframe(): A-MSDU subframe parse error!! Subframe Length: %d\n", nSubframe_Length) );
#endif
printk("%s: A-MSDU parse error!! pRfd->nTotalSubframe : %d\n",\
__FUNCTION__,rxb->nr_subframes);
printk("%s: A-MSDU parse error!! Subframe Length: %d\n",__FUNCTION__, nSubframe_Length);
@@ -1058,17 +1042,6 @@ int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb,
else
{
PRX_TS_RECORD pRxTS = NULL;
#if 0
struct ieee80211_hdr_3addr *hdr;
u16 fc;
hdr = (struct ieee80211_hdr_3addr *)skb->data;
fc = le16_to_cpu(hdr->frame_ctl);
u8 tmp = (fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS);
u8 tid = (*((u8*)skb->data + (((fc& IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS))?30:24)))&0xf;
printk("====================>fc:%x, tid:%d, tmp:%d\n", fc, tid, tmp);
//u8 tid = (u8)((frameqos*)(buf + ((fc & IEEE80211_FCTL_TODS)&&(fc & IEEE80211_FCTL_FROMDS))? 30 : 24))->field.tid;
#endif
//IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): QOS ENABLE AND RECEIVE QOS DATA , we will get Ts, tid:%d\n",__FUNCTION__, tid);
#if 1
if(GetTs(
@@ -1102,20 +1075,6 @@ int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb,
#endif
if (type == IEEE80211_FTYPE_MGMT) {
#if 0
if ( stype == IEEE80211_STYPE_AUTH &&
fc & IEEE80211_FCTL_WEP && ieee->host_decrypt &&
(keyidx = hostap_rx_frame_decrypt(ieee, skb, crypt)) < 0)
{
printk(KERN_DEBUG "%s: failed to decrypt mgmt::auth "
"from " MAC_FMT "\n", dev->name,
MAC_ARG(hdr->addr2));
/* TODO: could inform hostapd about this so that it
* could send auth failure report */
goto rx_dropped;
}
#endif
//IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len);
if (ieee80211_rx_frame_mgmt(ieee, skb, rx_stats, type, stype))
goto rx_dropped;
@@ -1812,12 +1771,8 @@ int ieee80211_parse_info_param(struct ieee80211_device *ieee,
network->dtim_period = info_element->data[1];
if(ieee->state != IEEE80211_LINKED)
break;
#if 0
network->last_dtim_sta_time[0] = stats->mac_time[0];
#else
//we use jiffies for legacy Power save
network->last_dtim_sta_time[0] = jiffies;
#endif
network->last_dtim_sta_time[1] = stats->mac_time[1];
network->dtim_data = IEEE80211_DTIM_VALID;
@@ -1984,16 +1939,6 @@ int ieee80211_parse_info_param(struct ieee80211_device *ieee,
}
}
#if 0
if (tmp_htcap_len !=0)
{
u16 cap_ext = ((PHT_CAPABILITY_ELE)&info_element->data[0])->ExtHTCapInfo;
if ((cap_ext & 0x0c00) == 0x0c00)
{
network->ralink_cap_exist = true;
}
}
#endif
if(info_element->len >= 3 &&
info_element->data[0] == 0x00 &&
info_element->data[1] == 0x0c &&
@@ -2176,45 +2121,6 @@ int ieee80211_parse_info_param(struct ieee80211_device *ieee,
//printk("=====>Receive <%s> Country IE\n",network->ssid);
ieee80211_extract_country_ie(ieee, info_element, network, network->bssid);//addr2 is same as addr3 when from an AP
break;
/* TODO */
#if 0
/* 802.11h */
case MFIE_TYPE_POWER_CONSTRAINT:
network->power_constraint = info_element->data[0];
network->flags |= NETWORK_HAS_POWER_CONSTRAINT;
break;
case MFIE_TYPE_CSA:
network->power_constraint = info_element->data[0];
network->flags |= NETWORK_HAS_CSA;
break;
case MFIE_TYPE_QUIET:
network->quiet.count = info_element->data[0];
network->quiet.period = info_element->data[1];
network->quiet.duration = info_element->data[2];
network->quiet.offset = info_element->data[3];
network->flags |= NETWORK_HAS_QUIET;
break;
case MFIE_TYPE_IBSS_DFS:
if (network->ibss_dfs)
break;
network->ibss_dfs = kmemdup(info_element->data,
info_element->len,
GFP_ATOMIC);
if (!network->ibss_dfs)
return 1;
network->flags |= NETWORK_HAS_IBSS_DFS;
break;
case MFIE_TYPE_TPC_REPORT:
network->tpc_report.transmit_power =
info_element->data[0];
network->tpc_report.link_margin = info_element->data[1];
network->flags |= NETWORK_HAS_TPC_REPORT;
break;
#endif
default:
IEEE80211_DEBUG_MGMT
("Unsupported info element: %s (%d)\n",
drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c
+1 -84
View File
@@ -796,10 +796,7 @@ static struct sk_buff* ieee80211_probe_resp(struct ieee80211_device *ieee, u8 *d
cpu_to_le16((beacon_buf->capability |= WLAN_CAPABILITY_SHORT_SLOT));
crypt = ieee->crypt[ieee->tx_keyidx];
#if 0
encrypt = ieee->host_encrypt && crypt && crypt->ops &&
(0 == strcmp(crypt->ops->name, "WEP"));
#endif
if (encrypt)
beacon_buf->capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY);
@@ -838,14 +835,7 @@ static struct sk_buff* ieee80211_probe_resp(struct ieee80211_device *ieee, u8 *d
*(tag++) = 1;
*(tag++) = erpinfo_content;
}
#if 0
//Include High Throuput capability
*(tag++) = MFIE_TYPE_HT_CAP;
*(tag++) = tmp_ht_cap_len - 2;
memcpy(tag, tmp_ht_cap_buf, tmp_ht_cap_len - 2);
tag += tmp_ht_cap_len - 2;
#endif
if(rate_ex_len){
*(tag++) = MFIE_TYPE_RATES_EX;
*(tag++) = rate_ex_len-2;
@@ -853,14 +843,6 @@ static struct sk_buff* ieee80211_probe_resp(struct ieee80211_device *ieee, u8 *d
tag+=rate_ex_len-2;
}
#if 0
//Include High Throuput info
*(tag++) = MFIE_TYPE_HT_INFO;
*(tag++) = tmp_ht_info_len - 2;
memcpy(tag, tmp_ht_info_buf, tmp_ht_info_len -2);
tag += tmp_ht_info_len - 2;
#endif
if (wpa_ie_len)
{
if (ieee->iw_mode == IW_MODE_ADHOC)
@@ -871,28 +853,6 @@ static struct sk_buff* ieee80211_probe_resp(struct ieee80211_device *ieee, u8 *d
tag += wpa_ie_len;
}
#if 0
//
// Construct Realtek Proprietary Aggregation mode (Set AMPDU Factor to 2, 32k)
//
if(pHTInfo->bRegRT2RTAggregation)
{
(*tag++) = 0xdd;
(*tag++) = tmp_generic_ie_len - 2;
memcpy(tag,tmp_generic_ie_buf,tmp_generic_ie_len -2);
tag += tmp_generic_ie_len -2;
}
#endif
#if 0
if(ieee->qos_support)
{
(*tag++) = 0xdd;
(*tag++) = wmm_len;
memcpy(tag,QosOui,wmm_len);
tag += wmm_len;
}
#endif
//skb->dev = ieee->dev;
return skb;
}
@@ -1346,10 +1306,6 @@ void ieee80211_auth_challenge(struct ieee80211_device *ieee, u8 *challenge, int
softmac_mgmt_xmit(skb, ieee);
mod_timer(&ieee->associate_timer, jiffies + (HZ/2));
#if 0
ieee->associate_timer.expires = jiffies + (HZ / 2);
add_timer(&ieee->associate_timer);
#endif
//dev_kfree_skb_any(skb);//edit by thomas
}
kfree(challenge);
@@ -1371,10 +1327,6 @@ void ieee80211_associate_step2(struct ieee80211_device *ieee)
else{
softmac_mgmt_xmit(skb, ieee);
mod_timer(&ieee->associate_timer, jiffies + (HZ/2));
#if 0
ieee->associate_timer.expires = jiffies + (HZ / 2);
add_timer(&ieee->associate_timer);
#endif
//dev_kfree_skb_any(skb);//edit by thomas
}
}
@@ -1434,25 +1386,7 @@ void ieee80211_associate_complete(struct ieee80211_device *ieee)
// struct net_device* dev = ieee->dev;
del_timer_sync(&ieee->associate_timer);
#if 0
for(i = 0; i < 6; i++) {
ieee->seq_ctrl[i] = 0;
}
#endif
ieee->state = IEEE80211_LINKED;
#if 0
if (ieee->pHTInfo->bCurrentHTSupport)
{
printk("Successfully associated, ht enabled\n");
queue_work(ieee->wq, &ieee->ht_onAssRsp);
}
else
{
printk("Successfully associated, ht not enabled\n");
memset(ieee->dot11HTOperationalRateSet, 0, 16);
HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT);
}
#endif
//ieee->UpdateHalRATRTableHandler(dev, ieee->dot11HTOperationalRateSet);
queue_work(ieee->wq, &ieee->associate_complete_wq);
}
@@ -1777,11 +1711,6 @@ ieee80211_rx_assoc_rq(struct ieee80211_device *ieee, struct sk_buff *skb)
printk(KERN_INFO"New client associated: "MAC_FMT"\n", MAC_ARG(dest));
//FIXME
#if 0
spin_lock_irqsave(&ieee->lock,flags);
add_associate(ieee,dest);
spin_unlock_irqrestore(&ieee->lock,flags);
#endif
}
@@ -2010,18 +1939,6 @@ ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb,
if(!ieee->proto_started)
return 0;
#if 0
printk("%d, %d, %d, %d\n", ieee->sta_sleep, ieee->ps, ieee->iw_mode, ieee->state);
if(ieee->sta_sleep || (ieee->ps != IEEE80211_PS_DISABLED &&
ieee->iw_mode == IW_MODE_INFRA &&
ieee->state == IEEE80211_LINKED))
tasklet_schedule(&ieee->ps_task);
if(WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_PROBE_RESP &&
WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_BEACON)
ieee->last_rx_ps_time = jiffies;
#endif
switch (WLAN_FC_GET_STYPE(header->frame_ctl)) {
drivers/staging/rtl8192su/ieee80211/ieee80211_softmac_wx.c
-8
View File
@@ -436,14 +436,6 @@ int ieee80211_wx_set_essid(struct ieee80211_device *ieee,
len = ((wrqu->essid.length-1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length-1) : IW_ESSID_MAX_SIZE;
strncpy(ieee->current_network.ssid, extra, len+1);
ieee->current_network.ssid_len = len+1;
#if 0
{
int i;
for (i=0; i<len + 1; i++)
printk("%c ", extra[i]);
printk("\n");
}
#endif
ieee->ssid_set = 1;
}
else{
drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c
-5
View File
@@ -235,11 +235,6 @@ void ieee80211_txb_free(struct ieee80211_txb *txb) {
//int i;
if (unlikely(!txb))
return;
#if 0
for (i = 0; i < txb->nr_frags; i++)
if (txb->fragments[i])
dev_kfree_skb_any(txb->fragments[i]);
#endif
kfree(txb);
}
drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c
+4 -38
View File
@@ -35,11 +35,7 @@
#include <linux/module.h>
#include "ieee80211.h"
#if 0
static const char *ieee80211_modes[] = {
"?", "a", "b", "ab", "g", "ag", "bg", "abg"
};
#endif
struct modes_unit {
char *mode_string;
int mode_size;
@@ -170,15 +166,7 @@ static inline char *rtl819x_translate_scan(struct ieee80211_device *ieee,
if (rate > max_rate)
max_rate = rate;
}
#if 0
printk("max rate:%d ===basic rate:\n", max_rate);
for (i=0;i<network->rates_len;i++)
printk(" %x", network->rates[i]);
printk("\n=======extend rate\n");
for (i=0; i<network->rates_ex_len; i++)
printk(" %x", network->rates_ex[i]);
printk("\n");
#endif
iwe.cmd = SIOCGIWRATE;
iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0;
iwe.u.bitrate.value = max_rate * 500000;
@@ -495,15 +483,7 @@ int ieee80211_wx_get_encode(struct ieee80211_device *ieee,
erq->flags |= IW_ENCODE_DISABLED;
return 0;
}
#if 0
if (strcmp(crypt->ops->name, "WEP") != 0) {
/* only WEP is supported with wireless extensions, so just
* report that encryption is used */
erq->length = 0;
erq->flags |= IW_ENCODE_ENABLED;
return 0;
}
#endif
len = crypt->ops->get_key(keybuf, SCM_KEY_LEN, NULL, crypt->priv);
erq->length = (len >= 0 ? len : 0);
@@ -585,12 +565,7 @@ int ieee80211_wx_set_encode_ext(struct ieee80211_device *ieee,
sec.enabled = 1;
// sec.encrypt = 1;
#if 0
if (group_key ? !ieee->host_mc_decrypt :
!(ieee->host_encrypt || ieee->host_decrypt ||
ieee->host_encrypt_msdu))
goto skip_host_crypt;
#endif
switch (ext->alg) {
case IW_ENCODE_ALG_WEP:
alg = "WEP";
@@ -841,15 +816,6 @@ int ieee80211_wx_set_auth(struct ieee80211_device *ieee,
#if 1
int ieee80211_wx_set_gen_ie(struct ieee80211_device *ieee, u8 *ie, size_t len)
{
#if 0
printk("====>%s()\n", __FUNCTION__);
{
int i;
for (i=0; i<len; i++)
printk("%2x ", ie[i]&0xff);
printk("\n");
}
#endif
u8 *buf;
if (len>MAX_WPA_IE_LEN || (len && ie == NULL))
drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c
-43
View File
@@ -174,49 +174,6 @@ static struct sk_buff* ieee80211_ADDBA(struct ieee80211_device* ieee, u8* Dst, P
//return NULL;
}
#if 0 //I try to merge ADDBA_REQ and ADDBA_RSP frames together..
/********************************************************************************************************************
*function: construct ADDBAREQ frame
* input: u8* dst //ADDBARsp frame's destination
* PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA_RSP.
* u16 StatusCode //status code.
* output: none
* return: sk_buff* skb //return constructed skb to xmit
********************************************************************************************************************/
static struct sk_buff* ieee80211_ADDBA_Rsp( IN struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA, u16 StatusCode)
{
OCTET_STRING osADDBAFrame, tmp;
FillOctetString(osADDBAFrame, Buffer, 0);
*pLength = 0;
ConstructMaFrameHdr(
Adapter,
Addr,
ACT_CAT_BA,
ACT_ADDBARSP,
&osADDBAFrame );
// Dialog Token
FillOctetString(tmp, &pBA->DialogToken, 1);
PacketAppendData(&osADDBAFrame, tmp);
// Status Code
FillOctetString(tmp, &StatusCode, 2);
PacketAppendData(&osADDBAFrame, tmp);
// BA Parameter Set
FillOctetString(tmp, &pBA->BaParamSet, 2);
PacketAppendData(&osADDBAFrame, tmp);
// BA Timeout Value
FillOctetString(tmp, &pBA->BaTimeoutValue, 2);
PacketAppendData(&osADDBAFrame, tmp);
*pLength = osADDBAFrame.Length;
}
#endif
/********************************************************************************************************************
*function: construct DELBA frame
* input: u8* dst //DELBA frame's destination
drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c
+2 -224
View File
@@ -340,11 +340,7 @@ bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee)
{
bool retValue = false;
struct ieee80211_network* net = &ieee->current_network;
#if 0
if(pMgntInfo->bHalfNMode == false)
retValue = false;
else
#endif
if((memcmp(net->bssid, BELKINF5D8233V1_RALINK, 3)==0) ||
(memcmp(net->bssid, BELKINF5D82334V3_RALINK, 3)==0) ||
(memcmp(net->bssid, PCI_RALINK, 3)==0) ||
@@ -423,24 +419,7 @@ void HTIOTPeerDetermine(struct ieee80211_device* ieee)
u8 HTIOTActIsDisableMCS14(struct ieee80211_device* ieee, u8* PeerMacAddr)
{
u8 ret = 0;
#if 0
// Apply for 819u only
#if (HAL_CODE_BASE==RTL8192 && DEV_BUS_TYPE==USB_INTERFACE)
if((memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0) ||
(memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)
)
{
ret = 1;
}
if(pHTInfo->bCurrentRT2RTAggregation)
{
// The parameter of pHTInfo->bCurrentRT2RTAggregation must be decided previously
ret = 1;
}
#endif
#endif
return ret;
}
@@ -541,18 +520,6 @@ u8 HTIOTActIsDisableEDCATurbo(struct ieee80211_device* ieee, u8* PeerMacAddr)
// Set specific EDCA parameter for different AP in DM handler.
return retValue;
#if 0
if((memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0)||
(memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)||
(memcmp(PeerMacAddr, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)||
(memcmp(PeerMacAddr, NETGEAR834Bv2_BROADCOM, 3)==0))
{
retValue = 1; //Linksys disable EDCA turbo mode
}
return retValue;
#endif
}
/********************************************************************************************************************
@@ -1203,12 +1170,7 @@ u8 HTFilterMCSRate( struct ieee80211_device* ieee, u8* pSupportMCS, u8* pOperate
return true;
}
void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
#if 0
//I need move this function to other places, such as rx?
void HTOnAssocRsp_wq(struct work_struct *work)
{
struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, ht_onAssRsp);
#endif
void HTOnAssocRsp(struct ieee80211_device *ieee)
{
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
@@ -1315,10 +1277,6 @@ void HTOnAssocRsp(struct ieee80211_device *ieee)
{
// Set MPDU density to 2 to Realtek AP, and set it to 0 for others
// Replace MPDU factor declared in original association response frame format. 2007.08.20 by Emily
#if 0
osTmp= PacketGetElement( asocpdu, EID_Vendor, OUI_SUB_REALTEK_AGG, OUI_SUBTYPE_DONT_CARE);
if(osTmp.Length >= 5) //00:e0:4c:02:00
#endif
if (ieee->current_network.bssht.bdRT2RTAggregation)
{
if( ieee->pairwise_key_type != KEY_TYPE_NA)
@@ -1498,187 +1456,7 @@ void HTInitializeBssDesc(PBSS_HT pBssHT)
pBssHT->bdRT2RTLongSlotTime = false;
pBssHT->RT2RT_HT_Mode = (RT_HT_CAPBILITY)0;
}
#if 0
//below function has merged into ieee80211_network_init() in ieee80211_rx.c
void
HTParsingHTCapElement(
IN PADAPTER Adapter,
IN OCTET_STRING HTCapIE,
OUT PRT_WLAN_BSS pBssDesc
)
{
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
if( HTCapIE.Length > sizeof(pBssDesc->BssHT.bdHTCapBuf) )
{
RT_TRACE( COMP_HT, DBG_LOUD, ("HTParsingHTCapElement(): HT Capability Element length is too long!\n") );
return;
}
// TODO: Check the correctness of HT Cap
//Print each field in detail. Driver should not print out this message by default
if(!pMgntInfo->mActingAsAp && !pMgntInfo->mAssoc)
HTDebugHTCapability(DBG_TRACE, Adapter, &HTCapIE, (pu8)"HTParsingHTCapElement()");
HTCapIE.Length = HTCapIE.Length > sizeof(pBssDesc->BssHT.bdHTCapBuf)?\
sizeof(pBssDesc->BssHT.bdHTCapBuf):HTCapIE.Length; //prevent from overflow
CopyMem(pBssDesc->BssHT.bdHTCapBuf, HTCapIE.Octet, HTCapIE.Length);
pBssDesc->BssHT.bdHTCapLen = HTCapIE.Length;
}
void
HTParsingHTInfoElement(
PADAPTER Adapter,
OCTET_STRING HTInfoIE,
PRT_WLAN_BSS pBssDesc
)
{
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
if( HTInfoIE.Length > sizeof(pBssDesc->BssHT.bdHTInfoBuf))
{
RT_TRACE( COMP_HT, DBG_LOUD, ("HTParsingHTInfoElement(): HT Information Element length is too long!\n") );
return;
}
// TODO: Check the correctness of HT Info
//Print each field in detail. Driver should not print out this message by default
if(!pMgntInfo->mActingAsAp && !pMgntInfo->mAssoc)
HTDebugHTInfo(DBG_TRACE, Adapter, &HTInfoIE, (pu8)"HTParsingHTInfoElement()");
HTInfoIE.Length = HTInfoIE.Length > sizeof(pBssDesc->BssHT.bdHTInfoBuf)?\
sizeof(pBssDesc->BssHT.bdHTInfoBuf):HTInfoIE.Length; //prevent from overflow
CopyMem( pBssDesc->BssHT.bdHTInfoBuf, HTInfoIE.Octet, HTInfoIE.Length);
pBssDesc->BssHT.bdHTInfoLen = HTInfoIE.Length;
}
/*
* Get HT related information from beacon and save it in BssDesc
*
* (1) Parse HTCap, and HTInfo, and record whether it is 11n AP
* (2) If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT()
* (3) Check whether peer is Realtek AP (for Realtek proprietary aggregation mode).
* Input:
* PADAPTER Adapter
*
* Output:
* PRT_TCB BssDesc
*
*/
void HTGetValueFromBeaconOrProbeRsp(
PADAPTER Adapter,
POCTET_STRING pSRCmmpdu,
PRT_WLAN_BSS bssDesc
)
{
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);
OCTET_STRING HTCapIE, HTInfoIE, HTRealtekAgg, mmpdu;
OCTET_STRING BroadcomElement, CiscoElement;
mmpdu.Octet = pSRCmmpdu->Octet;
mmpdu.Length = pSRCmmpdu->Length;
//2Note:
// Mark for IOT testing using Linksys WRT350N, This AP does not contain WMM IE when
// it is configured at pure-N mode.
// if(bssDesc->BssQos.bdQoSMode & QOS_WMM)
//
HTInitializeBssDesc (&bssDesc->BssHT);
//2<1> Parse HTCap, and HTInfo
// Get HT Capability IE: (1) Get IEEE Draft N IE or (2) Get EWC IE
HTCapIE = PacketGetElement(mmpdu, EID_HTCapability, OUI_SUB_DONT_CARE, OUI_SUBTYPE_DONT_CARE);
if(HTCapIE.Length == 0)
{
HTCapIE = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_11N_EWC_HT_CAP, OUI_SUBTYPE_DONT_CARE);
if(HTCapIE.Length != 0)
bssDesc->BssHT.bdHTSpecVer= HT_SPEC_VER_EWC;
}
if(HTCapIE.Length != 0)
HTParsingHTCapElement(Adapter, HTCapIE, bssDesc);
// Get HT Information IE: (1) Get IEEE Draft N IE or (2) Get EWC IE
HTInfoIE = PacketGetElement(mmpdu, EID_HTInfo, OUI_SUB_DONT_CARE, OUI_SUBTYPE_DONT_CARE);
if(HTInfoIE.Length == 0)
{
HTInfoIE = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_11N_EWC_HT_INFO, OUI_SUBTYPE_DONT_CARE);
if(HTInfoIE.Length != 0)
bssDesc->BssHT.bdHTSpecVer = HT_SPEC_VER_EWC;
}
if(HTInfoIE.Length != 0)
HTParsingHTInfoElement(Adapter, HTInfoIE, bssDesc);
//2<2>If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT()
if(HTCapIE.Length != 0)
{
bssDesc->BssHT.bdSupportHT = true;
if(bssDesc->BssQos.bdQoSMode == QOS_DISABLE)
QosSetLegacyWMMParamWithHT(Adapter, bssDesc);
}
else
{
bssDesc->BssHT.bdSupportHT = false;
}
//2<3>Check whether the peer is Realtek AP/STA
if(pHTInfo->bRegRT2RTAggregation)
{
if(bssDesc->BssHT.bdSupportHT)
{
HTRealtekAgg = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_REALTEK_AGG, OUI_SUBTYPE_DONT_CARE);
if(HTRealtekAgg.Length >=5 )
{
bssDesc->BssHT.bdRT2RTAggregation = true;
if((HTRealtekAgg.Octet[4]==1) && (HTRealtekAgg.Octet[5] & 0x02))
bssDesc->BssHT.bdRT2RTLongSlotTime = true;
}
}
}
//
// 2008/01/25 MH Get Broadcom AP IE for manamgent frame CCK rate problem.
// AP can not receive CCK managemtn from from 92E.
//
// Initialize every new bss broadcom cap exist as false..
bssDesc->bBroadcomCapExist= false;
if(HTCapIE.Length != 0 || HTInfoIE.Length != 0)
{
u4Byte Length = 0;
FillOctetString(BroadcomElement, NULL, 0);
BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_1, OUI_SUBTYPE_DONT_CARE);
Length += BroadcomElement.Length;
BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_2, OUI_SUBTYPE_DONT_CARE);
Length += BroadcomElement.Length;
BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_3, OUI_SUBTYPE_DONT_CARE);
Length += BroadcomElement.Length;
if(Length > 0)
bssDesc->bBroadcomCapExist = true;
}
// For Cisco IOT issue
CiscoElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_CISCO_IE, OUI_SUBTYPE_DONT_CARE);
if(CiscoElement.Length != 0){ // 3: 0x00, 0x40, 0x96 ....
bssDesc->bCiscoCapExist = true;
}else{
bssDesc->bCiscoCapExist = false;
}
}
#endif
/********************************************************************************************************************
*function: initialize Bss HT structure(struct PBSS_HT)
* input: struct ieee80211_device *ieee
drivers/staging/rtl8192su/ieee80211/rtl819x_Qos.h
-166
View File
@@ -70,147 +70,6 @@ typedef enum _ACK_POLICY{
}ACK_POLICY,*PACK_POLICY;
#define WMM_PARAM_ELEMENT_SIZE (8+(4*AC_PARAM_SIZE))
#if 0
#define GET_QOS_CTRL(_pStart) ReadEF2Byte((u8 *)(_pStart) + 24)
#define SET_QOS_CTRL(_pStart, _value) WriteEF2Byte((u8 *)(_pStart) + 24, _value)
// WMM control field.
#define GET_QOS_CTRL_WMM_UP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 3))
#define SET_QOS_CTRL_WMM_UP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 3, (u8)(_value))
#define GET_QOS_CTRL_WMM_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1))
#define SET_QOS_CTRL_WMM_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value))
#define GET_QOS_CTRL_WMM_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2))
#define SET_QOS_CTRL_WMM_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value))
// 802.11e control field (by STA, data)
#define GET_QOS_CTRL_STA_DATA_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4))
#define SET_QOS_CTRL_STA_DATA_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value))
#define GET_QOS_CTRL_STA_DATA_QSIZE_FLAG(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1))
#define SET_QOS_CTRL_STA_DATA_QSIZE_FLAG(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value))
#define GET_QOS_CTRL_STA_DATA_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2))
#define SET_QOS_CTRL_STA_DATA_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value))
#define GET_QOS_CTRL_STA_DATA_TXOP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8))
#define SET_QOS_CTRL_STA_DATA_TXOP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value))
#define GET_QOS_CTRL_STA_DATA_QSIZE(_pStart) GET_QOS_CTRL_STA_DATA_TXOP(_pStart)
#define SET_QOS_CTRL_STA_DATA_QSIZE(_pStart, _value) SET_QOS_CTRL_STA_DATA_TXOP(_pStart)
// 802.11e control field (by HC, data)
#define GET_QOS_CTRL_HC_DATA_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4))
#define SET_QOS_CTRL_HC_DATA_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value))
#define GET_QOS_CTRL_HC_DATA_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1))
#define SET_QOS_CTRL_HC_DATA_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value))
#define GET_QOS_CTRL_HC_DATA_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2))
#define SET_QOS_CTRL_HC_DATA_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value))
#define GET_QOS_CTRL_HC_DATA_PS_BUFSTATE(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8))
#define SET_QOS_CTRL_HC_DATA_PS_BUFSTATE(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value))
// 802.11e control field (by HC, CFP)
#define GET_QOS_CTRL_HC_CFP_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4))
#define SET_QOS_CTRL_HC_CFP_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value))
#define GET_QOS_CTRL_HC_CFP_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1))
#define SET_QOS_CTRL_HC_CFP_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value))
#define GET_QOS_CTRL_HC_CFP_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2))
#define SET_QOS_CTRL_HC_CFP_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value))
#define GET_QOS_CTRL_HC_CFP_TXOP_LIMIT(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8))
#define SET_QOS_CTRL_HC_CFP_TXOP_LIMIT(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value))
#define SET_WMM_QOS_INFO_FIELD(_pStart, _val) WriteEF1Byte(_pStart, _val)
#define GET_WMM_QOS_INFO_FIELD_PARAMETERSET_COUNT(_pStart) LE_BITS_TO_1BYTE(_pStart, 0, 4)
#define SET_WMM_QOS_INFO_FIELD_PARAMETERSET_COUNT(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 0, 4, _val)
#define GET_WMM_QOS_INFO_FIELD_AP_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 7, 1)
#define SET_WMM_QOS_INFO_FIELD_AP_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 7, 1, _val)
#define GET_WMM_QOS_INFO_FIELD_STA_AC_VO_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 0, 1)
#define SET_WMM_QOS_INFO_FIELD_STA_AC_VO_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 0, 1, _val)
#define GET_WMM_QOS_INFO_FIELD_STA_AC_VI_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 1, 1)
#define SET_WMM_QOS_INFO_FIELD_STA_AC_VI_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 1, 1, _val)
#define GET_WMM_QOS_INFO_FIELD_STA_AC_BE_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 2, 1)
#define SET_WMM_QOS_INFO_FIELD_STA_AC_BE_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 2, 1, _val)
#define GET_WMM_QOS_INFO_FIELD_STA_AC_BK_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 3, 1)
#define SET_WMM_QOS_INFO_FIELD_STA_AC_BK_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 3, 1, _val)
#define GET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart) LE_BITS_TO_1BYTE(_pStart, 5, 2)
#define SET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 5, 2, _val)
#define WMM_INFO_ELEMENT_SIZE 7
#define GET_WMM_INFO_ELE_OUI(_pStart) ((u8 *)(_pStart))
#define SET_WMM_INFO_ELE_OUI(_pStart, _pVal) PlatformMoveMemory(_pStart, _pVal, 3);
#define GET_WMM_INFO_ELE_OUI_TYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+3) ) )
#define SET_WMM_INFO_ELE_OUI_TYPE(_pStart, _val) ( *((u8 *)(_pStart)+3) = EF1Byte(_val) )
#define GET_WMM_INFO_ELE_OUI_SUBTYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+4) ) )
#define SET_WMM_INFO_ELE_OUI_SUBTYPE(_pStart, _val) ( *((u8 *)(_pStart)+4) = EF1Byte(_val) )
#define GET_WMM_INFO_ELE_VERSION(_pStart) ( EF1Byte( *((u8 *)(_pStart)+5) ) )
#define SET_WMM_INFO_ELE_VERSION(_pStart, _val) ( *((u8 *)(_pStart)+5) = EF1Byte(_val) )
#define GET_WMM_INFO_ELE_QOS_INFO_FIELD(_pStart) ( EF1Byte( *((u8 *)(_pStart)+6) ) )
#define SET_WMM_INFO_ELE_QOS_INFO_FIELD(_pStart, _val) ( *((u8 *)(_pStart)+6) = EF1Byte(_val) )
#define GET_WMM_AC_PARAM_AIFSN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 0, 4) )
#define SET_WMM_AC_PARAM_AIFSN(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 0, 4, _val)
#define GET_WMM_AC_PARAM_ACM(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 4, 1) )
#define SET_WMM_AC_PARAM_ACM(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 4, 1, _val)
#define GET_WMM_AC_PARAM_ACI(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 5, 2) )
#define SET_WMM_AC_PARAM_ACI(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 5, 2, _val)
#define GET_WMM_AC_PARAM_ACI_AIFSN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 0, 8) )
#define SET_WMM_AC_PARAM_ACI_AIFSN(_pStart, _val) SET_BTIS_TO_LE_4BYTE(_pStart, 0, 8, _val)
#define GET_WMM_AC_PARAM_ECWMIN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 8, 4) )
#define SET_WMM_AC_PARAM_ECWMIN(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 8, 4, _val)
#define GET_WMM_AC_PARAM_ECWMAX(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 12, 4) )
#define SET_WMM_AC_PARAM_ECWMAX(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 12, 4, _val)
#define GET_WMM_AC_PARAM_TXOP_LIMIT(_pStart) ( (u16)LE_BITS_TO_4BYTE(_pStart, 16, 16) )
#define SET_WMM_AC_PARAM_TXOP_LIMIT(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 16, 16, _val)
#define GET_WMM_PARAM_ELE_OUI(_pStart) ((u8 *)(_pStart))
#define SET_WMM_PARAM_ELE_OUI(_pStart, _pVal) PlatformMoveMemory(_pStart, _pVal, 3)
#define GET_WMM_PARAM_ELE_OUI_TYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+3) ) )
#define SET_WMM_PARAM_ELE_OUI_TYPE(_pStart, _val) ( *((u8 *)(_pStart)+3) = EF1Byte(_val) )
#define GET_WMM_PARAM_ELE_OUI_SUBTYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+4) ) )
#define SET_WMM_PARAM_ELE_OUI_SUBTYPE(_pStart, _val) ( *((u8 *)(_pStart)+4) = EF1Byte(_val) )
#define GET_WMM_PARAM_ELE_VERSION(_pStart) ( EF1Byte( *((u8 *)(_pStart)+5) ) )
#define SET_WMM_PARAM_ELE_VERSION(_pStart, _val) ( *((u8 *)(_pStart)+5) = EF1Byte(_val) )
#define GET_WMM_PARAM_ELE_QOS_INFO_FIELD(_pStart) ( EF1Byte( *((u8 *)(_pStart)+6) ) )
#define SET_WMM_PARAM_ELE_QOS_INFO_FIELD(_pStart, _val) ( *((u8 *)(_pStart)+6) = EF1Byte(_val) )
#define GET_WMM_PARAM_ELE_AC_PARAM(_pStart) ( (u8 *)(_pStart)+8 )
#define SET_WMM_PARAM_ELE_AC_PARAM(_pStart, _pVal) PlatformMoveMemory((_pStart)+8, _pVal, 16)
#endif
//
// QoS Control Field
@@ -361,22 +220,6 @@ typedef union _QOS_INFO_FIELD{
}QOS_INFO_FIELD, *PQOS_INFO_FIELD;
#if 0
//
// WMM Information Element
// Ref: WMM spec 2.2.1: WME Information Element, p.10.
//
typedef struct _WMM_INFO_ELEMENT{
// u8 ElementID;
// u8 Length;
u8 OUI[3];
u8 OUI_Type;
u8 OUI_SubType;
u8 Version;
QOS_INFO_FIELD QosInfo;
}WMM_INFO_ELEMENT, *PWMM_INFO_ELEMENT;
#endif
//
// ACI to AC coding.
// Ref: WMM spec 2.2.2: WME Parameter Element, p.13.
@@ -650,16 +493,7 @@ typedef struct _OCTET_STRING{
u8 *Octet;
u16 Length;
}OCTET_STRING, *POCTET_STRING;
#if 0
#define FillOctetString(_os,_octet,_len) \
(_os).Octet=(u8 *)(_octet); \
(_os).Length=(_len);
#define WMM_ELEM_HDR_LEN 6
#define WMMElemSkipHdr(_osWMMElem) \
(_osWMMElem).Octet += WMM_ELEM_HDR_LEN; \
(_osWMMElem).Length -= WMM_ELEM_HDR_LEN;
#endif
//
// STA QoS data.
// Ref: DOT11_QOS in 8185 code. [def. in QoS_mp.h]
drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c
+1 -21
View File
@@ -89,21 +89,7 @@ void RxPktPendingTimeout(unsigned long data)
if(bPktInBuf && (pRxTs->RxTimeoutIndicateSeq==0xffff))
{
pRxTs->RxTimeoutIndicateSeq = pRxTs->RxIndicateSeq;
#if 0
if(timer_pending(&pTS->RxPktPendingTimer))
del_timer_sync(&pTS->RxPktPendingTimer);
pTS->RxPktPendingTimer.expires = jiffies + MSECS(pHTInfo->RxReorderPendingTime);
add_timer(&pTS->RxPktPendingTimer);
#else
mod_timer(&pRxTs->RxPktPendingTimer, jiffies + MSECS(ieee->pHTInfo->RxReorderPendingTime));
#endif
#if 0
if(timer_pending(&pRxTs->RxPktPendingTimer))
del_timer_sync(&pRxTs->RxPktPendingTimer);
pRxTs->RxPktPendingTimer.expires = jiffies + ieee->pHTInfo->RxReorderPendingTime;
add_timer(&pRxTs->RxPktPendingTimer);
#endif
}
spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags);
//PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
@@ -372,17 +358,11 @@ bool GetTs(
IEEE80211_DEBUG(IEEE80211_DL_ERR, "get TS for Broadcast or Multicast\n");
return false;
}
#if 0
if(ieee->pStaQos->CurrentQosMode == QOS_DISABLE)
{ UP = 0; } //only use one TS
else if(ieee->pStaQos->CurrentQosMode & QOS_WMM)
{
#else
if (ieee->current_network.qos_data.supported == 0)
UP = 0;
else
{
#endif
// In WMM case: we use 4 TID only
if (!IsACValid(TID))
{
drivers/staging/rtl8192su/r8192S_Efuse.c
-84
View File
@@ -188,10 +188,6 @@ static u16
efuse_GetCurrentSize(struct net_device* dev);
static u8
efuse_CalculateWordCnts(u8 word_en);
#if 0
static void
efuse_ResetLoader(struct net_device* dev);
#endif
//
// API for power on power off!!!
//
@@ -1020,49 +1016,6 @@ efuse_ReadAllMap(struct net_device* dev, u8 *Efuse)
efuse_PowerSwitch(dev, TRUE);
ReadEFuse(dev, 0, 128, Efuse);
efuse_PowerSwitch(dev, FALSE);
#if 0
// ==> Prevent efuse read error!!!
RT_TRACE(COMP_INIT, "efuse_ResetLoader\n");
efuse_ResetLoader(dev);
// Change Efuse Clock for write action to 40MHZ
write_nic_byte(dev, EFUSE_CLK, 0x03);
ReadEFuse(dev, 0, 128, Efuse);
// Change Efuse Clock for write action to 500K
write_nic_byte(dev, EFUSE_CLK, 0x02);
#if 0 // Error !!!!!!
for(offset = 0;offset<16;offset++) // For 8192SE
{
PlatformFillMemory((PVOID)pg_data, 8, 0xff);
efuse_PgPacketRead(pAdapter,offset,pg_data);
PlatformMoveMemory((PVOID)&Efuse[offset*8], (PVOID)pg_data, 8);
}
#endif
//
// Error Check and Reset Again!!!!
//
if (Efuse[0] != 0x29 || Efuse[1] != 0x81)
{
// SW autoload fail, we have to read again!!!
if (index ++ < 5)
{
RT_TRACE(COMP_INIT, "EFUSE R FAIL %d\n", index);
efuse_ReadAllMap(dev, Efuse);
// Wait a few time ???? Or need to do some setting ???
// When we reload driver, efuse will be OK!!
}
}
else
{
index = 0;
}
//efuse_PowerSwitch(pAdapter, FALSE);
#endif
} // efuse_ReadAllMap
@@ -1772,43 +1725,6 @@ efuse_CalculateWordCnts(u8 word_en)
return word_cnts;
} // efuse_CalculateWordCnts
/*-----------------------------------------------------------------------------
* Function: efuse_ResetLoader
*
* Overview: When read Efuse Fail we must reset loader!!!!
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/22/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
#if 0
static void efuse_ResetLoader(struct net_device* dev)
{
u16 tmpU2b;
//
// 2008/11/22 MH Sometimes, we may read efuse fail, for preventing the condition
// We have to reset loader.
//
tmpU2b = read_nic_word(dev, SYS_FUNC_EN);
write_nic_word(dev, SYS_FUNC_EN, (tmpU2b&~(BIT12)));
//PlatformStallExecution(10000); // How long should we delay!!!
mdelay(10);
write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|BIT12));
//PlatformStallExecution(10000); // How long should we delay!!!
mdelay(10);
} // efuse_ResetLoader
#endif
/*-----------------------------------------------------------------------------
* Function: EFUSE_ProgramMap
*
drivers/staging/rtl8192su/r8192S_hw.h
-55
View File
@@ -62,16 +62,6 @@ typedef enum _BaseBand_Config_Type{
BaseBand_Config_AGC_TAB = 1, //Radio Path B
}BaseBand_Config_Type, *PBaseBand_Config_Type;
#if 0
typedef enum _RT_RF_TYPE_819xU{
RF_TYPE_MIN = 0,
RF_8225,
RF_8256,
RF_8258,
RF_PSEUDO_11N = 4,
}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
#endif
#define RTL8187_REQT_READ 0xc0
#define RTL8187_REQT_WRITE 0x40
#define RTL8187_REQ_GET_REGS 0x05
@@ -1303,51 +1293,6 @@ Default: 00b.
#define FW_DM_DISABLE 0xfd00aa00
#define FW_BB_RESET_ENABLE 0xff00000d
#define FW_BB_RESET_DISABLE 0xff00000e
#if 0
//----------------------------------------------------------------------------
// 8190 EEROM
//----------------------------------------------------------------------------
#define RTL8190_EEPROM_ID 0x8129
//#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
#define EEPROM_RFInd_PowerDiff 0x28
#define EEPROM_ThermalMeter 0x29
#define EEPROM_TxPwDiff_CrystalCap 0x2A //0x2A~0x2B
#define EEPROM_TxPwIndex_CCK 0x2C //0x2C~0x39
#define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x3A~0x47
#define EEPROM_TxPwIndex_OFDM_5G 0x34 //0x34~0x7B
//The following definition is for eeprom 93c56......modified 20080220
#define EEPROM_C56_CrystalCap 0x17 //0x17
#define EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex 0x80 //0x80
#define EEPROM_C56_RfA_HT_OFDM_TxPwIndex 0x81 //0x81~0x83
#define EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex 0xbc //0xb8
#define EEPROM_C56_RfC_HT_OFDM_TxPwIndex 0xb9 //0xb9~0xbb
#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID
#define EEPROM_ICVersion_ChannelPlan 0x7C //0x7C:ChnlPlan,
//0x7D:IC_Ver
#define EEPROM_CRC 0x7E //0x7E~0x7F
#define EEPROM_Default_LegacyHTTxPowerDiff 0x4
#define EEPROM_Default_ThermalMeter 0x77
#define EEPROM_Default_AntTxPowerDiff 0x0
#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
#define EEPROM_Default_TxPower 0x1010
#define EEPROM_Default_TxPowerLevel 0x10
//
// Define Different EEPROM type for customer
//
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_CAMEO 0x1
#define EEPROM_CID_RUNTOP 0x2
#define EEPROM_CID_Senao 0x3
#define EEPROM_CID_TOSHIBA 0x4
#define EEPROM_CID_NetCore 0x5
#define EEPROM_CID_Nettronix 0x6
#define EEPROM_CID_Pronet 0x7
#endif
//
//--------------92SU require delete or move to other place later
drivers/staging/rtl8192su/r8192S_phy.c
-342
View File
@@ -624,178 +624,6 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32
}
/**
* Function: phy_RFSerialRead
*
* OverView: Read regster from RF chips
*
* Input:
* PADAPTER Adapter,
* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
* u4Byte Offset, //The target address to be read
*
* Output: None
* Return: u4Byte reback value
* Note: Threre are three types of serial operations:
* 1. Software serial write
* 2. Hardware LSSI-Low Speed Serial Interface
* 3. Hardware HSSI-High speed
* serial write. Driver need to implement (1) and (2).
* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
*/
#if 0
static u32
phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
{
u32 retValue = 0;
struct r8192_priv *priv = ieee80211_priv(dev);
BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
u32 NewOffset;
//u32 value = 0;
u32 tmplong,tmplong2;
u32 RfPiEnable=0;
#if 0
if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
return retValue;
if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
return retValue;
#endif
//
// Make sure RF register offset is correct
//
Offset &= 0x3f;
//
// Switch page for 8256 RF IC
//
NewOffset = Offset;
// For 92S LSSI Read RFLSSIRead
// For RF A/B write 0x824/82c(does not work in the future)
// We must use 0x824 for RF A and B to execute read trigger
tmplong = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord);
tmplong2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, bMaskDWord);
tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF
rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
mdelay(1);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
mdelay(1);
rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
mdelay(1);
if(eRFPath == RF90_PATH_A)
RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
else if(eRFPath == RF90_PATH_B)
RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XB_HSSIParameter1, BIT8);
if(RfPiEnable)
{ // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
//DbgPrint("Readback from RF-PI : 0x%x\n", retValue);
}
else
{ //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
//DbgPrint("Readback from RF-SI : 0x%x\n", retValue);
}
//RTPRINT(FPHY, PHY_RFR, ("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue));
return retValue;
}
4
/**
* Function: phy_RFSerialWrite
*
* OverView: Write data to RF register (page 8~)
*
* Input:
* PADAPTER Adapter,
* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
* u4Byte Offset, //The target address to be read
* u4Byte Data //The new register Data in the target bit position
* //of the target to be read
*
* Output: None
* Return: None
* Note: Threre are three types of serial operations:
* 1. Software serial write
* 2. Hardware LSSI-Low Speed Serial Interface
* 3. Hardware HSSI-High speed
* serial write. Driver need to implement (1) and (2).
* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
*
* Note: For RF8256 only
* The total count of RTL8256(Zebra4) register is around 36 bit it only employs
* 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
* to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
* programming guide" for more details.
* Thus, we define a sub-finction for RTL8526 register address conversion
* ===========================================================
* Register Mode RegCTL[1] RegCTL[0] Note
* (Reg00[12]) (Reg00[10])
* ===========================================================
* Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
* ------------------------------------------------------------------
* Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
* ------------------------------------------------------------------
* Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
* ------------------------------------------------------------------
*
* 2008/09/02 MH Add 92S RF definition
*
*
*
*/
static void
phy_RFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data)
{
u32 DataAndAddr = 0;
struct r8192_priv *priv = ieee80211_priv(dev);
BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
u32 NewOffset;
#if 0
//<Roger_TODO> We should check valid regs for RF_6052 case.
if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
return;
if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
return;
#endif
Offset &= 0x3f;
//
// Shadow Update
//
PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
//
// Switch page for 8256 RF IC
//
NewOffset = Offset;
//
// Put write addr in [5:0] and write data in [31:16]
//
//DataAndAddr = (Data<<16) | (NewOffset&0x3f);
DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF
//
// Write Operation
//
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
//RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
}
#endif
/**
* Function: phy_CalculateBitShift
*
@@ -1097,33 +925,6 @@ phy_BB8192S_Config_ParaFile(struct net_device* dev)
}
#if 0 // 2008/08/18 MH Disable for 92SE
if(pHalData->VersionID > VERSION_8190_BD)
{
//if(pHalData->RF_Type == RF_2T4R)
//{
// Antenna gain offset from B/C/D to A
u4RegValue = ( pHalData->AntennaTxPwDiff[2]<<8 |
pHalData->AntennaTxPwDiff[1]<<4 |
pHalData->AntennaTxPwDiff[0]);
//}
//else
//u4RegValue = 0;
PHY_SetBBReg(dev, rFPGA0_TxGainStage,
(bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
// CrystalCap
// Simulate 8192???
u4RegValue = pHalData->CrystalCap;
PHY_SetBBReg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, u4RegValue);
// Simulate 8190??
//u4RegValue = ((pHalData->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap
//PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, bXtalCap23, u4RegValue);
}
#endif
// Check if the CCK HighPower is turned ON.
// This is used to calculate PWDB.
priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
@@ -2162,18 +1963,10 @@ PHY_GetTxPowerLevel8192S(
// Calculate Antenna pwr diff
if (pwrdiff[rfpath] < 8) // 0~+7
{
#if 0//cosa, it doesn't need to add the offset here
if (rfpath == 0)
powerlevelOFDM24G += pwrdiff[rfpath];
#endif
ht20pwr[rfpath] += pwrdiff[rfpath];
}
else // index8-15=-8~-1
{
#if 0//cosa, it doesn't need to add the offset here
if (rfpath == 0)
powerlevelOFDM24G -= (15-pwrdiff[rfpath]);
#endif
ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
}
}
@@ -2215,10 +2008,6 @@ PHY_GetTxPowerLevel8192S(
ht20pwr[rfpath] -= pwrdiff[rfpath];
}
#if 0//cosa, it doesn't need to add the offset here
if (rfpath == 0)
powerlevelOFDM24G -= pwrdiff[rfpath];
#endif
}
if (priv->rf_type == RF_2T2R)
@@ -2248,10 +2037,6 @@ PHY_GetTxPowerLevel8192S(
}
}
}
#if 0//cosa, useless
// Read HT/Legacy OFDM diff
legacy_ant_pwr_diff= pHalData->TxPwrLegacyHtDiff[RF90_PATH_A][index];
#endif
}
//Cosa added for protection, the reg rFPGA0_TxGainStage
@@ -2340,10 +2125,6 @@ PHY_GetTxPowerLevel8192S(
break;
case RF_8256:
#if 0
PHY_SetRF8256CCKTxPower(dev, powerlevel);
PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
#endif
break;
case RF_6052:
@@ -2574,65 +2355,6 @@ void PHY_InitialGain8192S(struct net_device* dev,u8 Operation )
//struct r8192_priv *priv = ieee80211_priv(dev);
//u32 BitMask;
//u8 initial_gain;
#if 0 // For 8192s test disable
if(!dev->bDriverStopped)
{
switch(Operation)
{
case IG_Backup:
RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Backup, backup the initial gain.\n"));
initial_gain = priv->DefaultInitialGain[0];
BitMask = bMaskByte0;
if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
pMgntInfo->InitGain_Backup.XAAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
pMgntInfo->InitGain_Backup.XBAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
pMgntInfo->InitGain_Backup.XCAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
pMgntInfo->InitGain_Backup.XDAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
BitMask = bMaskByte2;
pMgntInfo->InitGain_Backup.CCA = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Write scan initial gain = 0x%x \n", initial_gain));
write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
break;
case IG_Restore:
RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Restore, restore the initial gain.\n"));
BitMask = 0x7f; //Bit0~ Bit6
if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XAAGCCore1);
rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XBAGCCore1);
rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XCAGCCore1);
rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XDAGCCore1);
BitMask = (BIT22|BIT23);
rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)pMgntInfo->InitGain_Backup.CCA);
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
break;
default:
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown IG Operation. \n"));
break;
}
}
#endif
}
/*-----------------------------------------------------------------------------
@@ -2729,12 +2451,6 @@ void PHY_SetBWModeCallback8192S(struct net_device *dev)
//write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
//write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
//write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
#if 0 //LZM 090219
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
#endif
if (priv->card_8192_version >= VERSION_8192S_BCUT)
write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
@@ -2751,11 +2467,6 @@ void PHY_SetBWModeCallback8192S(struct net_device *dev)
//write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
//write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
//write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
#if 0 //LZM 090219
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
#endif
// Set Control channel to upper or lower. These settings are required only for 40MHz
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
@@ -2874,16 +2585,6 @@ void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EX
else
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
#if 0
if(!priv->bDriverStopped)
{
#ifdef USE_WORKITEM
PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem));//SetBWModeCallback8192SUsbWorkItem
#else
PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0);//PHY_SetBWModeCallback8192S
#endif
}
#endif
if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
{
SetBWModeCallback8192SUsbWorkItem(dev);
@@ -3320,16 +3021,6 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
bool rtValue = TRUE;
// NOt check RF Path now.!
#if 0
if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
{
rtValue = FALSE;
}
if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
{
}
#endif
return rtValue;
} /* PHY_CheckIsLegalRfPath8192S */
@@ -3869,18 +3560,6 @@ void SetBWModeCallback8192SUsb(struct net_device *dev)
case HT_CHANNEL_WIDTH_20:
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
#if 0 //LZM090219
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
// Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
//write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
//write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
//write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
#endif
if (priv->card_8192_version >= VERSION_8192S_BCUT)
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
@@ -4017,33 +3696,12 @@ void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
#if 0 //LZM 090219
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
// Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
#endif
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
break;
case HT_CHANNEL_WIDTH_20_40:
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
#if 0 //LZM 090219
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
// Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
#endif
// Set Control channel to upper or lower. These settings are required only for 40MHz
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
drivers/staging/rtl8192su/r8192S_rtl6052.c
-66
View File
@@ -87,51 +87,6 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];// = {{0}};//FIXLZ
*---------------------------------------------------------------------------*/
extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate)
{
// We do not support gain table change inACUT now !!!! Delete later !!!
#if 0//(RTL92SE_FPGA_VERIFY == 0)
static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
static u4Byte tx_gain_tbl1[6]
= {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
static u4Byte tx_gain_tbl2[6]
= {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
u1Byte i;
if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x0f000);
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G3, bMask20Bits, 0xeacf1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TX_AGC, bMask20Bits, tx_gain_tbl1[i]);
// Set PA to high value
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x01e39);
}
else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x04440);
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G3, bMask20Bits, 0xea4f1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TX_AGC, bMask20Bits, tx_gain_tbl2[i]);
// Set PA low gain
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x01e19);
}
#endif
} /* RF_ChangeTxPath */
@@ -279,15 +234,6 @@ extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel)
{
ofdm_bandedge_chnl_low = 1;
ofdm_bandedge_chnl_high = 11;
#if 0//cosa, Todo: check ofdm 40MHz, when lower and duplicate, the bandedge chnl low=3, high=9
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
{ // Is it the same with the document?
if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
else if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER;
else
pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
}
#endif
BandEdge_Pwrdiff = 0;
if (Channel <= ofdm_bandedge_chnl_low)
BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0];
@@ -385,18 +331,6 @@ extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel)
//
if (priv->rf_type == RF_2T2R)
{
#if 0//cosa, we have only one AntennaTxPwDiff
// HT OFDM
if (index > 1)
{
rf_pwr_diff = pHalData->AntennaTxPwDiff[0];
}
// Legacy OFDM
else
{
rf_pwr_diff = pHalData->AntTxPwDiffLegacy[0];
}
#endif
rf_pwr_diff = priv->AntennaTxPwDiff[0];
//RTPRINT(FPHY, PHY_TXPWR, ("2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff));
drivers/staging/rtl8192su/r8192S_rtl6052.h
-47
View File
@@ -81,53 +81,6 @@ extern void PHY_RF6052SetOFDMTxPower(struct net_device * dev, u8 powerlevel);
extern RT_STATUS PHY_RF6052_Config(struct net_device * dev);
extern void PHY_RFShadowRefresh( struct net_device * dev);
extern void PHY_RFShadowWrite( struct net_device* dev, u32 eRFPath, u32 Offset, u32 Data);
#if 0
//
// RF Shadow operation relative API
//
extern u32
PHY_RFShadowRead(
struct net_device * dev,
RF90_RADIO_PATH_E eRFPath,
u32 Offset);
extern void
PHY_RFShadowCompare(
struct net_device * dev,
RF90_RADIO_PATH_E eRFPath,
u32 Offset);
extern void
PHY_RFShadowRecorver(
struct net_device * dev,
RF90_RADIO_PATH_E eRFPath,
u32 Offset);
extern void
PHY_RFShadowCompareAll(
struct net_device * dev);
extern void
PHY_RFShadowRecorverAll(
struct net_device * dev);
extern void
PHY_RFShadowCompareFlagSet(
struct net_device * dev,
RF90_RADIO_PATH_E eRFPath,
u32 Offset,
u8 Type);
extern void
PHY_RFShadowRecorverFlagSet(
struct net_device * dev,
RF90_RADIO_PATH_E eRFPath,
u32 Offset,
u8 Type);
extern void
PHY_RFShadowCompareFlagSetAll(
struct net_device * dev);
extern void
PHY_RFShadowRecorverFlagSetAll(
struct net_device * dev);
extern void
PHY_RFShadowRefresh(
struct net_device * dev);
#endif
/*--------------------------Exported Function prototype---------------------*/
drivers/staging/rtl8192su/r8192U.h
-214
View File
@@ -87,11 +87,6 @@
// Rx smooth factor
#define Rx_Smooth_Factor 20
#if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
#define DMESG(x,a...) printk(KERN_INFO RTL819xU_MODULE_NAME ": " x "\n", ## a)
#define DMESGW(x,a...) printk(KERN_WARNING RTL819xU_MODULE_NAME ": WW:" x "\n", ## a)
#define DMESGE(x,a...) printk(KERN_WARNING RTL819xU_MODULE_NAME ": EE:" x "\n", ## a)
#else
#define DMESG(x,a...)
#define DMESGW(x,a...)
#define DMESGE(x,a...)
@@ -149,7 +144,6 @@ do { if(rt_global_debug_component & component) \
#define COMP_DOWN BIT29 //for rm driver module
#define COMP_RESET BIT30 //for silent reset
#define COMP_ERR BIT31 //for error out, always on
#endif
#define RTL819x_DEBUG
#ifdef RTL819x_DEBUG
@@ -711,135 +705,6 @@ typedef enum _RTL8192SUSB_LOOPBACK{
}RTL8192SUSB_LOOPBACK_E;
//#endif
#if 0
/* due to rtl8192 firmware */
typedef enum _desc_packet_type_e{
DESC_PACKET_TYPE_INIT = 0,
DESC_PACKET_TYPE_NORMAL = 1,
}desc_packet_type_e;
typedef enum _firmware_source{
FW_SOURCE_IMG_FILE = 0,
FW_SOURCE_HEADER_FILE = 1, //from header file
}firmware_source_e, *pfirmware_source_e;
typedef enum _firmware_status{
FW_STATUS_0_INIT = 0,
FW_STATUS_1_MOVE_BOOT_CODE = 1,
FW_STATUS_2_MOVE_MAIN_CODE = 2,
FW_STATUS_3_TURNON_CPU = 3,
FW_STATUS_4_MOVE_DATA_CODE = 4,
FW_STATUS_5_READY = 5,
}firmware_status_e;
typedef struct _rt_firmare_seg_container {
u16 seg_size;
u8 *seg_ptr;
}fw_seg_container, *pfw_seg_container;
//--------------------------------------------------------------------------------
// 8192S Firmware related
//--------------------------------------------------------------------------------
typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required
//--- LONG WORD 0 ----
u32 RegulatoryClass;
u32 Rfintfs;
//--- LONG WORD 1 ----
u32 ChipVer;
u32 HCISel;
//--- LONG WORD 2 ----
u32 IBKMode;
u32 Rsvd00;
//--- LONG WORD 3 ----
u32 Rsvd01;
u8 Qos_En; // QoS enable
u8 En40MHz; // 40MHz BW enable
u8 AMSDU2AMPDU_En; //14181 convert AMSDU to AMPDU, 0: disable
u8 AMPDU_En; //111n AMPDU/AMSDU enable
//--- LONG WORD 4 ----
u8 rate_control_offload;//FW offloads, 0: driver handles
u8 aggregation_offload; // FW offloads, 0: driver handles
u8 beacon_offload; //FW offloads, 0: driver handles
u8 MLME_offload; // FW offloads, 0: driver handles
u8 hwpc_offload; // FW offloads, 0: driver handles
u8 tcp_checksum_offload; //FW offloads, 0: driver handles
u8 tcp_offload; //FW offloads, 0: driver handles
u8 ps_control_offload; //FW offloads, 0: driver handles
//--- LONG WORD 5 ----
u8 WWLAN_Offload; // FW offloads, 0: driver handles
u8 MPMode; // normal mode, 0: MP mode;
u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
u16 Signature; //0x12: 8712, 0x92: 8192S
u16 Rsvd11;
// u32 rsvd1;
// u32 wireless_band; //no A-band exists in 8712
}RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV;
typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required
//--- LONG WORD 0 ----
u16 Signature;
u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
u32 DMEMSize; //define the size of boot loader
//--- LONG WORD 1 ----
u32 IMG_IMEM_SIZE; //define the size of FW in IMEM
u32 IMG_SRAM_SIZE; //define the size of FW in SRAM
//--- LONG WORD 2 ----
u32 FW_PRIV_SIZE; //define the size of DMEM variable
u32 Rsvd0;
//--- LONG WORD 3 ----
u32 Rsvd1;
u32 Rsvd2;
RT_8192S_FIRMWARE_PRIV FWPriv;
}RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR;
#define RT_8192S_FIRMWARE_HDR_SIZE 80
typedef enum _FIRMWARE_8192S_STATUS{
FW_STATUS_INIT = 0,
FW_STATUS_LOAD_IMEM = 1,
FW_STATUS_LOAD_EMEM = 2,
FW_STATUS_LOAD_DMEM = 3,
FW_STATUS_READY = 4,
}FIRMWARE_8192S_STATUS;
#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
typedef struct _rt_firmware{
firmware_source_e eFWSource;
PRT_8192S_FIRMWARE_HDR pFwHeader;
FIRMWARE_8192S_STATUS FWStatus;
u8 FwIMEM[64000];
u8 FwEMEM[64000];
u32 FwIMEMLen;
u32 FwEMEMLen;
u8 szFwTmpBuffer[164000];
u16 CmdPacketFragThresold;
//firmware_status_e firmware_status;//in 92u temp FIXLZM
//u16 cmdpacket_frag_thresold;//in 92u temp FIXLZM
//u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];//in 92u temp FIXLZM
//u16 firmware_buf_size;//in 92u temp FIXLZM
}rt_firmware, *prt_firmware;
typedef struct _rt_firmware_info_819xUsb{
u8 sz_info[16];
}rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
#endif
//+by amy 080507
#define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
@@ -920,21 +785,6 @@ typedef struct rtl_reg_debug{
unsigned char buf[0xff];
}rtl_reg_debug;
#if 0
typedef struct tx_pendingbuf
{
struct ieee80211_txb *txb;
short ispending;
short descfrag;
} tx_pendigbuf;
#endif
typedef struct _rt_9x_tx_rate_history {
u32 cck[4];
u32 ofdm[8];
@@ -1689,70 +1539,6 @@ typedef enum{
UART_PRIORITY //0x0F
} priority_t;
#if 0
typedef enum{
NIC_8192U = 1,
NIC_8190P = 2,
NIC_8192E = 3,
NIC_8192SE = 4,
NIC_8192SU = 5,
} nic_t;
#endif
#if 0 //defined in Qos.h
//typedef u32 AC_CODING;
#define AC0_BE 0 // ACI: 0x00 // Best Effort
#define AC1_BK 1 // ACI: 0x01 // Background
#define AC2_VI 2 // ACI: 0x10 // Video
#define AC3_VO 3 // ACI: 0x11 // Voice
#define AC_MAX 4 // Max: define total number; Should not to be used as a real enum.
//
// ECWmin/ECWmax field.
// Ref: WMM spec 2.2.2: WME Parameter Element, p.13.
//
typedef union _ECW{
u8 charData;
struct
{
u8 ECWmin:4;
u8 ECWmax:4;
}f; // Field
}ECW, *PECW;
//
// ACI/AIFSN Field.
// Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
//
typedef union _ACI_AIFSN{
u8 charData;
struct
{
u8 AIFSN:4;
u8 ACM:1;
u8 ACI:2;
u8 Reserved:1;
}f; // Field
}ACI_AIFSN, *PACI_AIFSN;
//
// AC Parameters Record Format.
// Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
//
typedef union _AC_PARAM{
u32 longData;
u8 charData[4];
struct
{
ACI_AIFSN AciAifsn;
ECW Ecw;
u16 TXOPLimit;
}f; // Field
}AC_PARAM, *PAC_PARAM;
#endif
#ifdef JOHN_HWSEC
struct ssid_thread {
struct net_device *dev;
drivers/staging/rtl8192su/r8192U_core.c
+3 -1517
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