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Merge remote-tracking branch 'scottwood/next' into next
Scott says: "Highlights include a bunch of 8xx optimizations, device tree bindings for Freescale BMan, QMan, and FMan datapath components, misc device tree updates, and inbound rio window support."
This commit is contained in:
Michael Ellerman
@@ -62,6 +62,8 @@ Required properties:
|
||||
It takes parent's clock-frequency as its clock.
|
||||
* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
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||||
It takes parent's clock-frequency as its clock.
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||||
* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
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||||
* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
|
||||
- #clock-cells: From common clock binding. The number of cells in a
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||||
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
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clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
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@@ -128,8 +130,16 @@ Example for clock block and clock provider:
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clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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clock-output-names = "cmux1";
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};
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||||
platform-pll: platform-pll@c00 {
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#clock-cells = <1>;
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reg = <0xc00 0x4>;
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compatible = "fsl,qoriq-platform-pll-1.0";
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clocks = <&sysclk>;
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clock-output-names = "platform-pll", "platform-pll-div2";
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};
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};
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}
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};
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Example for clock consumer:
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||||
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||||
@@ -139,4 +149,4 @@ Example for clock consumer:
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clocks = <&mux0>;
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||||
...
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};
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}
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};
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,56 @@
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QorIQ DPAA Buffer Manager Portals Device Tree Binding
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||||
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||||
Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
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CONTENTS
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||||
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- BMan Portal
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- Example
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BMan Portal Node
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Portals are memory mapped interfaces to BMan that allow low-latency, lock-less
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interaction by software running on processor cores, accelerators and network
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interfaces with the BMan
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PROPERTIES
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- compatible
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Usage: Required
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Value type: <stringlist>
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Definition: Must include "fsl,bman-portal-<hardware revision>"
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May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal"
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- reg
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Usage: Required
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Value type: <prop-encoded-array>
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Definition: Two regions. The first is the cache-enabled region of
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the portal. The second is the cache-inhibited region of
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the portal
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- interrupts
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Usage: Required
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Value type: <prop-encoded-array>
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Definition: Standard property
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EXAMPLE
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The example below shows a (P4080) BMan portals container/bus node with two portals
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bman-portals@ff4000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0xf 0xf4000000 0x200000>;
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bman-portal@0 {
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compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
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reg = <0x0 0x4000>, <0x100000 0x1000>;
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interrupts = <105 2 0 0>;
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};
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bman-portal@4000 {
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compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
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reg = <0x4000 0x4000>, <0x101000 0x1000>;
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interrupts = <107 2 0 0>;
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};
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};
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@@ -0,0 +1,125 @@
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QorIQ DPAA Buffer Manager Device Tree Bindings
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|
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Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
|
||||
|
||||
CONTENTS
|
||||
|
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- BMan Node
|
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- BMan Private Memory Node
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- Example
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BMan Node
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The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA).
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BMan supports hardware allocation and deallocation of buffers belonging to pools
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originally created by software with configurable depletion thresholds. This
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binding covers the CCSR space programming model
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PROPERTIES
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- compatible
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Usage: Required
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Value type: <stringlist>
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Definition: Must include "fsl,bman"
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May include "fsl,<SoC>-bman"
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- reg
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Usage: Required
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Value type: <prop-encoded-array>
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Definition: Registers region within the CCSR address space
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The BMan revision information is located in the BMAN_IP_REV_1/2 registers which
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are located at offsets 0xbf8 and 0xbfc
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- interrupts
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Usage: Required
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Value type: <prop-encoded-array>
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Definition: Standard property. The error interrupt
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- fsl,liodn
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Usage: See pamu.txt
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Value type: <prop-encoded-array>
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Definition: PAMU property used for static LIODN assignment
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- fsl,iommu-parent
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Usage: See pamu.txt
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Value type: <phandle>
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Definition: PAMU property used for dynamic LIODN assignment
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For additional details about the PAMU/LIODN binding(s) see pamu.txt
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Devices connected to a BMan instance via Direct Connect Portals (DCP) must link
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to the respective BMan instance
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- fsl,bman
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Usage: Required
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Value type: <prop-encoded-array>
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Description: List of phandle and DCP index pairs, to the BMan instance
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to which this device is connected via the DCP
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BMan Private Memory Node
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BMan requires a contiguous range of physical memory used for the backing store
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for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as a
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node under the /reserved-memory node
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The BMan FBPR memory node must be named "bman-fbpr"
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PROPERTIES
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- compatible
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Usage: required
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Value type: <stringlist>
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Definition: Must inclide "fsl,bman-fbpr"
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The following constraints are relevant to the FBPR private memory:
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- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
|
||||
16 GiB
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- The alignment must be a muliptle of the memory size
|
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|
||||
The size of the FBPR must be chosen by observing the hardware features configured
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via the Reset Configuration Word (RCW) and that are relevant to a specific board
|
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(e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports,
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etc.). The size configured in the DT must reflect the hardware capabilities and
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not the specific needs of an application
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For additional details about reserved memory regions see reserved-memory.txt
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EXAMPLE
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The example below shows a BMan FBPR dynamic allocation memory node
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bman_fbpr: bman-fbpr {
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compatible = "fsl,bman-fbpr";
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alloc-ranges = <0 0 0xf 0xffffffff>;
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size = <0 0x1000000>;
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alignment = <0 0x1000000>;
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};
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};
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The example below shows a (P4080) BMan CCSR-space node
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crypto@300000 {
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...
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fsl,bman = <&bman, 2>;
|
||||
...
|
||||
};
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|
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bman: bman@31a000 {
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compatible = "fsl,bman";
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reg = <0x31a000 0x1000>;
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interrupts = <16 2 1 2>;
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fsl,liodn = <0x17>;
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memory-region = <&bman_fbpr>;
|
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};
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|
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fman@400000 {
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...
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fsl,bman = <&bman, 0>;
|
||||
...
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};
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@@ -0,0 +1,154 @@
|
||||
QorIQ DPAA Queue Manager Portals Device Tree Binding
|
||||
|
||||
Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
|
||||
|
||||
CONTENTS
|
||||
|
||||
- QMan Portal
|
||||
- QMan Pool Channel
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- Example
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|
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QMan Portal Node
|
||||
|
||||
Portals are memory mapped interfaces to QMan that allow low-latency, lock-less
|
||||
interaction by software running on processor cores, accelerators and network
|
||||
interfaces with the QMan
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: Required
|
||||
Value type: <stringlist>
|
||||
Definition: Must include "fsl,qman-portal-<hardware revision>"
|
||||
May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal"
|
||||
|
||||
- reg
|
||||
Usage: Required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Two regions. The first is the cache-enabled region of
|
||||
the portal. The second is the cache-inhibited region of
|
||||
the portal
|
||||
|
||||
- interrupts
|
||||
Usage: Required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Standard property
|
||||
|
||||
- fsl,liodn
|
||||
Usage: See pamu.txt
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN
|
||||
(FLIODN)
|
||||
|
||||
- fsl,iommu-parent
|
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Usage: See pamu.txt
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||||
Value type: <phandle>
|
||||
Definition: PAMU property used for dynamic LIODN assignment
|
||||
|
||||
For additional details about the PAMU/LIODN binding(s) see pamu.txt
|
||||
|
||||
- fsl,qman-channel-id
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||||
Usage: Required
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||||
Value type: <u32>
|
||||
Definition: The hardware index of the channel. This can also be
|
||||
determined by dividing any of the channel's 8 work queue
|
||||
IDs by 8
|
||||
|
||||
In addition to these properties the qman-portals should have sub-nodes to
|
||||
represent the HW devices/portals that are connected to the software portal
|
||||
described here
|
||||
|
||||
The currently supported sub-nodes are:
|
||||
* fman0
|
||||
* fman1
|
||||
* pme
|
||||
* crypto
|
||||
|
||||
These subnodes should have the following properties:
|
||||
|
||||
- fsl,liodn
|
||||
Usage: See pamu.txt
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: PAMU property used for static LIODN assignment
|
||||
|
||||
- fsl,iommu-parent
|
||||
Usage: See pamu.txt
|
||||
Value type: <phandle>
|
||||
Definition: PAMU property used for dynamic LIODN assignment
|
||||
|
||||
- dev-handle
|
||||
Usage: Required
|
||||
Value type: <phandle>
|
||||
Definition: The phandle to the particular hardware device that this
|
||||
portal is connected to.
|
||||
|
||||
DPAA QMan Pool Channel Nodes
|
||||
|
||||
Pool Channels are defined with the following properties.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: Required
|
||||
Value type: <stringlist>
|
||||
Definition: Must include "fsl,qman-pool-channel"
|
||||
May include "fsl,<SoC>-qman-pool-channel"
|
||||
|
||||
- fsl,qman-channel-id
|
||||
Usage: Required
|
||||
Value type: <u32>
|
||||
Definition: The hardware index of the channel. This can also be
|
||||
determined by dividing any of the channel's 8 work queue
|
||||
IDs by 8
|
||||
|
||||
EXAMPLE
|
||||
|
||||
The example below shows a (P4080) QMan portals container/bus node with two portals
|
||||
|
||||
qman-portals@ff4200000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0xf 0xf4200000 0x200000>;
|
||||
|
||||
qman-portal@0 {
|
||||
compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
|
||||
reg = <0 0x4000>, <0x100000 0x1000>;
|
||||
interrupts = <104 2 0 0>;
|
||||
fsl,liodn = <1 2>;
|
||||
fsl,qman-channel-id = <0>;
|
||||
|
||||
fman0 {
|
||||
fsl,liodn = <0x21>;
|
||||
dev-handle = <&fman0>;
|
||||
};
|
||||
fman1 {
|
||||
fsl,liodn = <0xa1>;
|
||||
dev-handle = <&fman1>;
|
||||
};
|
||||
crypto {
|
||||
fsl,liodn = <0x41 0x66>;
|
||||
dev-handle = <&crypto>;
|
||||
};
|
||||
};
|
||||
qman-portal@4000 {
|
||||
compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
|
||||
reg = <0x4000 0x4000>, <0x101000 0x1000>;
|
||||
interrupts = <106 2 0 0>;
|
||||
fsl,liodn = <3 4>;
|
||||
fsl,qman-channel-id = <1>;
|
||||
|
||||
fman0 {
|
||||
fsl,liodn = <0x22>;
|
||||
dev-handle = <&fman0>;
|
||||
};
|
||||
fman1 {
|
||||
fsl,liodn = <0xa2>;
|
||||
dev-handle = <&fman1>;
|
||||
};
|
||||
crypto {
|
||||
fsl,liodn = <0x42 0x67>;
|
||||
dev-handle = <&crypto>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,165 @@
|
||||
QorIQ DPAA Queue Manager Device Tree Binding
|
||||
|
||||
Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
|
||||
|
||||
CONTENTS
|
||||
|
||||
- QMan Node
|
||||
- QMan Private Memory Nodes
|
||||
- Example
|
||||
|
||||
QMan Node
|
||||
|
||||
The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan
|
||||
supports queuing and QoS scheduling of frames to CPUs, network interfaces and
|
||||
DPAA logic modules, maintains packet ordering within flows. Besides providing
|
||||
flow-level queuing, is also responsible for congestion management functions such
|
||||
as RED/WRED, congestion notifications and tail discards. This binding covers the
|
||||
CCSR space programming model
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: Required
|
||||
Value type: <stringlist>
|
||||
Definition: Must include "fsl,qman"
|
||||
May include "fsl,<SoC>-qman"
|
||||
|
||||
- reg
|
||||
Usage: Required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Registers region within the CCSR address space
|
||||
|
||||
The QMan revision information is located in the QMAN_IP_REV_1/2 registers which
|
||||
are located at offsets 0xbf8 and 0xbfc
|
||||
|
||||
- interrupts
|
||||
Usage: Required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Standard property. The error interrupt
|
||||
|
||||
- fsl,liodn
|
||||
Usage: See pamu.txt
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: PAMU property used for static LIODN assignment
|
||||
|
||||
- fsl,iommu-parent
|
||||
Usage: See pamu.txt
|
||||
Value type: <phandle>
|
||||
Definition: PAMU property used for dynamic LIODN assignment
|
||||
|
||||
For additional details about the PAMU/LIODN binding(s) see pamu.txt
|
||||
|
||||
- clocks
|
||||
Usage: See clock-bindings.txt and qoriq-clock.txt
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Reference input clock. Its frequency is half of the
|
||||
platform clock
|
||||
|
||||
Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
|
||||
to the respective QMan instance
|
||||
|
||||
- fsl,qman
|
||||
Usage: Required
|
||||
Value type: <prop-encoded-array>
|
||||
Description: List of phandle and DCP index pairs, to the QMan instance
|
||||
to which this device is connected via the DCP
|
||||
|
||||
QMan Private Memory Nodes
|
||||
|
||||
QMan requires two contiguous range of physical memory used for the backing store
|
||||
for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR).
|
||||
This memory is reserved/allocated as a nodes under the /reserved-memory node
|
||||
|
||||
The QMan FQD memory node must be named "qman-fqd"
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must inclide "fsl,qman-fqd"
|
||||
|
||||
The QMan PFDR memory node must be named "qman-pfdr"
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must inclide "fsl,qman-pfdr"
|
||||
|
||||
The following constraints are relevant to the FQD and PFDR private memory:
|
||||
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
|
||||
1 GiB
|
||||
- The alignment must be a muliptle of the memory size
|
||||
|
||||
The size of the FQD and PFDP must be chosen by observing the hardware features
|
||||
configured via the Reset Configuration Word (RCW) and that are relevant to a
|
||||
specific board (e.g. number of MAC(s) pinned-out, number of offline/host command
|
||||
FMan ports, etc.). The size configured in the DT must reflect the hardware
|
||||
capabilities and not the specific needs of an application
|
||||
|
||||
For additional details about reserved memory regions see reserved-memory.txt
|
||||
|
||||
EXAMPLE
|
||||
|
||||
The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
qman_fqd: qman-fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0xf 0xffffffff>;
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0xf 0xffffffff>;
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
The example below shows a (P4080) QMan CCSR-space node
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
...
|
||||
sysclk: sysclk {
|
||||
...
|
||||
};
|
||||
...
|
||||
platform_pll: platform-pll@c00 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0xc00 0x4>;
|
||||
compatible = "fsl,qoriq-platform-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "platform-pll", "platform-pll-div2";
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
crypto@300000 {
|
||||
...
|
||||
fsl,qman = <&qman, 2>;
|
||||
...
|
||||
};
|
||||
|
||||
qman: qman@318000 {
|
||||
compatible = "fsl,qman";
|
||||
reg = <0x318000 0x1000>;
|
||||
interrupts = <16 2 1 3>
|
||||
fsl,liodn = <0x16>;
|
||||
memory-region = <&qman_fqd &qman_pfdr>;
|
||||
clocks = <&platform_pll 1>;
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
...
|
||||
fsl,qman = <&qman, 0>;
|
||||
...
|
||||
};
|
||||
@@ -552,7 +552,7 @@ config PPC_4K_PAGES
|
||||
bool "4k page size"
|
||||
|
||||
config PPC_16K_PAGES
|
||||
bool "16k page size" if 44x
|
||||
bool "16k page size" if 44x || PPC_8xx
|
||||
|
||||
config PPC_64K_PAGES
|
||||
bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64
|
||||
|
||||
@@ -193,9 +193,9 @@
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
/include/ "fsl/qoriq-clockgen2.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-dma-0.dtsi"
|
||||
|
||||
@@ -152,6 +152,29 @@
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2>;
|
||||
|
||||
ina220@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
adt7461@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -40,31 +40,6 @@
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x0 0x0 0x4000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 3MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00300000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@300000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00300000 0x00100000>;
|
||||
label = "NAND DTB Image";
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
/* 8MB for Linux Kernel Image */
|
||||
reg = <0x00400000 0x00800000>;
|
||||
label = "NAND Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@c00000 {
|
||||
/* Rest space for Root file System Image */
|
||||
reg = <0x00c00000 0x07400000>;
|
||||
label = "NAND RFS Image";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -82,31 +57,6 @@
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
/* 512KB for u-boot Bootloader Image */
|
||||
partition@0 {
|
||||
reg = <0x0 0x00080000>;
|
||||
label = "SPI Flash U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
/* 512KB for DTB Image */
|
||||
partition@80000 {
|
||||
reg = <0x00080000 0x00080000>;
|
||||
label = "SPI Flash DTB Image";
|
||||
};
|
||||
|
||||
/* 4MB for Linux Kernel Image */
|
||||
partition@100000 {
|
||||
reg = <0x00100000 0x00400000>;
|
||||
label = "SPI Flash Kernel Image";
|
||||
};
|
||||
|
||||
/*11MB for RFS Image */
|
||||
partition@500000 {
|
||||
reg = <0x00500000 0x00B00000>;
|
||||
label = "SPI Flash RFS Image";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -80,33 +80,9 @@
|
||||
compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
/include/ "qoriq-clockgen2.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-2.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
|
||||
@@ -124,33 +124,9 @@
|
||||
compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
/include/ "qoriq-clockgen2.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-2.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
|
||||
@@ -305,53 +305,9 @@
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
/include/ "qoriq-clockgen1.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
||||
mux2: mux2@40 {
|
||||
#clock-cells = <0>;
|
||||
|
||||
@@ -332,53 +332,9 @@
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
/include/ "qoriq-clockgen1.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
||||
mux2: mux2@40 {
|
||||
#clock-cells = <0>;
|
||||
|
||||
@@ -352,35 +352,9 @@
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
/include/ "qoriq-clockgen1.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
pll2: pll2@840 {
|
||||
#clock-cells = <1>;
|
||||
@@ -398,24 +372,6 @@
|
||||
clock-output-names = "pll3", "pll3-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
||||
mux2: mux2@40 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x40 0x4>;
|
||||
|
||||
@@ -337,53 +337,9 @@
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
/include/ "qoriq-clockgen1.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
|
||||
@@ -297,53 +297,9 @@
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
/include/ "qoriq-clockgen1.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
||||
mux2: mux2@40 {
|
||||
#clock-cells = <0>;
|
||||
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
platform_pll: platform-pll@c00 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0xc00 0x4>;
|
||||
compatible = "fsl,qoriq-platform-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "platform-pll", "platform-pll-div2";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,qoriq-clockgen-2.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
|
||||
};
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
|
||||
};
|
||||
platform_pll: platform-pll@c00 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0xc00 0x4>;
|
||||
compatible = "fsl,qoriq-platform-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "platform-pll", "platform-pll-div2";
|
||||
};
|
||||
};
|
||||
@@ -281,35 +281,9 @@
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
/include/ "qoriq-clockgen2.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-2.0";
|
||||
clock-output-names = "sysclk", "fixed-clock";
|
||||
};
|
||||
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user