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Merge remote-tracking branches 'asoc/topic/ad1836', 'asoc/topic/ad193x', 'asoc/topic/adav80x', 'asoc/topic/adsp', 'asoc/topic/ak4641', 'asoc/topic/ak4642', 'asoc/topic/arizona', 'asoc/topic/atmel', 'asoc/topic/au1x', 'asoc/topic/axi', 'asoc/topic/bcm2835', 'asoc/topic/blackfin', 'asoc/topic/cs4271', 'asoc/topic/cs42l52', 'asoc/topic/da7210', 'asoc/topic/davinci', 'asoc/topic/ep93xx', 'asoc/topic/fsl', 'asoc/topic/fsl-mxs', 'asoc/topic/generic', 'asoc/topic/hdmi', 'asoc/topic/jack', 'asoc/topic/jz4740', 'asoc/topic/max98090', 'asoc/topic/mxs', 'asoc/topic/omap', 'asoc/topic/pxa', 'asoc/topic/rcar', 'asoc/topic/s6000', 'asoc/topic/sai', 'asoc/topic/samsung', 'asoc/topic/sgtl5000', 'asoc/topic/spear', 'asoc/topic/ssm2518', 'asoc/topic/ssm2602', 'asoc/topic/tegra', 'asoc/topic/tlv320aic3x', 'asoc/topic/twl6040', 'asoc/topic/txx9', 'asoc/topic/uda1380', 'asoc/topic/width', 'asoc/topic/wm8510', 'asoc/topic/wm8523', 'asoc/topic/wm8580', 'asoc/topic/wm8711', 'asoc/topic/wm8728', 'asoc/topic/wm8731', 'asoc/topic/wm8741', 'asoc/topic/wm8750', 'asoc/topic/wm8753', 'asoc/topic/wm8776', 'asoc/topic/wm8804', 'asoc/topic/wm8900', 'asoc/topic/wm8901', 'asoc/topic/wm8940', 'asoc/topic/wm8962', 'asoc/topic/wm8974', 'asoc/topic/wm8985', 'asoc/topic/wm8988', 'asoc/topic/wm8990', 'asoc/topic/wm8991', 'asoc/topic/wm8994', 'asoc/topic/wm8995', 'asoc/topic/wm9081' and 'asoc/topic/x86' into asoc-next
This commit is contained in:
Mark Brown
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commit
2cde51fbd0
@@ -0,0 +1,31 @@
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ADI AXI-I2S controller
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Required properties:
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- compatible : Must be "adi,axi-i2s-1.00.a"
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- reg : Must contain I2S core's registers location and length
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- clocks : Pairs of phandle and specifier referencing the controller's clocks.
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The controller expects two clocks, the clock used for the AXI interface and
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the clock used as the sampling rate reference clock sample.
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- clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
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rate reference clock.
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- dmas: Pairs of phandle and specifier for the DMA channels that are used by
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the core. The core expects two dma channels, one for transmit and one for
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receive.
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- dma-names : "tx" for the transmit channel, "rx" for the receive channel.
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For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
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please check:
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* resource-names.txt
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* clock/clock-bindings.txt
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* dma/dma.txt
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Example:
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i2s: i2s@0x77600000 {
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compatible = "adi,axi-i2s-1.00.a";
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reg = <0x77600000 0x1000>;
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clocks = <&clk 15>, <&audio_clock>;
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clock-names = "axi", "ref";
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dmas = <&ps7_dma 0>, <&ps7_dma 1>;
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dma-names = "tx", "rx";
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};
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@@ -0,0 +1,30 @@
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ADI AXI-SPDIF controller
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Required properties:
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- compatible : Must be "adi,axi-spdif-1.00.a"
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- reg : Must contain SPDIF core's registers location and length
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- clocks : Pairs of phandle and specifier referencing the controller's clocks.
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The controller expects two clocks, the clock used for the AXI interface and
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the clock used as the sampling rate reference clock sample.
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- clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
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rate reference clock.
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- dmas: Pairs of phandle and specifier for the DMA channel that is used by
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the core. The core expects one dma channel for transmit.
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- dma-names : Must be "tx"
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For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
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please check:
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* resource-names.txt
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* clock/clock-bindings.txt
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* dma/dma.txt
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Example:
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spdif: spdif@0x77400000 {
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compatible = "adi,axi-spdif-tx-1.00.a";
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reg = <0x77600000 0x1000>;
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clocks = <&clk 15>, <&audio_clock>;
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clock-names = "axi", "ref";
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dmas = <&ps7_dma 0>;
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dma-names = "tx";
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};
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@@ -0,0 +1,25 @@
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* Broadcom BCM2835 SoC I2S/PCM module
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Required properties:
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- compatible: "brcm,bcm2835-i2s"
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- reg: A list of base address and size entries:
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* The first entry should cover the PCM registers
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* The second entry should cover the PCM clock registers
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- dmas: List of DMA controller phandle and DMA request line ordered pairs.
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- dma-names: Identifier string for each DMA request line in the dmas property.
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These strings correspond 1:1 with the ordered pairs in dmas.
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One of the DMA channels will be responsible for transmission (should be
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named "tx") and one for reception (should be named "rx").
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Example:
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bcm2835_i2s: i2s@7e203000 {
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compatible = "brcm,bcm2835-i2s";
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reg = <0x7e203000 0x20>,
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<0x7e101098 0x02>;
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dmas = <&dma 2>,
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<&dma 3>;
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dma-names = "tx", "rx";
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};
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@@ -0,0 +1,46 @@
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CS42L52 audio CODEC
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Required properties:
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- compatible : "cirrus,cs42l52"
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- reg : the I2C address of the device for I2C
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Optional properties:
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- cirrus,reset-gpio : GPIO controller's phandle and the number
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of the GPIO used to reset the codec.
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- cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
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Allowable values of 0x00 through 0x0F. These are raw values written to the
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register, not the actual frequency. The frequency is determined by the following.
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Frequency = (64xFs)/(N+2)
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N = chgfreq_val
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Fs = Sample Rate (variable)
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- cirrus,mica-differential-cfg : boolean, If present, then the MICA input is configured
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as a differential input. If not present then the MICA input is configured as
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Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
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- cirrus,micb-differential-cfg : boolean, If present, then the MICB input is configured
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as a differential input. If not present then the MICB input is configured as
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Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
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- cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin
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0 = 0.5 x VA
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1 = 0.6 x VA
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2 = 0.7 x VA
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3 = 0.8 x VA
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4 = 0.83 x VA
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5 = 0.91 x VA
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Example:
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codec: codec@4a {
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compatible = "cirrus,cs42l52";
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reg = <0x4a>;
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reset-gpio = <&gpio 10 0>;
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cirrus,chgfreq-divisor = <0x05>;
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cirrus.mica-differential-cfg;
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cirrus,micbias-lvl = <5>;
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};
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@@ -4,7 +4,8 @@ Required properties:
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- compatible :
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"ti,dm646x-mcasp-audio" : for DM646x platforms
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"ti,da830-mcasp-audio" : for both DA830 & DA850 platforms
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"ti,am33xx-mcasp-audio" : for AM33xx platforms (AM33xx, TI81xx)
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"ti,am33xx-mcasp-audio" : for AM33xx platforms (AM33xx, AM43xx, TI81xx)
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"ti,dra7-mcasp-audio" : for DRA7xx platforms
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- reg : Should contain reg specifiers for the entries in the reg-names property.
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- reg-names : Should contain:
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@@ -36,7 +37,8 @@ Optional properties:
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- pinctrl-0: Should specify pin control group used for this controller.
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- pinctrl-names: Should contain only one value - "default", for more details
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please refer to pinctrl-bindings.txt
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- fck_parent : Should contain a valid clock name which will be used as parent
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for the McASP fck
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Example:
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@@ -0,0 +1,40 @@
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Freescale Synchronous Audio Interface (SAI).
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The SAI is based on I2S module that used communicating with audio codecs,
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which provides a synchronous audio interface that supports fullduplex
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serial interfaces with frame synchronization such as I2S, AC97, TDM, and
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codec/DSP interfaces.
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Required properties:
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- compatible: Compatible list, contains "fsl,vf610-sai".
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- reg: Offset and length of the register set for the device.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names : Must include the "sai" entry.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Two dmas have to be defined, "tx" and "rx".
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- pinctrl-names: Must contain a "default" entry.
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- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
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See ../pinctrl/pinctrl-bindings.txt for details of the property values.
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- big-endian-regs: If this property is absent, the little endian mode will
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be in use as default, or the big endian mode will be in use for all the
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device registers.
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- big-endian-data: If this property is absent, the little endian mode will
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be in use as default, or the big endian mode will be in use for all the
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fifo data.
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Example:
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sai2: sai@40031000 {
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compatible = "fsl,vf610-sai";
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reg = <0x40031000 0x1000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2_1>;
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clocks = <&clks VF610_CLK_SAI2>;
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clock-names = "sai";
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dma-names = "tx", "rx";
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dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
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<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
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big-endian-regs;
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big-endian-data;
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};
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@@ -0,0 +1,17 @@
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Device-Tree bindings for dummy HDMI codec
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Required properties:
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- compatible: should be "linux,hdmi-audio".
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CODEC output pins:
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* TX
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CODEC input pins:
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* RX
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Example node:
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hdmi_audio: hdmi_audio@0 {
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compatible = "linux,hdmi-audio";
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status = "okay";
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};
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@@ -0,0 +1,43 @@
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MAX98090 audio CODEC
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This device supports I2C only.
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Required properties:
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- compatible : "maxim,max98090".
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- reg : The I2C address of the device.
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- interrupts : The CODEC's interrupt output.
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Pins on the device (for linking into audio routes):
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* MIC1
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* MIC2
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* DMICL
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* DMICR
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* IN1
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* IN2
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* IN3
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* IN4
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* IN5
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* IN6
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* IN12
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* IN34
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* IN56
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* HPL
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* HPR
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* SPKL
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* SPKR
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* RCVL
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* RCVR
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* MICBIAS
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Example:
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audio-codec@10 {
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compatible = "maxim,max98090";
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reg = <0x10>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
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};
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@@ -0,0 +1,51 @@
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NVIDIA Tegra audio complex, with MAX98090 CODEC
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Required properties:
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- compatible : "nvidia,tegra-audio-max98090"
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names : Must include the following entries:
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- pll_a
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- pll_a_out0
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- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
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- nvidia,model : The user-visible name of this sound complex.
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- nvidia,audio-routing : A list of the connections between audio components.
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Each entry is a pair of strings, the first being the connection's sink,
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the second being the connection's source. Valid names for sources and
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sinks are the MAX98090's pins (as documented in its binding), and the jacks
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on the board:
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* Headphones
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* Speakers
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* Mic Jack
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- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
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connected to the CODEC.
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- nvidia,audio-codec : The phandle of the MAX98090 audio codec.
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Optional properties:
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- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
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Example:
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sound {
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compatible = "nvidia,tegra-audio-max98090-venice2",
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"nvidia,tegra-audio-max98090";
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nvidia,model = "NVIDIA Tegra Venice2";
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nvidia,audio-routing =
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"Headphones", "HPR",
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"Headphones", "HPL",
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"Speakers", "SPKR",
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"Speakers", "SPKL",
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"Mic Jack", "MICBIAS",
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"IN34", "Mic Jack";
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nvidia,i2s-controller = <&tegra_i2s1>;
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nvidia,audio-codec = <&acodec>;
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clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
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<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
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<&tegra_car TEGRA124_CLK_EXTERN1>;
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clock-names = "pll_a", "pll_a_out0", "mclk";
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};
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@@ -9,8 +9,13 @@ Required properties:
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Optional properties:
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- simple-audio-card,format : CPU/CODEC common audio format.
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"i2s", "right_j", "left_j" , "dsp_a"
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"dsp_b", "ac97", "pdm", "msb", "lsb"
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"i2s", "right_j", "left_j" , "dsp_a"
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"dsp_b", "ac97", "pdm", "msb", "lsb"
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- simple-audio-routing : A list of the connections between audio components.
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Each entry is a pair of strings, the first being the
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connection's sink, the second being the connection's
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source.
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Required subnodes:
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- simple-audio-card,cpu : CPU sub-node
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@@ -38,6 +43,10 @@ Example:
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "left_j";
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simple-audio-routing =
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"MIC_IN", "Mic Jack",
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"Headphone Jack", "HP_OUT",
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"Ext Spk", "LINE_OUT";
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simple-audio-card,cpu {
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sound-dai = <&sh_fsi2 0>;
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@@ -723,6 +723,7 @@ config ARCH_S3C64XX
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bool "Samsung S3C64XX"
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select ARCH_HAS_CPUFREQ
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select ARCH_REQUIRE_GPIOLIB
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select ARM_AMBA
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select ARM_VIC
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select CLKDEV_LOOKUP
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select CLKSRC_SAMSUNG_PWM
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@@ -17,9 +17,10 @@ config CPU_S3C6410
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help
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Enable S3C6410 CPU support
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config S3C64XX_DMA
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bool "S3C64XX DMA"
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select S3C_DMA
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config S3C64XX_PL080
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bool "S3C64XX DMA using generic PL08x driver"
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select AMBA_PL08X
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select SAMSUNG_DMADEV
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config S3C64XX_SETUP_SDHCI
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bool
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@@ -26,7 +26,7 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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# DMA support
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obj-$(CONFIG_S3C64XX_DMA) += dma.o
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obj-$(CONFIG_S3C64XX_PL080) += pl080.o
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# Device support
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@@ -58,4 +58,9 @@ int __init s3c64xx_pm_late_initcall(void);
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static inline int s3c64xx_pm_late_initcall(void) { return 0; }
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#endif
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#ifdef CONFIG_S3C64XX_PL080
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extern struct pl08x_platform_data s3c64xx_dma0_plat_data;
|
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extern struct pl08x_platform_data s3c64xx_dma1_plat_data;
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#endif
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||||
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#endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */
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File diff suppressed because it is too large
Load Diff
@@ -11,51 +11,48 @@
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#ifndef __ASM_ARCH_DMA_H
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#define __ASM_ARCH_DMA_H __FILE__
|
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|
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#define S3C_DMA_CHANNELS (16)
|
||||
#define S3C64XX_DMA_CHAN(name) ((unsigned long)(name))
|
||||
|
||||
/* see mach-s3c2410/dma.h for notes on dma channel numbers */
|
||||
/* DMA0/SDMA0 */
|
||||
#define DMACH_UART0 S3C64XX_DMA_CHAN("uart0_tx")
|
||||
#define DMACH_UART0_SRC2 S3C64XX_DMA_CHAN("uart0_rx")
|
||||
#define DMACH_UART1 S3C64XX_DMA_CHAN("uart1_tx")
|
||||
#define DMACH_UART1_SRC2 S3C64XX_DMA_CHAN("uart1_rx")
|
||||
#define DMACH_UART2 S3C64XX_DMA_CHAN("uart2_tx")
|
||||
#define DMACH_UART2_SRC2 S3C64XX_DMA_CHAN("uart2_rx")
|
||||
#define DMACH_UART3 S3C64XX_DMA_CHAN("uart3_tx")
|
||||
#define DMACH_UART3_SRC2 S3C64XX_DMA_CHAN("uart3_rx")
|
||||
#define DMACH_PCM0_TX S3C64XX_DMA_CHAN("pcm0_tx")
|
||||
#define DMACH_PCM0_RX S3C64XX_DMA_CHAN("pcm0_rx")
|
||||
#define DMACH_I2S0_OUT S3C64XX_DMA_CHAN("i2s0_tx")
|
||||
#define DMACH_I2S0_IN S3C64XX_DMA_CHAN("i2s0_rx")
|
||||
#define DMACH_SPI0_TX S3C64XX_DMA_CHAN("spi0_tx")
|
||||
#define DMACH_SPI0_RX S3C64XX_DMA_CHAN("spi0_rx")
|
||||
#define DMACH_HSI_I2SV40_TX S3C64XX_DMA_CHAN("i2s2_tx")
|
||||
#define DMACH_HSI_I2SV40_RX S3C64XX_DMA_CHAN("i2s2_rx")
|
||||
|
||||
/* DMA1/SDMA1 */
|
||||
#define DMACH_PCM1_TX S3C64XX_DMA_CHAN("pcm1_tx")
|
||||
#define DMACH_PCM1_RX S3C64XX_DMA_CHAN("pcm1_rx")
|
||||
#define DMACH_I2S1_OUT S3C64XX_DMA_CHAN("i2s1_tx")
|
||||
#define DMACH_I2S1_IN S3C64XX_DMA_CHAN("i2s1_rx")
|
||||
#define DMACH_SPI1_TX S3C64XX_DMA_CHAN("spi1_tx")
|
||||
#define DMACH_SPI1_RX S3C64XX_DMA_CHAN("spi1_rx")
|
||||
#define DMACH_AC97_PCMOUT S3C64XX_DMA_CHAN("ac97_out")
|
||||
#define DMACH_AC97_PCMIN S3C64XX_DMA_CHAN("ac97_in")
|
||||
#define DMACH_AC97_MICIN S3C64XX_DMA_CHAN("ac97_mic")
|
||||
#define DMACH_PWM S3C64XX_DMA_CHAN("pwm")
|
||||
#define DMACH_IRDA S3C64XX_DMA_CHAN("irda")
|
||||
#define DMACH_EXTERNAL S3C64XX_DMA_CHAN("external")
|
||||
#define DMACH_SECURITY_RX S3C64XX_DMA_CHAN("sec_rx")
|
||||
#define DMACH_SECURITY_TX S3C64XX_DMA_CHAN("sec_tx")
|
||||
|
||||
/* Note, for the S3C64XX architecture we keep the DMACH_
|
||||
* defines in the order they are allocated to [S]DMA0/[S]DMA1
|
||||
* so that is easy to do DHACH_ -> DMA controller conversion
|
||||
*/
|
||||
enum dma_ch {
|
||||
/* DMA0/SDMA0 */
|
||||
DMACH_UART0 = 0,
|
||||
DMACH_UART0_SRC2,
|
||||
DMACH_UART1,
|
||||
DMACH_UART1_SRC2,
|
||||
DMACH_UART2,
|
||||
DMACH_UART2_SRC2,
|
||||
DMACH_UART3,
|
||||
DMACH_UART3_SRC2,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_I2S0_OUT,
|
||||
DMACH_I2S0_IN,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_HSI_I2SV40_TX,
|
||||
DMACH_HSI_I2SV40_RX,
|
||||
DMACH_MAX = 32
|
||||
};
|
||||
|
||||
/* DMA1/SDMA1 */
|
||||
DMACH_PCM1_TX = 16,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_I2S1_OUT,
|
||||
DMACH_I2S1_IN,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_AC97_PCMOUT,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_PWM,
|
||||
DMACH_IRDA,
|
||||
DMACH_EXTERNAL,
|
||||
DMACH_RES1,
|
||||
DMACH_RES2,
|
||||
DMACH_SECURITY_RX, /* SDMA1 only */
|
||||
DMACH_SECURITY_TX, /* SDMA1 only */
|
||||
DMACH_MAX /* the end */
|
||||
struct s3c2410_dma_client {
|
||||
char *name;
|
||||
};
|
||||
|
||||
static inline bool samsung_dma_has_circular(void)
|
||||
@@ -65,67 +62,10 @@ static inline bool samsung_dma_has_circular(void)
|
||||
|
||||
static inline bool samsung_dma_is_dmadev(void)
|
||||
{
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
#define S3C2410_DMAF_CIRCULAR (1 << 0)
|
||||
|
||||
#include <plat/dma.h>
|
||||
|
||||
#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
|
||||
|
||||
struct s3c64xx_dma_buff;
|
||||
|
||||
/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
|
||||
* @next: Pointer to next buffer in queue or ring.
|
||||
* @pw: Client provided identifier
|
||||
* @lli: Pointer to hardware descriptor this buffer is associated with.
|
||||
* @lli_dma: Hardare address of the descriptor.
|
||||
*/
|
||||
struct s3c64xx_dma_buff {
|
||||
struct s3c64xx_dma_buff *next;
|
||||
|
||||
void *pw;
|
||||
struct pl080s_lli *lli;
|
||||
dma_addr_t lli_dma;
|
||||
};
|
||||
|
||||
struct s3c64xx_dmac;
|
||||
|
||||
struct s3c2410_dma_chan {
|
||||
unsigned char number; /* number of this dma channel */
|
||||
unsigned char in_use; /* channel allocated */
|
||||
unsigned char bit; /* bit for enable/disable/etc */
|
||||
unsigned char hw_width;
|
||||
unsigned char peripheral;
|
||||
|
||||
unsigned int flags;
|
||||
enum dma_data_direction source;
|
||||
|
||||
|
||||
dma_addr_t dev_addr;
|
||||
|
||||
struct s3c2410_dma_client *client;
|
||||
struct s3c64xx_dmac *dmac; /* pointer to controller */
|
||||
|
||||
void __iomem *regs;
|
||||
|
||||
/* cdriver callbacks */
|
||||
s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
|
||||
s3c2410_dma_opfn_t op_fn; /* channel op callback */
|
||||
|
||||
/* buffer list and information */
|
||||
struct s3c64xx_dma_buff *curr; /* current dma buffer */
|
||||
struct s3c64xx_dma_buff *next; /* next buffer to load */
|
||||
struct s3c64xx_dma_buff *end; /* end of queue */
|
||||
|
||||
/* note, when channel is running in circular mode, curr is the
|
||||
* first buffer enqueued, end is the last and curr is where the
|
||||
* last buffer-done event is set-at. The buffers are not freed
|
||||
* and the last buffer hardware descriptor points back to the
|
||||
* first.
|
||||
*/
|
||||
};
|
||||
|
||||
#include <plat/dma-core.h>
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <plat/dma-ops.h>
|
||||
|
||||
#endif /* __ASM_ARCH_IRQ_H */
|
||||
|
||||
@@ -0,0 +1,244 @@
|
||||
/*
|
||||
* Samsung's S3C64XX generic DMA support using amba-pl08x driver.
|
||||
*
|
||||
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/amba/pl080.h>
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include "regs-sys.h"
|
||||
|
||||
static int pl08x_get_xfer_signal(const struct pl08x_channel_data *cd)
|
||||
{
|
||||
return cd->min_signal;
|
||||
}
|
||||
|
||||
static void pl08x_put_xfer_signal(const struct pl08x_channel_data *cd, int ch)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* DMA0
|
||||
*/
|
||||
|
||||
static struct pl08x_channel_data s3c64xx_dma0_info[] = {
|
||||
{
|
||||
.bus_id = "uart0_tx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart0_rx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart1_tx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart1_rx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart2_tx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart2_rx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart3_tx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart3_rx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "pcm0_tx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "pcm0_rx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2s0_tx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2s0_rx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "spi0_tx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "spi0_rx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2s2_tx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2s2_rx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}
|
||||
};
|
||||
|
||||
struct pl08x_platform_data s3c64xx_dma0_plat_data = {
|
||||
.memcpy_channel = {
|
||||
.bus_id = "memcpy",
|
||||
.cctl_memcpy =
|
||||
(PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
|
||||
PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT |
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT |
|
||||
PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE |
|
||||
PL080_CONTROL_PROT_SYS),
|
||||
},
|
||||
.lli_buses = PL08X_AHB1,
|
||||
.mem_buses = PL08X_AHB1,
|
||||
.get_xfer_signal = pl08x_get_xfer_signal,
|
||||
.put_xfer_signal = pl08x_put_xfer_signal,
|
||||
.slave_channels = s3c64xx_dma0_info,
|
||||
.num_slave_channels = ARRAY_SIZE(s3c64xx_dma0_info),
|
||||
};
|
||||
|
||||
static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0,
|
||||
0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data);
|
||||
|
||||
/*
|
||||
* DMA1
|
||||
*/
|
||||
|
||||
static struct pl08x_channel_data s3c64xx_dma1_info[] = {
|
||||
{
|
||||
.bus_id = "pcm1_tx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "pcm1_rx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2s1_tx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2s1_rx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "spi1_tx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "spi1_rx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ac97_out",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ac97_in",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ac97_mic",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "pwm",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "irda",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "external",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
},
|
||||
};
|
||||
|
||||
struct pl08x_platform_data s3c64xx_dma1_plat_data = {
|
||||
.memcpy_channel = {
|
||||
.bus_id = "memcpy",
|
||||
.cctl_memcpy =
|
||||
(PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
|
||||
PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT |
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT |
|
||||
PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE |
|
||||
PL080_CONTROL_PROT_SYS),
|
||||
},
|
||||
.lli_buses = PL08X_AHB1,
|
||||
.mem_buses = PL08X_AHB1,
|
||||
.get_xfer_signal = pl08x_get_xfer_signal,
|
||||
.put_xfer_signal = pl08x_put_xfer_signal,
|
||||
.slave_channels = s3c64xx_dma1_info,
|
||||
.num_slave_channels = ARRAY_SIZE(s3c64xx_dma1_info),
|
||||
};
|
||||
|
||||
static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0,
|
||||
0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data);
|
||||
|
||||
static int __init s3c64xx_pl080_init(void)
|
||||
{
|
||||
/* Set all DMA configuration to be DMA, not SDMA */
|
||||
writel(0xffffff, S3C64XX_SDMA_SEL);
|
||||
|
||||
if (of_have_populated_dt())
|
||||
return 0;
|
||||
|
||||
amba_device_register(&s3c64xx_dma0_device, &iomem_resource);
|
||||
amba_device_register(&s3c64xx_dma1_device, &iomem_resource);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(s3c64xx_pl080_init);
|
||||
@@ -1468,6 +1468,8 @@ void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
|
||||
pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
|
||||
#if defined(CONFIG_PL330_DMA)
|
||||
pd.filter = pl330_filter;
|
||||
#elif defined(CONFIG_S3C64XX_PL080)
|
||||
pd.filter = pl08x_filter_id;
|
||||
#elif defined(CONFIG_S3C24XX_DMAC)
|
||||
pd.filter = s3c24xx_dma_filter;
|
||||
#endif
|
||||
@@ -1509,8 +1511,10 @@ void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
|
||||
pd.num_cs = num_cs;
|
||||
pd.src_clk_nr = src_clk_nr;
|
||||
pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
|
||||
#ifdef CONFIG_PL330_DMA
|
||||
#if defined(CONFIG_PL330_DMA)
|
||||
pd.filter = pl330_filter;
|
||||
#elif defined(CONFIG_S3C64XX_PL080)
|
||||
pd.filter = pl08x_filter_id;
|
||||
#endif
|
||||
|
||||
s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
|
||||
@@ -1550,8 +1554,10 @@ void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
|
||||
pd.num_cs = num_cs;
|
||||
pd.src_clk_nr = src_clk_nr;
|
||||
pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
|
||||
#ifdef CONFIG_PL330_DMA
|
||||
#if defined(CONFIG_PL330_DMA)
|
||||
pd.filter = pl330_filter;
|
||||
#elif defined(CONFIG_S3C64XX_PL080)
|
||||
pd.filter = pl08x_filter_id;
|
||||
#endif
|
||||
|
||||
s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
|
||||
|
||||
@@ -18,6 +18,12 @@
|
||||
|
||||
#include <mach/dma.h>
|
||||
|
||||
#if defined(CONFIG_PL330_DMA)
|
||||
#define dma_filter pl330_filter
|
||||
#elif defined(CONFIG_S3C64XX_PL080)
|
||||
#define dma_filter pl08x_filter_id
|
||||
#endif
|
||||
|
||||
static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
|
||||
struct samsung_dma_req *param,
|
||||
struct device *dev, char *ch_name)
|
||||
@@ -30,7 +36,7 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
|
||||
if (dev->of_node)
|
||||
return (unsigned)dma_request_slave_channel(dev, ch_name);
|
||||
else
|
||||
return (unsigned)dma_request_channel(mask, pl330_filter,
|
||||
return (unsigned)dma_request_channel(mask, dma_filter,
|
||||
(void *)dma_ch);
|
||||
}
|
||||
|
||||
|
||||
@@ -331,8 +331,8 @@ static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
|
||||
ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
|
||||
ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
|
||||
ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
|
||||
ALIAS(HCLK_DMA1, NULL, "dma1"),
|
||||
ALIAS(HCLK_DMA0, NULL, "dma0"),
|
||||
ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
|
||||
ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
|
||||
ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
|
||||
ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
|
||||
ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user