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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
Pull m68knommu arch update from Greg Ungerer:
"Quite a varied set of changes this time.
- A little more merge cleanup, this time the assembler entry code.
- New sub-architecture support for the ColdFire 5251/5253 and 5441x
CPU families.
- Specific clk support code for the ColdFire 520x and 532x CPU
familes.
- Refactoring of the ColdFire GPIO support.
- PCI bus support for some ColdFire CPUS that have PCI hardware (54xx
family). This showed up a few problems with ColdFire cache,
allocating coherent memory and bi-directional DMA support. Fixes
for those too."
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (21 commits)
m68k: allow PCI bus to be enabled for ColdFire m54xx CPUs
m68k: add PCI bus code support for the ColdFire M54xx SoC family
m68k: add IO access definitions to support PCI on ColdFire platforms
m68k: add PCI bus support definitions for the ColdFire M54xx SoC family
m68k: common PCI support definitions and code
m68k: add support for DMA_BIDIRECTIONAL in dma support functions
m68k: fix ColdFire clear cache operation
m68k: use simpler dma_alloc_coherent() for ColdFire CPUs
m68knommu: platform support for 8390 based ethernet used on some boards
m68knommu: Add clk definitions for m532x.
m68knommu: Add clk definitions for m520x.
m68knommu: Add rtc device for m5441x.
m68knommu: add definitions for the third interrupt controller on devices that don't have a third interrupt controller.
m68knommu: Add support for the Coldfire m5441x.
m68knommu: use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1
coldfire-qspi: Add support for the Coldfire 5251/5253.
m68knommu: Add support for the Coldfire 5251/5253
m68knommu: refactor Coldfire GPIO not to require GPIOLIB, eliminate mcf_gpio_chips.
m68k: merge the MMU and non-MMU versions of the entry.S code
m68k: use jbsr to call functions instead of bsrl
...
This commit is contained in:
Linus Torvalds
@@ -48,6 +48,13 @@ config ISA
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config GENERIC_ISA_DMA
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def_bool ISA
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config PCI
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bool "PCI support"
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depends on M54xx
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help
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Enable the PCI bus. Support for the PCI bus hardware built into the
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ColdFire 547x and 548x processors.
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source "drivers/pci/Kconfig"
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source "drivers/zorro/Kconfig"
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+17
-1
@@ -23,7 +23,7 @@ config M68KCLASSIC
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config COLDFIRE
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bool "Coldfire CPU family support"
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select GENERIC_GPIO
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select ARCH_HAVE_CUSTOM_GPIO_H
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select CPU_HAS_NO_BITFIELDS
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select CPU_HAS_NO_MULDIV64
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@@ -167,6 +167,14 @@ config M5249
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help
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Motorola ColdFire 5249 processor support.
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config M525x
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bool "MCF525x"
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depends on !MMU
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select COLDFIRE_SW_A7
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select HAVE_MBAR
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help
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Freescale (Motorola) Coldfire 5251/5253 processor support.
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config M527x
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bool
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@@ -253,6 +261,14 @@ config M548x
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help
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Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
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config M5441x
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bool "MCF5441x"
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depends on !MMU
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select GENERIC_CLOCKEVENTS
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select HAVE_CACHE_CB
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help
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Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
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endif # COLDFIRE
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@@ -41,6 +41,7 @@ cpuflags-$(CONFIG_M68030) :=
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cpuflags-$(CONFIG_M68020) :=
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cpuflags-$(CONFIG_M68360) := -m68332
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cpuflags-$(CONFIG_M68000) := -m68000
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cpuflags-$(CONFIG_M5441x) := $(call cc-option,-mcpu=54455,-mcfv4e)
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cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200)
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cpuflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200)
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cpuflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
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@@ -50,6 +51,7 @@ cpuflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307)
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cpuflags-$(CONFIG_M5272) := $(call cc-option,-mcpu=5272,-m5307)
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cpuflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307)
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cpuflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307)
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cpuflags-$(CONFIG_M525x) := $(call cc-option,-mcpu=5253,-m5200)
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cpuflags-$(CONFIG_M5249) := $(call cc-option,-mcpu=5249,-m5200)
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cpuflags-$(CONFIG_M520x) := $(call cc-option,-mcpu=5208,-m5200)
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cpuflags-$(CONFIG_M5206e) := $(call cc-option,-mcpu=5206e,-m5200)
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@@ -16,7 +16,48 @@
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#define DCACHE_MAX_ADDR 0
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#define DCACHE_SETMASK 0
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#endif
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#ifndef CACHE_MODE
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#define CACHE_MODE 0
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#define CACR_ICINVA 0
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#define CACR_DCINVA 0
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#define CACR_BCINVA 0
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#endif
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/*
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* ColdFire architecture has no way to clear individual cache lines, so we
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* are stuck invalidating all the cache entries when we want a clear operation.
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*/
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static inline void clear_cf_icache(unsigned long start, unsigned long end)
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{
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__asm__ __volatile__ (
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"movec %0,%%cacr\n\t"
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"nop"
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:
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: "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA));
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}
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static inline void clear_cf_dcache(unsigned long start, unsigned long end)
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{
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__asm__ __volatile__ (
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"movec %0,%%cacr\n\t"
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"nop"
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:
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: "r" (CACHE_MODE | CACR_DCINVA));
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}
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static inline void clear_cf_bcache(unsigned long start, unsigned long end)
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{
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__asm__ __volatile__ (
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"movec %0,%%cacr\n\t"
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"nop"
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:
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: "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA | CACR_DCINVA));
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}
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/*
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* Use the ColdFire cpushl instruction to push (and invalidate) cache lines.
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* The start and end addresses are cache line numbers not memory addresses.
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*/
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static inline void flush_cf_icache(unsigned long start, unsigned long end)
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{
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unsigned long set;
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@@ -33,7 +33,9 @@
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* Set number of channels of DMA on ColdFire for different implementations.
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*/
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#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
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defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
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defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
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defined(CONFIG_M528x) || defined(CONFIG_M525x)
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#define MAX_M68K_DMA_CHANNELS 4
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#elif defined(CONFIG_M5272)
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#define MAX_M68K_DMA_CHANNELS 1
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@@ -486,6 +488,10 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
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extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
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extern void free_dma(unsigned int dmanr); /* release it again */
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#ifdef CONFIG_PCI
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extern int isa_dma_bridge_buggy;
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#else
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#define isa_dma_bridge_buggy (0)
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#endif
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#endif /* _M68K_DMA_H */
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+12
-167
@@ -17,170 +17,9 @@
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#define coldfire_gpio_h
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#include <linux/io.h>
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#include <asm-generic/gpio.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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/*
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* The Freescale Coldfire family is quite varied in how they implement GPIO.
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* Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
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* only one port, others have multiple ports; some have a single data latch
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* for both input and output, others have a separate pin data register to read
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* input; some require a read-modify-write access to change an output, others
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* have set and clear registers for some of the outputs; Some have all the
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* GPIOs in a single control area, others have some GPIOs implemented in
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* different modules.
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*
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* This implementation attempts accommodate the differences while presenting
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* a generic interface that will optimize to as few instructions as possible.
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*/
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M532x) || defined(CONFIG_M54xx)
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/* These parts have GPIO organized by 8 bit ports */
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#define MCFGPIO_PORTTYPE u8
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#define MCFGPIO_PORTSIZE 8
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#define mcfgpio_read(port) __raw_readb(port)
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#define mcfgpio_write(data, port) __raw_writeb(data, port)
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#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
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/* These parts have GPIO organized by 16 bit ports */
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#define MCFGPIO_PORTTYPE u16
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#define MCFGPIO_PORTSIZE 16
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#define mcfgpio_read(port) __raw_readw(port)
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#define mcfgpio_write(data, port) __raw_writew(data, port)
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#elif defined(CONFIG_M5249)
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/* These parts have GPIO organized by 32 bit ports */
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#define MCFGPIO_PORTTYPE u32
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#define MCFGPIO_PORTSIZE 32
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#define mcfgpio_read(port) __raw_readl(port)
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#define mcfgpio_write(data, port) __raw_writel(data, port)
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#endif
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#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
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#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
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#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
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/*
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* These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
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* read-modify-write to change an output and a GPIO module which has separate
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* set/clr registers to directly change outputs with a single write access.
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*/
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#if defined(CONFIG_M528x)
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/*
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* The 528x also has GPIOs in other modules (GPT, QADC) which use
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* read-modify-write as well as those controlled by the EPORT and GPIO modules.
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*/
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#define MCFGPIO_SCR_START 40
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#else
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#define MCFGPIO_SCR_START 8
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#endif
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#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
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mcfgpio_port(gpio - MCFGPIO_SCR_START))
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#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
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mcfgpio_port(gpio - MCFGPIO_SCR_START))
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#else
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#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
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/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
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#define MCFGPIO_SETR_PORT(gpio) 0
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#define MCFGPIO_CLRR_PORT(gpio) 0
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#endif
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/*
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* Coldfire specific helper functions
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*/
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/* return the port pin data register for a gpio */
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static inline u32 __mcf_gpio_ppdr(unsigned gpio)
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{
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M5307) || defined(CONFIG_M5407)
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return MCFSIM_PADAT;
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#elif defined(CONFIG_M5272)
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if (gpio < 16)
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return MCFSIM_PADAT;
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else if (gpio < 32)
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return MCFSIM_PBDAT;
|
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else
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return MCFSIM_PCDAT;
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#elif defined(CONFIG_M5249)
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if (gpio < 32)
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return MCFSIM2_GPIOREAD;
|
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else
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return MCFSIM2_GPIO1READ;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
|
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
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if (gpio < 8)
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return MCFEPORT_EPPDR;
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#if defined(CONFIG_M528x)
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||||
else if (gpio < 16)
|
||||
return MCFGPTA_GPTPORT;
|
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else if (gpio < 24)
|
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return MCFGPTB_GPTPORT;
|
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else if (gpio < 32)
|
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return MCFQADC_PORTQA;
|
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else if (gpio < 40)
|
||||
return MCFQADC_PORTQB;
|
||||
#endif
|
||||
else
|
||||
return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* return the port output data register for a gpio */
|
||||
static inline u32 __mcf_gpio_podr(unsigned gpio)
|
||||
{
|
||||
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
|
||||
defined(CONFIG_M5307) || defined(CONFIG_M5407)
|
||||
return MCFSIM_PADAT;
|
||||
#elif defined(CONFIG_M5272)
|
||||
if (gpio < 16)
|
||||
return MCFSIM_PADAT;
|
||||
else if (gpio < 32)
|
||||
return MCFSIM_PBDAT;
|
||||
else
|
||||
return MCFSIM_PCDAT;
|
||||
#elif defined(CONFIG_M5249)
|
||||
if (gpio < 32)
|
||||
return MCFSIM2_GPIOWRITE;
|
||||
else
|
||||
return MCFSIM2_GPIO1WRITE;
|
||||
#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
|
||||
defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
|
||||
if (gpio < 8)
|
||||
return MCFEPORT_EPDR;
|
||||
#if defined(CONFIG_M528x)
|
||||
else if (gpio < 16)
|
||||
return MCFGPTA_GPTPORT;
|
||||
else if (gpio < 24)
|
||||
return MCFGPTB_GPTPORT;
|
||||
else if (gpio < 32)
|
||||
return MCFQADC_PORTQA;
|
||||
else if (gpio < 40)
|
||||
return MCFQADC_PORTQB;
|
||||
#endif
|
||||
else
|
||||
return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#include <asm/mcfgpio.h>
|
||||
/*
|
||||
* The Generic GPIO functions
|
||||
*
|
||||
@@ -191,7 +30,7 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
|
||||
static inline int gpio_get_value(unsigned gpio)
|
||||
{
|
||||
if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
|
||||
return mcfgpio_read(__mcf_gpio_ppdr(gpio)) & mcfgpio_bit(gpio);
|
||||
return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
|
||||
else
|
||||
return __gpio_get_value(gpio);
|
||||
}
|
||||
@@ -204,12 +43,12 @@ static inline void gpio_set_value(unsigned gpio, int value)
|
||||
MCFGPIO_PORTTYPE data;
|
||||
|
||||
local_irq_save(flags);
|
||||
data = mcfgpio_read(__mcf_gpio_podr(gpio));
|
||||
data = mcfgpio_read(__mcfgpio_podr(gpio));
|
||||
if (value)
|
||||
data |= mcfgpio_bit(gpio);
|
||||
else
|
||||
data &= ~mcfgpio_bit(gpio);
|
||||
mcfgpio_write(data, __mcf_gpio_podr(gpio));
|
||||
mcfgpio_write(data, __mcfgpio_podr(gpio));
|
||||
local_irq_restore(flags);
|
||||
} else {
|
||||
if (value)
|
||||
@@ -225,8 +64,14 @@ static inline void gpio_set_value(unsigned gpio, int value)
|
||||
|
||||
static inline int gpio_to_irq(unsigned gpio)
|
||||
{
|
||||
return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE
|
||||
: __gpio_to_irq(gpio);
|
||||
#if defined(MCFGPIO_IRQ_MIN)
|
||||
if ((gpio >= MCFGPIO_IRQ_MIN) && (gpio < MCFGPIO_IRQ_MAX))
|
||||
#else
|
||||
if (gpio < MCFGPIO_IRQ_MAX)
|
||||
#endif
|
||||
return gpio + MCFGPIO_IRQ_VECBASE;
|
||||
else
|
||||
return __gpio_to_irq(gpio);
|
||||
}
|
||||
|
||||
static inline int irq_to_gpio(unsigned irq)
|
||||
|
||||
@@ -65,7 +65,53 @@
|
||||
|
||||
|
||||
|
||||
#ifdef CONFIG_ISA
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE)
|
||||
|
||||
#define HAVE_ARCH_PIO_SIZE
|
||||
#define PIO_OFFSET 0
|
||||
#define PIO_MASK 0xffff
|
||||
#define PIO_RESERVED 0x10000
|
||||
|
||||
u8 mcf_pci_inb(u32 addr);
|
||||
u16 mcf_pci_inw(u32 addr);
|
||||
u32 mcf_pci_inl(u32 addr);
|
||||
void mcf_pci_insb(u32 addr, u8 *buf, u32 len);
|
||||
void mcf_pci_insw(u32 addr, u16 *buf, u32 len);
|
||||
void mcf_pci_insl(u32 addr, u32 *buf, u32 len);
|
||||
|
||||
void mcf_pci_outb(u8 v, u32 addr);
|
||||
void mcf_pci_outw(u16 v, u32 addr);
|
||||
void mcf_pci_outl(u32 v, u32 addr);
|
||||
void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len);
|
||||
void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len);
|
||||
void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len);
|
||||
|
||||
#define inb mcf_pci_inb
|
||||
#define inb_p mcf_pci_inb
|
||||
#define inw mcf_pci_inw
|
||||
#define inw_p mcf_pci_inw
|
||||
#define inl mcf_pci_inl
|
||||
#define inl_p mcf_pci_inl
|
||||
#define insb mcf_pci_insb
|
||||
#define insw mcf_pci_insw
|
||||
#define insl mcf_pci_insl
|
||||
|
||||
#define outb mcf_pci_outb
|
||||
#define outb_p mcf_pci_outb
|
||||
#define outw mcf_pci_outw
|
||||
#define outw_p mcf_pci_outw
|
||||
#define outl mcf_pci_outl
|
||||
#define outl_p mcf_pci_outl
|
||||
#define outsb mcf_pci_outsb
|
||||
#define outsw mcf_pci_outsw
|
||||
#define outsl mcf_pci_outsl
|
||||
|
||||
#define readb(addr) in_8(addr)
|
||||
#define writeb(v, addr) out_8((addr), (v))
|
||||
#define readw(addr) in_le16(addr)
|
||||
#define writew(v, addr) out_le16((addr), (v))
|
||||
|
||||
#elif defined(CONFIG_ISA)
|
||||
|
||||
#if MULTI_ISA == 0
|
||||
#undef MULTI_ISA
|
||||
@@ -340,4 +386,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
|
||||
*/
|
||||
#define xlate_dev_kmem_ptr(p) p
|
||||
|
||||
#define ioport_map(port, nr) ((void __iomem *)(port))
|
||||
|
||||
#endif /* _IO_H */
|
||||
|
||||
@@ -42,6 +42,9 @@
|
||||
#define MCFINTC1_SIMR (0)
|
||||
#define MCFINTC1_CIMR (0)
|
||||
#define MCFINTC1_ICR0 (0)
|
||||
#define MCFINTC2_SIMR (0)
|
||||
#define MCFINTC2_CIMR (0)
|
||||
#define MCFINTC2_ICR0 (0)
|
||||
|
||||
#define MCFINT_VECBASE 64
|
||||
#define MCFINT_UART0 26 /* Interrupt number for UART0 */
|
||||
@@ -62,6 +65,7 @@
|
||||
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
|
||||
|
||||
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
|
||||
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
|
||||
|
||||
/*
|
||||
* SDRAM configuration registers.
|
||||
@@ -186,5 +190,15 @@
|
||||
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
|
||||
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
|
||||
|
||||
/*
|
||||
* Power Management.
|
||||
*/
|
||||
#define MCFPM_WCR 0xfc040013
|
||||
#define MCFPM_PPMSR0 0xfc04002c
|
||||
#define MCFPM_PPMCR0 0xfc04002d
|
||||
#define MCFPM_PPMHR0 0xfc040030
|
||||
#define MCFPM_PPMLR0 0xfc040034
|
||||
#define MCFPM_LPCR 0xfc0a0007
|
||||
|
||||
/****************************************************************************/
|
||||
#endif /* m520xsim_h */
|
||||
|
||||
@@ -52,6 +52,7 @@
|
||||
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
|
||||
|
||||
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
|
||||
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
|
||||
|
||||
/*
|
||||
* SDRAM configuration registers.
|
||||
|
||||
@@ -0,0 +1,194 @@
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* m525xsim.h -- ColdFire 525x System Integration Module support.
|
||||
*
|
||||
* (C) Copyright 2012, Steven king <sfking@fdwdc.com>
|
||||
* (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
|
||||
*/
|
||||
|
||||
/****************************************************************************/
|
||||
#ifndef m525xsim_h
|
||||
#define m525xsim_h
|
||||
/****************************************************************************/
|
||||
|
||||
#define CPU_NAME "COLDFIRE(m525x)"
|
||||
#define CPU_INSTR_PER_JIFFY 3
|
||||
#define MCF_BUSCLK (MCF_CLK / 2)
|
||||
|
||||
#include <asm/m52xxacr.h>
|
||||
|
||||
/*
|
||||
* The 525x has a second MBAR region, define its address.
|
||||
*/
|
||||
#define MCF_MBAR2 0x80000000
|
||||
|
||||
/*
|
||||
* Define the 525x SIM register set addresses.
|
||||
*/
|
||||
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
|
||||
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
|
||||
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
|
||||
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
|
||||
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
|
||||
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
|
||||
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
|
||||
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
|
||||
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
|
||||
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
|
||||
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
|
||||
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
|
||||
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
|
||||
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
|
||||
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
|
||||
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
|
||||
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
|
||||
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
|
||||
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
|
||||
|
||||
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
|
||||
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
|
||||
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
|
||||
|
||||
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
|
||||
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
|
||||
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
|
||||
|
||||
/*
|
||||
* Secondary Interrupt Controller (in MBAR2)
|
||||
*/
|
||||
#define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
|
||||
#define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
|
||||
#define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
|
||||
#define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
|
||||
#define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
|
||||
#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
|
||||
#define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
|
||||
#define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
|
||||
#define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
|
||||
|
||||
#define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \
|
||||
((((i) - MCFINTC2_VECBASE) / 8) * 4))
|
||||
#define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4))
|
||||
|
||||
/*
|
||||
* Timer module.
|
||||
*/
|
||||
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
|
||||
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
|
||||
|
||||
/*
|
||||
* UART module.
|
||||
*/
|
||||
#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
|
||||
#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
|
||||
|
||||
/*
|
||||
* QSPI module.
|
||||
*/
|
||||
#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
|
||||
#define MCFQSPI_SIZE 0x40 /* Register set size */
|
||||
|
||||
|
||||
#define MCFQSPI_CS0 15
|
||||
#define MCFQSPI_CS1 16
|
||||
#define MCFQSPI_CS2 24
|
||||
#define MCFQSPI_CS3 28
|
||||
|
||||
/*
|
||||
* I2C module.
|
||||
*/
|
||||
#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */
|
||||
#define MCFI2C_SIZE0 0x20 /* Register set size */
|
||||
|
||||
#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
|
||||
#define MCFI2C_SIZE1 0x20 /* Register set size */
|
||||
/*
|
||||
* DMA unit base addresses.
|
||||
*/
|
||||
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
|
||||
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
|
||||
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
|
||||
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
|
||||
|
||||
/*
|
||||
* Some symbol defines for the above...
|
||||
*/
|
||||
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
|
||||
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
|
||||
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
|
||||
#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
|
||||
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
|
||||
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
|
||||
#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
|
||||
#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
|
||||
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
|
||||
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
|
||||
#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
|
||||
|
||||
/*
|
||||
* Define system peripheral IRQ usage.
|
||||
*/
|
||||
#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
|
||||
#define MCF_IRQ_I2C0 29
|
||||
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
|
||||
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
|
||||
|
||||
#define MCF_IRQ_UART0 73 /* UART0 */
|
||||
#define MCF_IRQ_UART1 74 /* UART1 */
|
||||
|
||||
/*
|
||||
* Define the base interrupt for the second interrupt controller.
|
||||
* We set it to 128, out of the way of the base interrupts, and plenty
|
||||
* of room for its 64 interrupts.
|
||||
*/
|
||||
#define MCFINTC2_VECBASE 128
|
||||
|
||||
#define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32)
|
||||
#define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33)
|
||||
#define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34)
|
||||
#define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35)
|
||||
#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
|
||||
#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
|
||||
#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
|
||||
|
||||
#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
|
||||
#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
|
||||
|
||||
/*
|
||||
* General purpose IO registers (in MBAR2).
|
||||
*/
|
||||
#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
|
||||
#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
|
||||
#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
|
||||
#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
|
||||
#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
|
||||
#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
|
||||
#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
|
||||
#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
|
||||
|
||||
#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
|
||||
#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
|
||||
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
|
||||
|
||||
/*
|
||||
* Generic GPIO support
|
||||
*/
|
||||
#define MCFGPIO_PIN_MAX 64
|
||||
#define MCFGPIO_IRQ_MAX 7
|
||||
#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
|
||||
|
||||
/****************************************************************************/
|
||||
#endif /* m525xsim_h */
|
||||
@@ -60,6 +60,7 @@
|
||||
#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
|
||||
|
||||
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
|
||||
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
|
||||
|
||||
/*
|
||||
* SDRAM configuration registers.
|
||||
|
||||
@@ -52,7 +52,7 @@
|
||||
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
|
||||
|
||||
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
|
||||
|
||||
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
|
||||
/*
|
||||
* SDRAM configuration registers.
|
||||
*/
|
||||
|
||||
@@ -82,6 +82,9 @@
|
||||
#define MCFINTC1_SIMR 0xFC04C01C
|
||||
#define MCFINTC1_CIMR 0xFC04C01D
|
||||
#define MCFINTC1_ICR0 0xFC04C040
|
||||
#define MCFINTC2_SIMR (0)
|
||||
#define MCFINTC2_CIMR (0)
|
||||
#define MCFINTC2_ICR0 (0)
|
||||
|
||||
#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
|
||||
#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
|
||||
@@ -135,6 +138,20 @@
|
||||
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
|
||||
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
|
||||
|
||||
|
||||
/*
|
||||
* Power Management
|
||||
*/
|
||||
#define MCFPM_WCR 0xfc040013
|
||||
#define MCFPM_PPMSR0 0xfc04002c
|
||||
#define MCFPM_PPMCR0 0xfc04002d
|
||||
#define MCFPM_PPMSR1 0xfc04002e
|
||||
#define MCFPM_PPMCR1 0xfc04002f
|
||||
#define MCFPM_PPMHR0 0xfc040030
|
||||
#define MCFPM_PPMLR0 0xfc040034
|
||||
#define MCFPM_PPMHR1 0xfc040038
|
||||
#define MCFPM_LPCR 0xec090007
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Inter-IC (I2C) Module
|
||||
|
||||
@@ -0,0 +1,276 @@
|
||||
/*
|
||||
* m5441xsim.h -- Coldfire 5441x register definitions
|
||||
*
|
||||
* (C) Copyright 2012, Steven King <sfking@fdwdc.com>
|
||||
*/
|
||||
|
||||
#ifndef m5441xsim_h
|
||||
#define m5441xsim_h
|
||||
|
||||
#define CPU_NAME "COLDFIRE(m5441x)"
|
||||
#define CPU_INSTR_PER_JIFFY 2
|
||||
#define MCF_BUSCLK (MCF_CLK / 2)
|
||||
|
||||
#include <asm/m54xxacr.h>
|
||||
|
||||
/*
|
||||
* Reset Controller Module.
|
||||
*/
|
||||
|
||||
#define MCF_RCR 0xec090000
|
||||
#define MCF_RSR 0xec090001
|
||||
|
||||
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
|
||||
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
|
||||
|
||||
/*
|
||||
* Interrupt Controller Modules.
|
||||
*/
|
||||
/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
|
||||
#define MCFINT_VECBASE 64
|
||||
#define MCFINT0_VECBASE MCFINT_VECBASE
|
||||
#define MCFINT1_VECBASE (MCFINT0_VECBASE + 64)
|
||||
#define MCFINT2_VECBASE (MCFINT1_VECBASE + 64)
|
||||
|
||||
/* interrupt controller 0 */
|
||||
#define MCFINTC0_SIMR 0xfc04801c
|
||||
#define MCFINTC0_CIMR 0xfc04801d
|
||||
#define MCFINTC0_ICR0 0xfc048040
|
||||
/* interrupt controller 1 */
|
||||
#define MCFINTC1_SIMR 0xfc04c01c
|
||||
#define MCFINTC1_CIMR 0xfc04c01d
|
||||
#define MCFINTC1_ICR0 0xfc04c040
|
||||
/* interrupt controller 2 */
|
||||
#define MCFINTC2_SIMR 0xfc05001c
|
||||
#define MCFINTC2_CIMR 0xfc05001d
|
||||
#define MCFINTC2_ICR0 0xfc050040
|
||||
|
||||
/* on interrupt controller 0 */
|
||||
#define MCFINT0_EPORT0 1
|
||||
#define MCFINT0_UART0 26
|
||||
#define MCFINT0_UART1 27
|
||||
#define MCFINT0_UART2 28
|
||||
#define MCFINT0_UART3 29
|
||||
#define MCFINT0_I2C0 30
|
||||
#define MCFINT0_DSPI0 31
|
||||
|
||||
#define MCFINT0_TIMER0 32
|
||||
#define MCFINT0_TIMER1 33
|
||||
#define MCFINT0_TIMER2 34
|
||||
#define MCFINT0_TIMER3 35
|
||||
|
||||
#define MCFINT0_FECRX0 36
|
||||
#define MCFINT0_FECTX0 40
|
||||
#define MCFINT0_FECENTC0 42
|
||||
|
||||
#define MCFINT0_FECRX1 49
|
||||
#define MCFINT0_FECTX1 53
|
||||
#define MCFINT0_FECENTC1 55
|
||||
|
||||
/* on interrupt controller 1 */
|
||||
#define MCFINT1_UART4 48
|
||||
#define MCFINT1_UART5 49
|
||||
#define MCFINT1_UART6 50
|
||||
#define MCFINT1_UART7 51
|
||||
#define MCFINT1_UART8 52
|
||||
#define MCFINT1_UART9 53
|
||||
#define MCFINT1_DSPI1 54
|
||||
#define MCFINT1_DSPI2 55
|
||||
#define MCFINT1_DSPI3 56
|
||||
#define MCFINT1_I2C1 57
|
||||
#define MCFINT1_I2C2 58
|
||||
#define MCFINT1_I2C3 59
|
||||
#define MCFINT1_I2C4 60
|
||||
#define MCFINT1_I2C5 61
|
||||
|
||||
/* on interrupt controller 2 */
|
||||
#define MCFINT2_PIT0 13
|
||||
#define MCFINT2_PIT1 14
|
||||
#define MCFINT2_PIT2 15
|
||||
#define MCFINT2_PIT3 16
|
||||
#define MCFINT2_RTC 26
|
||||
|
||||
/*
|
||||
* PIT timer module.
|
||||
*/
|
||||
#define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */
|
||||
#define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
|
||||
#define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */
|
||||
#define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */
|
||||
|
||||
|
||||
#define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1)
|
||||
|
||||
/*
|
||||
* Power Management
|
||||
*/
|
||||
#define MCFPM_WCR 0xfc040013
|
||||
#define MCFPM_PPMSR0 0xfc04002c
|
||||
#define MCFPM_PPMCR0 0xfc04002d
|
||||
#define MCFPM_PPMSR1 0xfc04002e
|
||||
#define MCFPM_PPMCR1 0xfc04002f
|
||||
#define MCFPM_PPMHR0 0xfc040030
|
||||
#define MCFPM_PPMLR0 0xfc040034
|
||||
#define MCFPM_PPMHR1 0xfc040038
|
||||
#define MCFPM_PPMLR1 0xfc04003c
|
||||
#define MCFPM_LPCR 0xec090007
|
||||
/*
|
||||
* UART module.
|
||||
*/
|
||||
#define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */
|
||||
#define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */
|
||||
#define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */
|
||||
#define MCFUART_BASE4 0xec060000 /* Base address of UART4 */
|
||||
#define MCFUART_BASE5 0xec064000 /* Base address of UART5 */
|
||||
#define MCFUART_BASE6 0xec068000 /* Base address of UART6 */
|
||||
#define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */
|
||||
#define MCFUART_BASE8 0xec070000 /* Base address of UART8 */
|
||||
#define MCFUART_BASE9 0xec074000 /* Base address of UART9 */
|
||||
|
||||
#define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0)
|
||||
#define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1)
|
||||
#define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2)
|
||||
#define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3)
|
||||
#define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4)
|
||||
#define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5)
|
||||
#define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6)
|
||||
#define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7)
|
||||
#define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8)
|
||||
#define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9)
|
||||
/*
|
||||
* FEC modules.
|
||||
*/
|
||||
#define MCFFEC_BASE0 0xfc0d4000
|
||||
#define MCFFEC_SIZE0 0x800
|
||||
#define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0)
|
||||
#define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0)
|
||||
#define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0)
|
||||
|
||||
#define MCFFEC_BASE1 0xfc0d8000
|
||||
#define MCFFEC_SIZE1 0x800
|
||||
#define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1)
|
||||
#define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1)
|
||||
#define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1)
|
||||
/*
|
||||
* I2C modules.
|
||||
*/
|
||||
#define MCFI2C_BASE0 0xfc058000
|
||||
#define MCFI2C_SIZE0 0x20
|
||||
#define MCFI2C_BASE1 0xfc038000
|
||||
#define MCFI2C_SIZE1 0x20
|
||||
#define MCFI2C_BASE2 0xec010000
|
||||
#define MCFI2C_SIZE2 0x20
|
||||
#define MCFI2C_BASE3 0xec014000
|
||||
#define MCFI2C_SIZE3 0x20
|
||||
#define MCFI2C_BASE4 0xec018000
|
||||
#define MCFI2C_SIZE4 0x20
|
||||
#define MCFI2C_BASE5 0xec01c000
|
||||
#define MCFI2C_SIZE5 0x20
|
||||
|
||||
#define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0)
|
||||
#define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1)
|
||||
#define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2)
|
||||
#define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3)
|
||||
#define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4)
|
||||
#define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5)
|
||||
/*
|
||||
* EPORT Module.
|
||||
*/
|
||||
#define MCFEPORT_EPPAR 0xfc090000
|
||||
#define MCFEPORT_EPIER 0xfc090003
|
||||
#define MCFEPORT_EPFR 0xfc090006
|
||||
/*
|
||||
* RTC Module.
|
||||
*/
|
||||
#define MCFRTC_BASE 0xfc0a8000
|
||||
#define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000)
|
||||
#define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC)
|
||||
|
||||
/*
|
||||
* GPIO Module.
|
||||
*/
|
||||
#define MCFGPIO_PODR_A 0xec094000
|
||||
#define MCFGPIO_PODR_B 0xec094001
|
||||
#define MCFGPIO_PODR_C 0xec094002
|
||||
#define MCFGPIO_PODR_D 0xec094003
|
||||
#define MCFGPIO_PODR_E 0xec094004
|
||||
#define MCFGPIO_PODR_F 0xec094005
|
||||
#define MCFGPIO_PODR_G 0xec094006
|
||||
#define MCFGPIO_PODR_H 0xec094007
|
||||
#define MCFGPIO_PODR_I 0xec094008
|
||||
#define MCFGPIO_PODR_J 0xec094009
|
||||
#define MCFGPIO_PODR_K 0xec09400a
|
||||
|
||||
#define MCFGPIO_PDDR_A 0xec09400c
|
||||
#define MCFGPIO_PDDR_B 0xec09400d
|
||||
#define MCFGPIO_PDDR_C 0xec09400e
|
||||
#define MCFGPIO_PDDR_D 0xec09400f
|
||||
#define MCFGPIO_PDDR_E 0xec094010
|
||||
#define MCFGPIO_PDDR_F 0xec094011
|
||||
#define MCFGPIO_PDDR_G 0xec094012
|
||||
#define MCFGPIO_PDDR_H 0xec094013
|
||||
#define MCFGPIO_PDDR_I 0xec094014
|
||||
#define MCFGPIO_PDDR_J 0xec094015
|
||||
#define MCFGPIO_PDDR_K 0xec094016
|
||||
|
||||
#define MCFGPIO_PPDSDR_A 0xec094018
|
||||
#define MCFGPIO_PPDSDR_B 0xec094019
|
||||
#define MCFGPIO_PPDSDR_C 0xec09401a
|
||||
#define MCFGPIO_PPDSDR_D 0xec09401b
|
||||
#define MCFGPIO_PPDSDR_E 0xec09401c
|
||||
#define MCFGPIO_PPDSDR_F 0xec09401d
|
||||
#define MCFGPIO_PPDSDR_G 0xec09401e
|
||||
#define MCFGPIO_PPDSDR_H 0xec09401f
|
||||
#define MCFGPIO_PPDSDR_I 0xec094020
|
||||
#define MCFGPIO_PPDSDR_J 0xec094021
|
||||
#define MCFGPIO_PPDSDR_K 0xec094022
|
||||
|
||||
#define MCFGPIO_PCLRR_A 0xec094024
|
||||
#define MCFGPIO_PCLRR_B 0xec094025
|
||||
#define MCFGPIO_PCLRR_C 0xec094026
|
||||
#define MCFGPIO_PCLRR_D 0xec094027
|
||||
#define MCFGPIO_PCLRR_E 0xec094028
|
||||
#define MCFGPIO_PCLRR_F 0xec094029
|
||||
#define MCFGPIO_PCLRR_G 0xec09402a
|
||||
#define MCFGPIO_PCLRR_H 0xec09402b
|
||||
#define MCFGPIO_PCLRR_I 0xec09402c
|
||||
#define MCFGPIO_PCLRR_J 0xec09402d
|
||||
#define MCFGPIO_PCLRR_K 0xec09402e
|
||||
|
||||
#define MCFGPIO_PAR_FBCTL 0xec094048
|
||||
#define MCFGPIO_PAR_BE 0xec094049
|
||||
#define MCFGPIO_PAR_CS 0xec09404a
|
||||
#define MCFGPIO_PAR_CANI2C 0xec09404b
|
||||
#define MCFGPIO_PAR_IRQ0H 0xec09404c
|
||||
#define MCFGPIO_PAR_IRQ0L 0xec09404d
|
||||
#define MCFGPIO_PAR_DSPIOWH 0xec09404e
|
||||
#define MCFGPIO_PAR_DSPIOWL 0xec09404f
|
||||
#define MCFGPIO_PAR_TIMER 0xec094050
|
||||
#define MCFGPIO_PAR_UART2 0xec094051
|
||||
#define MCFGPIO_PAR_UART1 0xec094052
|
||||
#define MCFGPIO_PAR_UART0 0xec094053
|
||||
#define MCFGPIO_PAR_SDHCH 0xec094054
|
||||
#define MCFGPIO_PAR_SDHCL 0xec094055
|
||||
#define MCFGPIO_PAR_SIMP0H 0xec094056
|
||||
#define MCFGPIO_PAR_SIMP0L 0xec094057
|
||||
#define MCFGPIO_PAR_SSI0H 0xec094058
|
||||
#define MCFGPIO_PAR_SSI0L 0xec094059
|
||||
#define MCFGPIO_PAR_DEBUGH1 0xec09405a
|
||||
#define MCFGPIO_PAR_DEBUGH0 0xec09405b
|
||||
#define MCFGPIO_PAR_DEBUGl 0xec09405c
|
||||
#define MCFGPIO_PAR_FEC 0xec09405e
|
||||
|
||||
/* generalization for generic gpio support */
|
||||
#define MCFGPIO_PODR MCFGPIO_PODR_A
|
||||
#define MCFGPIO_PDDR MCFGPIO_PDDR_A
|
||||
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A
|
||||
#define MCFGPIO_SETR MCFGPIO_PPDSDR_A
|
||||
#define MCFGPIO_CLRR MCFGPIO_PCLRR_A
|
||||
|
||||
#define MCFGPIO_IRQ_MIN 17
|
||||
#define MCFGPIO_IRQ_MAX 24
|
||||
#define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
|
||||
#define MCFGPIO_PIN_MAX 87
|
||||
|
||||
#endif /* m5441xsim_h */
|
||||
@@ -55,6 +55,10 @@
|
||||
#define ICACHE_SIZE 0x8000 /* instruction - 32k */
|
||||
#define DCACHE_SIZE 0x8000 /* data - 32k */
|
||||
|
||||
#elif defined(CONFIG_M5441x)
|
||||
|
||||
#define ICACHE_SIZE 0x2000 /* instruction - 8k */
|
||||
#define DCACHE_SIZE 0x2000 /* data - 8k */
|
||||
#endif
|
||||
|
||||
#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
|
||||
|
||||
@@ -0,0 +1,138 @@
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* m54xxpci.h -- ColdFire 547x and 548x PCI bus support
|
||||
*
|
||||
* (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
/****************************************************************************/
|
||||
#ifndef M54XXPCI_H
|
||||
#define M54XXPCI_H
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* The core set of PCI support registers are mapped into the MBAR region.
|
||||
*/
|
||||
#define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
|
||||
#define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
|
||||
#define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
|
||||
#define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
|
||||
#define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
|
||||
#define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
|
||||
#define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
|
||||
#define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
|
||||
#define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
|
||||
#define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
|
||||
#define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */
|
||||
|
||||
#define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */
|
||||
#define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */
|
||||
#define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */
|
||||
#define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */
|
||||
#define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */
|
||||
#define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */
|
||||
#define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */
|
||||
#define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */
|
||||
#define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */
|
||||
#define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */
|
||||
#define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */
|
||||
|
||||
#define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
|
||||
#define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
|
||||
#define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
|
||||
#define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
|
||||
#define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
|
||||
#define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
|
||||
#define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
|
||||
#define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
|
||||
#define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
|
||||
#define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */
|
||||
#define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
|
||||
#define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
|
||||
#define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
|
||||
#define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
|
||||
|
||||
#define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */
|
||||
#define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */
|
||||
#define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */
|
||||
#define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */
|
||||
#define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */
|
||||
#define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */
|
||||
#define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */
|
||||
#define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */
|
||||
#define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */
|
||||
#define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */
|
||||
#define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */
|
||||
#define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */
|
||||
#define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
|
||||
|
||||
#define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
|
||||
#define PASR (COFNIG_MBAR + 0xc04) /* PCI arbiter status */
|
||||
|
||||
/*
|
||||
* Definitions for the Global status and control register.
|
||||
*/
|
||||
#define PCIGSCR_PE 0x20000000 /* Parity error detected */
|
||||
#define PCIGSCR_SE 0x10000000 /* System error detected */
|
||||
#define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */
|
||||
#define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */
|
||||
#define PCIGSCR_SEE 0x00001000 /* System error intr enable */
|
||||
#define PCIGSCR_RESET 0x00000001 /* Reset bit */
|
||||
|
||||
/*
|
||||
* Bit definitions for the PCICAR configuration address register.
|
||||
*/
|
||||
#define PCICAR_E 0x80000000 /* Enable config space */
|
||||
#define PCICAR_BUSN 16 /* Move bus bits */
|
||||
#define PCICAR_DEVFNN 8 /* Move devfn bits */
|
||||
#define PCICAR_DWORDN 0 /* Move dword bits */
|
||||
|
||||
/*
|
||||
* The initiator windows hold the memory and IO mapping information.
|
||||
* This macro creates the register values from the desired addresses.
|
||||
*/
|
||||
#define WXBTAR(hostaddr, pciaddr, size) \
|
||||
(((hostaddr) & 0xff000000) | \
|
||||
((((size) - 1) & 0xff000000) >> 8) | \
|
||||
(((pciaddr) & 0xff000000) >> 16))
|
||||
|
||||
#define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */
|
||||
#define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */
|
||||
#define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */
|
||||
#define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */
|
||||
#define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */
|
||||
#define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */
|
||||
|
||||
#define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */
|
||||
#define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */
|
||||
#define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */
|
||||
#define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */
|
||||
#define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */
|
||||
#define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */
|
||||
|
||||
/*
|
||||
* Bit definitions for the PCIBATR registers.
|
||||
*/
|
||||
#define PCITBATR0_E 0x00000001 /* Enable window 0 */
|
||||
#define PCITBATR1_E 0x00000001 /* Enable window 1 */
|
||||
|
||||
/*
|
||||
* PCI arbiter support definitions and macros.
|
||||
*/
|
||||
#define PACR_INTMPRI 0x00000001
|
||||
#define PACR_EXTMPRI(x) (((x) & 0x1f) << 1)
|
||||
#define PACR_INTMINTE 0x00010000
|
||||
#define PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
|
||||
#define PACR_PKMD 0x40000000
|
||||
#define PACR_DS 0x80000000
|
||||
|
||||
#define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */
|
||||
#define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */
|
||||
|
||||
/****************************************************************************/
|
||||
#endif /* M54XXPCI_H */
|
||||
@@ -81,4 +81,7 @@
|
||||
#define MCF_PAR_PSC_RTS_RTS (0x30)
|
||||
#define MCF_PAR_PSC_CANRX (0x40)
|
||||
|
||||
#define MCF_PAR_PCIBG (CONFIG_MBAR + 0xa48) /* PCI bus grant */
|
||||
#define MCF_PAR_PCIBR (CONFIG_MBAR + 0xa4a) /* PCI */
|
||||
|
||||
#endif /* m54xxsim_h */
|
||||
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* mcfclk.h -- coldfire specific clock structure
|
||||
*/
|
||||
|
||||
|
||||
#ifndef mcfclk_h
|
||||
#define mcfclk_h
|
||||
|
||||
struct clk;
|
||||
|
||||
#ifdef MCFPM_PPMCR0
|
||||
struct clk_ops {
|
||||
void (*enable)(struct clk *);
|
||||
void (*disable)(struct clk *);
|
||||
};
|
||||
|
||||
struct clk {
|
||||
const char *name;
|
||||
struct clk_ops *clk_ops;
|
||||
unsigned long rate;
|
||||
unsigned long enabled;
|
||||
u8 slot;
|
||||
};
|
||||
|
||||
extern struct clk *mcf_clks[];
|
||||
extern struct clk_ops clk_ops0;
|
||||
#ifdef MCFPM_PPMCR1
|
||||
extern struct clk_ops clk_ops1;
|
||||
#endif /* MCFPM_PPMCR1 */
|
||||
|
||||
#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
|
||||
static struct clk __clk_##clk_bank##_##clk_slot = { \
|
||||
.name = clk_name, \
|
||||
.clk_ops = &clk_ops##clk_bank, \
|
||||
.rate = clk_rate, \
|
||||
.slot = clk_slot, \
|
||||
}
|
||||
|
||||
void __clk_init_enabled(struct clk *);
|
||||
void __clk_init_disabled(struct clk *);
|
||||
#endif /* MCFPM_PPMCR0 */
|
||||
|
||||
#endif /* mcfclk_h */
|
||||
+275
-68
@@ -16,82 +16,289 @@
|
||||
#ifndef mcfgpio_h
|
||||
#define mcfgpio_h
|
||||
|
||||
#include <linux/io.h>
|
||||
#ifdef CONFIG_GPIOLIB
|
||||
#include <asm-generic/gpio.h>
|
||||
#else
|
||||
|
||||
struct mcf_gpio_chip {
|
||||
struct gpio_chip gpio_chip;
|
||||
void __iomem *pddr;
|
||||
void __iomem *podr;
|
||||
void __iomem *ppdr;
|
||||
void __iomem *setr;
|
||||
void __iomem *clrr;
|
||||
const u8 *gpio_to_pinmux;
|
||||
};
|
||||
int __mcfgpio_get_value(unsigned gpio);
|
||||
void __mcfgpio_set_value(unsigned gpio, int value);
|
||||
int __mcfgpio_direction_input(unsigned gpio);
|
||||
int __mcfgpio_direction_output(unsigned gpio, int value);
|
||||
int __mcfgpio_request(unsigned gpio);
|
||||
void __mcfgpio_free(unsigned gpio);
|
||||
|
||||
extern struct mcf_gpio_chip mcf_gpio_chips[];
|
||||
extern unsigned int mcf_gpio_chips_size;
|
||||
/* our alternate 'gpiolib' functions */
|
||||
static inline int __gpio_get_value(unsigned gpio)
|
||||
{
|
||||
if (gpio < MCFGPIO_PIN_MAX)
|
||||
return __mcfgpio_get_value(gpio);
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline void __gpio_set_value(unsigned gpio, int value)
|
||||
{
|
||||
if (gpio < MCFGPIO_PIN_MAX)
|
||||
__mcfgpio_set_value(gpio, value);
|
||||
}
|
||||
|
||||
static inline int __gpio_cansleep(unsigned gpio)
|
||||
{
|
||||
if (gpio < MCFGPIO_PIN_MAX)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int __gpio_to_irq(unsigned gpio)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int gpio_direction_input(unsigned gpio)
|
||||
{
|
||||
if (gpio < MCFGPIO_PIN_MAX)
|
||||
return __mcfgpio_direction_input(gpio);
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int gpio_direction_output(unsigned gpio, int value)
|
||||
{
|
||||
if (gpio < MCFGPIO_PIN_MAX)
|
||||
return __mcfgpio_direction_output(gpio, value);
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int gpio_request(unsigned gpio, const char *label)
|
||||
{
|
||||
if (gpio < MCFGPIO_PIN_MAX)
|
||||
return __mcfgpio_request(gpio);
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline void gpio_free(unsigned gpio)
|
||||
{
|
||||
if (gpio < MCFGPIO_PIN_MAX)
|
||||
__mcfgpio_free(gpio);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GPIOLIB */
|
||||
|
||||
int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
|
||||
int mcf_gpio_get_value(struct gpio_chip *, unsigned);
|
||||
int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
|
||||
void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);
|
||||
void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
|
||||
int mcf_gpio_request(struct gpio_chip *, unsigned);
|
||||
void mcf_gpio_free(struct gpio_chip *, unsigned);
|
||||
|
||||
/*
|
||||
* Define macros to ease the pain of setting up the GPIO tables. There
|
||||
* are two cases we need to deal with here, they cover all currently
|
||||
* available ColdFire GPIO hardware. There are of course minor differences
|
||||
* in the layout and number of bits in each ColdFire part, but the macros
|
||||
* take all that in.
|
||||
* The Freescale Coldfire family is quite varied in how they implement GPIO.
|
||||
* Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
|
||||
* only one port, others have multiple ports; some have a single data latch
|
||||
* for both input and output, others have a separate pin data register to read
|
||||
* input; some require a read-modify-write access to change an output, others
|
||||
* have set and clear registers for some of the outputs; Some have all the
|
||||
* GPIOs in a single control area, others have some GPIOs implemented in
|
||||
* different modules.
|
||||
*
|
||||
* Firstly is the conventional GPIO registers where we toggle individual
|
||||
* bits in a register, preserving the other bits in the register. For
|
||||
* lack of a better term I have called this the slow method.
|
||||
* This implementation attempts accommodate the differences while presenting
|
||||
* a generic interface that will optimize to as few instructions as possible.
|
||||
*/
|
||||
#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \
|
||||
{ \
|
||||
.gpio_chip = { \
|
||||
.label = #mlabel, \
|
||||
.request = mcf_gpio_request, \
|
||||
.free = mcf_gpio_free, \
|
||||
.direction_input = mcf_gpio_direction_input, \
|
||||
.direction_output = mcf_gpio_direction_output,\
|
||||
.get = mcf_gpio_get_value, \
|
||||
.set = mcf_gpio_set_value, \
|
||||
.base = mbase, \
|
||||
.ngpio = mngpio, \
|
||||
}, \
|
||||
.pddr = (void __iomem *) mpddr, \
|
||||
.podr = (void __iomem *) mpodr, \
|
||||
.ppdr = (void __iomem *) mppdr, \
|
||||
}
|
||||
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
|
||||
defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
|
||||
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
|
||||
defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
|
||||
defined(CONFIG_M5441x)
|
||||
|
||||
/*
|
||||
* Secondly is the faster case, where we have set and clear registers
|
||||
* that allow us to set or clear a bit with a single write, not having
|
||||
* to worry about preserving other bits.
|
||||
*/
|
||||
#define MCFGPF(mlabel, mbase, mngpio) \
|
||||
{ \
|
||||
.gpio_chip = { \
|
||||
.label = #mlabel, \
|
||||
.request = mcf_gpio_request, \
|
||||
.free = mcf_gpio_free, \
|
||||
.direction_input = mcf_gpio_direction_input, \
|
||||
.direction_output = mcf_gpio_direction_output,\
|
||||
.get = mcf_gpio_get_value, \
|
||||
.set = mcf_gpio_set_value_fast, \
|
||||
.base = mbase, \
|
||||
.ngpio = mngpio, \
|
||||
}, \
|
||||
.pddr = (void __iomem *) MCFGPIO_PDDR_##mlabel, \
|
||||
.podr = (void __iomem *) MCFGPIO_PODR_##mlabel, \
|
||||
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
|
||||
.setr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
|
||||
.clrr = (void __iomem *) MCFGPIO_PCLRR_##mlabel, \
|
||||
}
|
||||
/* These parts have GPIO organized by 8 bit ports */
|
||||
|
||||
#define MCFGPIO_PORTTYPE u8
|
||||
#define MCFGPIO_PORTSIZE 8
|
||||
#define mcfgpio_read(port) __raw_readb(port)
|
||||
#define mcfgpio_write(data, port) __raw_writeb(data, port)
|
||||
|
||||
#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
|
||||
|
||||
/* These parts have GPIO organized by 16 bit ports */
|
||||
|
||||
#define MCFGPIO_PORTTYPE u16
|
||||
#define MCFGPIO_PORTSIZE 16
|
||||
#define mcfgpio_read(port) __raw_readw(port)
|
||||
#define mcfgpio_write(data, port) __raw_writew(data, port)
|
||||
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
|
||||
|
||||
/* These parts have GPIO organized by 32 bit ports */
|
||||
|
||||
#define MCFGPIO_PORTTYPE u32
|
||||
#define MCFGPIO_PORTSIZE 32
|
||||
#define mcfgpio_read(port) __raw_readl(port)
|
||||
#define mcfgpio_write(data, port) __raw_writel(data, port)
|
||||
|
||||
#endif
|
||||
|
||||
#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
|
||||
#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
|
||||
|
||||
#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
|
||||
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
|
||||
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
|
||||
/*
|
||||
* These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
|
||||
* read-modify-write to change an output and a GPIO module which has separate
|
||||
* set/clr registers to directly change outputs with a single write access.
|
||||
*/
|
||||
#if defined(CONFIG_M528x)
|
||||
/*
|
||||
* The 528x also has GPIOs in other modules (GPT, QADC) which use
|
||||
* read-modify-write as well as those controlled by the EPORT and GPIO modules.
|
||||
*/
|
||||
#define MCFGPIO_SCR_START 40
|
||||
#elif defined(CONFIGM5441x)
|
||||
/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
|
||||
#define MCFGPIO_SCR_START 0
|
||||
#else
|
||||
#define MCFGPIO_SCR_START 8
|
||||
#endif
|
||||
|
||||
#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
|
||||
mcfgpio_port(gpio - MCFGPIO_SCR_START))
|
||||
|
||||
#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
|
||||
mcfgpio_port(gpio - MCFGPIO_SCR_START))
|
||||
#else
|
||||
|
||||
#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
|
||||
/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
|
||||
#define MCFGPIO_SETR_PORT(gpio) 0
|
||||
#define MCFGPIO_CLRR_PORT(gpio) 0
|
||||
|
||||
#endif
|
||||
/*
|
||||
* Coldfire specific helper functions
|
||||
*/
|
||||
|
||||
/* return the port pin data register for a gpio */
|
||||
static inline u32 __mcfgpio_ppdr(unsigned gpio)
|
||||
{
|
||||
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
|
||||
defined(CONFIG_M5307) || defined(CONFIG_M5407)
|
||||
return MCFSIM_PADAT;
|
||||
#elif defined(CONFIG_M5272)
|
||||
if (gpio < 16)
|
||||
return MCFSIM_PADAT;
|
||||
else if (gpio < 32)
|
||||
return MCFSIM_PBDAT;
|
||||
else
|
||||
return MCFSIM_PCDAT;
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
|
||||
if (gpio < 32)
|
||||
return MCFSIM2_GPIOREAD;
|
||||
else
|
||||
return MCFSIM2_GPIO1READ;
|
||||
#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
|
||||
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
|
||||
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
|
||||
#if !defined(CONFIG_M5441x)
|
||||
if (gpio < 8)
|
||||
return MCFEPORT_EPPDR;
|
||||
#if defined(CONFIG_M528x)
|
||||
else if (gpio < 16)
|
||||
return MCFGPTA_GPTPORT;
|
||||
else if (gpio < 24)
|
||||
return MCFGPTB_GPTPORT;
|
||||
else if (gpio < 32)
|
||||
return MCFQADC_PORTQA;
|
||||
else if (gpio < 40)
|
||||
return MCFQADC_PORTQB;
|
||||
#endif /* defined(CONFIG_M528x) */
|
||||
else
|
||||
#endif /* !defined(CONFIG_M5441x) */
|
||||
return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* return the port output data register for a gpio */
|
||||
static inline u32 __mcfgpio_podr(unsigned gpio)
|
||||
{
|
||||
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
|
||||
defined(CONFIG_M5307) || defined(CONFIG_M5407)
|
||||
return MCFSIM_PADAT;
|
||||
#elif defined(CONFIG_M5272)
|
||||
if (gpio < 16)
|
||||
return MCFSIM_PADAT;
|
||||
else if (gpio < 32)
|
||||
return MCFSIM_PBDAT;
|
||||
else
|
||||
return MCFSIM_PCDAT;
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
|
||||
if (gpio < 32)
|
||||
return MCFSIM2_GPIOWRITE;
|
||||
else
|
||||
return MCFSIM2_GPIO1WRITE;
|
||||
#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
|
||||
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
|
||||
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
|
||||
#if !defined(CONFIG_M5441x)
|
||||
if (gpio < 8)
|
||||
return MCFEPORT_EPDR;
|
||||
#if defined(CONFIG_M528x)
|
||||
else if (gpio < 16)
|
||||
return MCFGPTA_GPTPORT;
|
||||
else if (gpio < 24)
|
||||
return MCFGPTB_GPTPORT;
|
||||
else if (gpio < 32)
|
||||
return MCFQADC_PORTQA;
|
||||
else if (gpio < 40)
|
||||
return MCFQADC_PORTQB;
|
||||
#endif /* defined(CONFIG_M528x) */
|
||||
else
|
||||
#endif /* !defined(CONFIG_M5441x) */
|
||||
return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* return the port direction data register for a gpio */
|
||||
static inline u32 __mcfgpio_pddr(unsigned gpio)
|
||||
{
|
||||
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
|
||||
defined(CONFIG_M5307) || defined(CONFIG_M5407)
|
||||
return MCFSIM_PADDR;
|
||||
#elif defined(CONFIG_M5272)
|
||||
if (gpio < 16)
|
||||
return MCFSIM_PADDR;
|
||||
else if (gpio < 32)
|
||||
return MCFSIM_PBDDR;
|
||||
else
|
||||
return MCFSIM_PCDDR;
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
|
||||
if (gpio < 32)
|
||||
return MCFSIM2_GPIOENABLE;
|
||||
else
|
||||
return MCFSIM2_GPIO1ENABLE;
|
||||
#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
|
||||
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
|
||||
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
|
||||
#if !defined(CONFIG_M5441x)
|
||||
if (gpio < 8)
|
||||
return MCFEPORT_EPDDR;
|
||||
#if defined(CONFIG_M528x)
|
||||
else if (gpio < 16)
|
||||
return MCFGPTA_GPTDDR;
|
||||
else if (gpio < 24)
|
||||
return MCFGPTB_GPTDDR;
|
||||
else if (gpio < 32)
|
||||
return MCFQADC_DDRQA;
|
||||
else if (gpio < 40)
|
||||
return MCFQADC_DDRQB;
|
||||
#endif /* defined(CONFIG_M528x) */
|
||||
else
|
||||
#endif /* !defined(CONFIG_M5441x) */
|
||||
return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* mcfgpio_h */
|
||||
|
||||
@@ -27,6 +27,9 @@
|
||||
#elif defined(CONFIG_M5249)
|
||||
#include <asm/m5249sim.h>
|
||||
#include <asm/mcfintc.h>
|
||||
#elif defined(CONFIG_M525x)
|
||||
#include <asm/m525xsim.h>
|
||||
#include <asm/mcfintc.h>
|
||||
#elif defined(CONFIG_M527x)
|
||||
#include <asm/m527xsim.h>
|
||||
#elif defined(CONFIG_M5272)
|
||||
@@ -43,6 +46,8 @@
|
||||
#include <asm/mcfintc.h>
|
||||
#elif defined(CONFIG_M54xx)
|
||||
#include <asm/m54xxsim.h>
|
||||
#elif defined(CONFIG_M5441x)
|
||||
#include <asm/m5441xsim.h>
|
||||
#endif
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user