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Merge tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull ARM SoC late cleanups from Arnd Bergmann:
 "These could not be part of the first cleanup branch, because they
  either came too late in the cycle, or they have dependencies on other
  branches.  Important changes are:

   - The integrator platform is almost multiplatform capable after some
     reorganization (Linus Walleij)
   - Minor cleanups on Zynq (Michal Simek)
   - Lots of changes for Exynos and other Samsung platforms, including
     further preparations for multiplatform support and the clocks
     bindings are rearranged"

* tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits)
  devicetree: fix newly added exynos sata bindings
  ARM: EXYNOS: Fix compilation error in cpuidle.c
  ARM: S5P64X0: Explicitly include linux/serial_s3c.h in mach/pm-core.h
  ARM: EXYNOS: Remove hardware.h file
  ARM: SAMSUNG: Remove hardware.h inclusion
  ARM: S3C24XX: Remove invalid code from hardware.h
  dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock
  ARM: dts: Keep some essential LDOs enabled for arndale-octa board
  ARM: dts: Disable MDMA1 node for arndale-octa board
  ARM: S3C64XX: Fix build for implicit serial_s3c.h inclusion
  serial: s3c: Fix build of header without serial_core.h preinclusion
  ARM: EXYNOS: Allow wake-up using GIC interrupts
  ARM: EXYNOS: Stop using legacy Samsung PM code
  ARM: EXYNOS: Remove PM initcalls and useless indirection
  ARM: EXYNOS: Fix abuse of CONFIG_PM
  ARM: SAMSUNG: Move s3c_pm_check_* prototypes to plat/pm-common.h
  ARM: SAMSUNG: Move common save/restore helpers to separate file
  ARM: SAMSUNG: Move Samsung PM debug code into separate file
  ARM: SAMSUNG: Consolidate PM debug functions
  ARM: SAMSUNG: Use debug_ll_addr() to get UART base address
  ...
This commit is contained in:
Linus Torvalds
2014-04-05 15:46:37 -07:00
parent d2b150d064 9dfbff16b4
commit 2bf73dd61a
92 changed files with 1156 additions and 1369 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
-14
View File
@@ -1,14 +0,0 @@
* Samsung SATA PHY Controller
SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
Each SATA PHY controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5-sata-phy"
- reg : <registers mapping>
Example:
sata@ffe07000 {
compatible = "samsung,exynos5-sata-phy";
reg = <0xffe07000 0x1000>;
};
Documentation/devicetree/bindings/ata/exynos-sata.txt
+22 -9
View File
@@ -4,14 +4,27 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5-sata"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
- compatible : compatible list, contains "samsung,exynos5-sata"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
- phys : Must contain exactly one entry as specified
in phy-bindings.txt
- phy-names : Must be "sata-phy"
Optional properties:
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Shall be "sata" for the external SATA bus clock,
and "sclk_sata" for the internal controller clock.
Example:
sata@ffe08000 {
compatible = "samsung,exynos5-sata";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
};
sata@122f0000 {
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122f0000 0x1ff>;
interrupts = <0 115 0>;
clocks = <&clock 277>, <&clock 143>;
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
phy-names = "sata-phy";
};
Documentation/devicetree/bindings/clock/zynq-7000.txt
+3 -1
View File
@@ -14,6 +14,7 @@ for all clock consumers of PS clocks.
Required properties:
- #clock-cells : Must be 1
- compatible : "xlnx,ps7-clkc"
- reg : SLCR offset and size taken via syscon < 0x100 0x100 >
- ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
(usually 33 MHz oscillators are used for Zynq platforms)
- clock-output-names : List of strings used to name the clock outputs. Shall be
@@ -87,10 +88,11 @@ Clock outputs:
47: dbg_apb
Example:
clkc: clkc {
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
reg = <0x100 0x100>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
Documentation/devicetree/bindings/phy/samsung-phy.txt
+40
View File
@@ -74,3 +74,43 @@ phy-consumer@12340000 {
Refer to DT bindings documentation of particular PHY consumer devices for more
information about required PHYs and the way of specification.
Samsung SATA PHY Controller
---------------------------
SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
Each SATA PHY controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5250-sata-phy"
- reg : offset and length of the SATA PHY register set;
- #phy-cells : must be zero
- clocks : must be exactly one entry
- clock-names : must be "sata_phyctrl"
- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
Example:
sata_phy: sata-phy@12170000 {
compatible = "samsung,exynos5250-sata-phy";
reg = <0x12170000 0x1ff>;
clocks = <&clock 287>;
clock-names = "sata_phyctrl";
#phy-cells = <0>;
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
samsung,syscon-phandle = <&pmu_syscon>;
};
Device-Tree bindings for sataphy i2c client driver
--------------------------------------------------
Required properties:
compatible: Should be "samsung,exynos-sataphy-i2c"
- reg: I2C address of the sataphy i2c device.
Example:
sata_phy_i2c:sata-phy@38 {
compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
arch/arm/Kconfig.debug
+2 -2
View File
@@ -1141,7 +1141,7 @@ config DEBUG_UART_8250_FLOW_CONTROL
config DEBUG_UNCOMPRESS
bool
depends on ARCH_MULTIPLATFORM || ARCH_MSM || ARCH_EXYNOS
depends on ARCH_MULTIPLATFORM || ARCH_MSM || PLAT_SAMSUNG
default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
(!DEBUG_TEGRA_UART || !ZBOOT_ROM)
help
@@ -1158,7 +1158,7 @@ config DEBUG_UNCOMPRESS
config UNCOMPRESS_INCLUDE
string
default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
ARCH_EXYNOS || ARCH_EFM32
PLAT_SAMSUNG || ARCH_EFM32
default "mach/uncompress.h"
config EARLY_PRINTK
arch/arm/boot/dts/exynos4.dtsi
+5
View File
@@ -86,6 +86,11 @@
reg = <0x10023CE0 0x20>;
};
pd_gps_alive: gps-alive-power-domain@10023D00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023D00 0x20>;
};
gic: interrupt-controller@10490000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
arch/arm/boot/dts/exynos4210-origen.dts
+1 -1
View File
@@ -19,7 +19,7 @@
/ {
model = "Insignal Origen evaluation board based on Exynos4210";
compatible = "insignal,origen", "samsung,exynos4210";
compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4";
memory {
reg = <0x40000000 0x10000000
arch/arm/boot/dts/exynos4210-smdkv310.dts
+1 -1
View File
@@ -19,7 +19,7 @@
/ {
model = "Samsung smdkv310 evaluation board based on Exynos4210";
compatible = "samsung,smdkv310", "samsung,exynos4210";
compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4";
memory {
reg = <0x40000000 0x80000000>;
arch/arm/boot/dts/exynos4210-trats.dts
+1 -1
View File
@@ -17,7 +17,7 @@
/ {
model = "Samsung Trats based on Exynos4210";
compatible = "samsung,trats", "samsung,exynos4210";
compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4";
memory {
reg = <0x40000000 0x10000000
arch/arm/boot/dts/exynos4210-universal_c210.dts
+1 -1
View File
@@ -17,7 +17,7 @@
/ {
model = "Samsung Universal C210 based on Exynos4210 rev0";
compatible = "samsung,universal_c210", "samsung,exynos4210";
compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4";
memory {
reg = <0x40000000 0x10000000
arch/arm/boot/dts/exynos4210.dtsi
+1 -1
View File
@@ -23,7 +23,7 @@
#include "exynos4210-pinctrl.dtsi"
/ {
compatible = "samsung,exynos4210";
compatible = "samsung,exynos4210", "samsung,exynos4";
aliases {
pinctrl0 = &pinctrl_0;
arch/arm/boot/dts/exynos4212.dtsi
+5 -10
View File
@@ -20,18 +20,13 @@
#include "exynos4x12.dtsi"
/ {
compatible = "samsung,exynos4212";
compatible = "samsung,exynos4212", "samsung,exynos4";
combiner: interrupt-controller@10440000 {
samsung,combiner-nr = <18>;
};
gic: interrupt-controller@10490000 {
cpu-offset = <0x8000>;
};
interrupt-controller@10440000 {
samsung,combiner-nr = <18>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 107 0>, <0 108 0>;
};
};
arch/arm/boot/dts/exynos4412-odroidx.dts
+1 -1
View File
@@ -16,7 +16,7 @@
/ {
model = "Hardkernel ODROID-X board based on Exynos4412";
compatible = "hardkernel,odroid-x", "samsung,exynos4412";
compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4";
memory {
reg = <0x40000000 0x40000000>;
arch/arm/boot/dts/exynos4412-origen.dts
+1 -1
View File
@@ -17,7 +17,7 @@
/ {
model = "Insignal Origen evaluation board based on Exynos4412";
compatible = "insignal,origen4412", "samsung,exynos4412";
compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4";
memory {
reg = <0x40000000 0x40000000>;
arch/arm/boot/dts/exynos4412-smdk4412.dts
+1 -1
View File
@@ -17,7 +17,7 @@
/ {
model = "Samsung SMDK evaluation board based on Exynos4412";
compatible = "samsung,smdk4412", "samsung,exynos4412";
compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4";
memory {
reg = <0x40000000 0x40000000>;
arch/arm/boot/dts/exynos4412-tiny4412.dts
+1 -1
View File
@@ -16,7 +16,7 @@
/ {
model = "FriendlyARM TINY4412 board based on Exynos4412";
compatible = "friendlyarm,tiny4412", "samsung,exynos4412";
compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4";
memory {
reg = <0x40000000 0x40000000>;
arch/arm/boot/dts/exynos4412-trats2.dts
+22 -1
View File
@@ -17,7 +17,7 @@
/ {
model = "Samsung Trats 2 based on Exynos4412";
compatible = "samsung,trats2", "samsung,exynos4412";
compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
aliases {
i2c8 = &i2c_ak8975;
@@ -106,6 +106,11 @@
};
};
adc: adc@126C0000 {
vdd-supply = <&ldo3_reg>;
status = "okay";
};
i2c@13890000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-slave-addr = <0x10>;
@@ -589,4 +594,20 @@
};
};
};
thermistor-ap@0 {
compatible = "ntc,ncp15wb473";
pullup-uv = <1800000>; /* VCC_1.8V_AP */
pullup-ohm = <100000>; /* 100K */
pulldown-ohm = <100000>; /* 100K */
io-channels = <&adc 1>; /* AP temperature */
};
thermistor-battery@1 {
compatible = "ntc,ncp15wb473";
pullup-uv = <1800000>; /* VCC_1.8V_AP */
pullup-ohm = <100000>; /* 100K */
pulldown-ohm = <100000>; /* 100K */
io-channels = <&adc 2>; /* Battery temperature */
};
};
arch/arm/boot/dts/exynos4412.dtsi
+5 -11
View File
@@ -20,19 +20,13 @@
#include "exynos4x12.dtsi"
/ {
compatible = "samsung,exynos4412";
compatible = "samsung,exynos4412", "samsung,exynos4";
combiner: interrupt-controller@10440000 {
samsung,combiner-nr = <20>;
};
gic: interrupt-controller@10490000 {
cpu-offset = <0x4000>;
};
interrupt-controller@10440000 {
samsung,combiner-nr = <20>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
};
};
arch/arm/boot/dts/exynos4x12.dtsi
+26
View File
@@ -31,6 +31,12 @@
mshc0 = &mshc_0;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&combiner>;
interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
};
pd_isp: isp-power-domain@10023CA0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
@@ -62,6 +68,14 @@
};
};
combiner: interrupt-controller@10440000 {
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
@@ -80,6 +94,18 @@
};
};
adc: adc@126C0000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x126C0000 0x100>, <0x10020718 0x4>;
interrupt-parent = <&combiner>;
interrupts = <10 3>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
status = "disabled";
};
pinctrl_2: pinctrl@03860000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x03860000 0x1000>;
arch/arm/boot/dts/exynos5250-arndale.dts
+22 -1
View File
@@ -15,7 +15,7 @@
/ {
model = "Insignal Arndale evaluation board based on EXYNOS5250";
compatible = "insignal,arndale", "samsung,exynos5250";
compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5";
memory {
reg = <0x40000000 0x80000000>;
@@ -375,6 +375,27 @@
};
};
i2c@121D0000 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <40000>;
samsung,i2c-slave-addr = <0x38>;
sata_phy_i2c:sata-phy@38 {
compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
};
sata@122F0000 {
status = "okay";
};
sata-phy@12170000 {
status = "okay";
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
};
mmc_0: mmc@12200000 {
status = "okay";
num-slots = <1>;

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