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Merge tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.12 kernel cycle.
Core changes:
- Return NULL from gpiod_get_optional() when GPIOLIB is disabled.
This was a much discussed change. It affects use cases where people
write drivers that might or might not be using GPIO resources. I
have decided that this is the lesser evil right now.
- Make gpiod_count() behave consistently across different hardware
descriptions.
- Fix the syntax around open drain/open source to not infer active
high/low semantics.
New drivers:
- A new single-register fixed-direction framework driver for hardware
that have lines controlled by a single register that just work in
one direction (out or in), including IRQ support.
- Support the Fintek F71889A GPIO SuperIO controller.
- Support the National NI 169445 MMIO GPIO.
- Support for the X-Gene derivative of the DWC GPIO controller
- Support for the Rohm BD9571MWV-M PMIC GPIO controller.
- Refactor the Gemini GPIO driver to a generic Faraday FTGPIO driver
and replace both the Gemini and the Moxa ART custom drivers with
this driver.
Driver improvements:
- A whole slew of drivers have their spinlocks chaned to raw
spinlocks as they provide irqchips, and thus we are progressing on
realtime compliance.
- Use devm_irq_alloc_descs() in a slew of drivers, getting managed
resources.
- Support for the embedded PWM controller inside the MVEBU driver.
- Debounce, open source and open drain support for the Aspeed driver.
- Misc smaller fixes like spelling and syntax and whatnot"
* tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (77 commits)
gpio: f7188x: Add a missing break
gpio: omap: return error if requested debounce time is not possible
gpio: Add ROHM BD9571MWV-M PMIC GPIO driver
gpio: gpio-wcove: fix GPIO IRQ status mask
gpio: DT bindings, move tca9554 from pcf857x to pca953x
gpio: move tca9554 from pcf857x to pca953x
gpio: arizona: Correct check whether the pin is an input
gpio: Add XRA1403 DTS binding documentation
dt-bindings: add exar to vendor prefixes list
gpio: gpio-wcove: fix irq pending status bit width
gpio: dwapb: use dwapb_read instead of readl_relaxed
gpio: aspeed: Add open-source and open-drain support
gpio: aspeed: Add debounce support
gpio: aspeed: dt: Add optional clocks property
gpio: aspeed: dt: Fix description alignment in bindings document
gpio: mvebu: Add limited PWM support
gpio: Use unsigned int for interrupt numbers
gpio: f7188x: Add F71889A GPIO support.
gpio: core: Decouple open drain/source flag with active low/high
gpio: arizona: Correct handling for reading input GPIOs
...
This commit is contained in:
Linus Torvalds
+6
-3
@@ -1,8 +1,11 @@
|
||||
Cortina Systems Gemini GPIO Controller
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||||
Faraday Technology FTGPIO010 GPIO Controller
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||||
|
||||
Required properties:
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|
||||
- compatible : Must be "cortina,gemini-gpio"
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- compatible : Should be one of
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"cortina,gemini-gpio", "faraday,ftgpio010"
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"moxa,moxart-gpio", "faraday,ftgpio010"
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"faraday,ftgpio010"
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- reg : Should contain registers location and length
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- interrupts : Should contain the interrupt line for the GPIO block
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- gpio-controller : marks this as a GPIO controller
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@@ -14,7 +17,7 @@ Required properties:
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Example:
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gpio@4d000000 {
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compatible = "cortina,gemini-gpio";
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4d000000 0x100>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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@@ -17,7 +17,8 @@ Required properties:
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Optional properties:
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- interrupt-parent : The parent interrupt controller, optional if inherited
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- interrupt-parent : The parent interrupt controller, optional if inherited
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- clocks : A phandle to the HPLL clock node for debounce timings
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The gpio and interrupt properties are further described in their respective
|
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bindings documentation:
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@@ -38,6 +38,24 @@ Required properties:
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- #gpio-cells: Should be two. The first cell is the pin number. The
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second cell is reserved for flags, unused at the moment.
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Optional properties:
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In order to use the GPIO lines in PWM mode, some additional optional
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properties are required. Only Armada 370 and XP support these properties.
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- compatible: Must contain "marvell,armada-370-xp-gpio"
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- reg: an additional register set is needed, for the GPIO Blink
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Counter on/off registers.
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- reg-names: Must contain an entry "pwm" corresponding to the
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additional register range needed for PWM operation.
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- #pwm-cells: Should be two. The first cell is the GPIO line number. The
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second cell is the period in nanoseconds.
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- clocks: Must be a phandle to the clock for the GPIO controller.
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Example:
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gpio0: gpio@d0018100 {
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@@ -51,3 +69,17 @@ Example:
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#interrupt-cells = <2>;
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interrupts = <16>, <17>, <18>, <19>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,armada-370-xp-gpio";
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reg = <0x18140 0x40>, <0x181c8 0x08>;
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reg-names = "gpio", "pwm";
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ngpios = <17>;
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gpio-controller;
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#gpio-cells = <2>;
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#pwm-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <87>, <88>, <89>;
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clocks = <&coreclk 0>;
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};
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@@ -26,6 +26,7 @@ Required properties:
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ti,tca6416
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ti,tca6424
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ti,tca9539
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ti,tca9554
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onsemi,pca9654
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exar,xra1202
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@@ -25,7 +25,6 @@ Required Properties:
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- "nxp,pcf8574": For the NXP PCF8574
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- "nxp,pcf8574a": For the NXP PCF8574A
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- "nxp,pcf8575": For the NXP PCF8575
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- "ti,tca9554": For the TI TCA9554
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- reg: I2C slave address.
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@@ -0,0 +1,27 @@
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Cavium ThunderX/OCTEON-TX GPIO controller bindings
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Required Properties:
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- reg: The controller bus address.
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells: Must be 2.
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- First cell is the GPIO pin number relative to the controller.
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- Second cell is a standard generic flag bitfield as described in gpio.txt.
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Optional Properties:
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- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: Must be present and have value of 2 if
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"interrupt-controller" is present.
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- First cell is the GPIO pin number relative to the controller.
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- Second cell is triggering flags as defined in interrupts.txt.
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Example:
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gpio_6_0: gpio@6,0 {
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compatible = "cavium,thunder-8890-gpio";
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reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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@@ -0,0 +1,46 @@
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GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR
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The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
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- Individually programmable inputs:
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- Internal pull-up resistors
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- Polarity inversion
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- Individual interrupt enable
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- Rising edge and/or Falling edge interrupt
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- Input filter
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- Individually programmable outputs
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- Output Level Control
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- Output Three-State Control
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Properties
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----------
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Check documentation for SPI and GPIO controllers regarding properties needed to configure the node.
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- compatible = "exar,xra1403".
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- reg - SPI id of the device.
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- gpio-controller - marks the node as gpio.
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- #gpio-cells - should be two where the first cell is the pin number
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and the second one is used for optional parameters.
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Optional properties:
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-------------------
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- reset-gpios: in case available used to control the device reset line.
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- interrupt-controller - marks the node as interrupt controller.
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- #interrupt-cells - should be two and represents the number of cells
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needed to encode interrupt source.
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Example
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--------
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gpioxra0: gpio@2 {
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compatible = "exar,xra1403";
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reg = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
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spi-max-frequency = <1000000>;
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};
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@@ -1,19 +0,0 @@
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MOXA ART GPIO Controller
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Required properties:
|
||||
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- #gpio-cells : Should be 2, The first cell is the pin number,
|
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the second cell is used to specify polarity:
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0 = active high
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1 = active low
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- compatible : Must be "moxa,moxart-gpio"
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- reg : Should contain registers location and length
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Example:
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gpio: gpio@98700000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "moxa,moxart-gpio";
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reg = <0x98700000 0xC>;
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};
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@@ -0,0 +1,38 @@
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Bindings for the National Instruments 169445 GPIO NAND controller
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The 169445 GPIO NAND controller has two memory mapped GPIO registers, one
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for input (the ready signal) and one for output (control signals). It is
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intended to be used with the GPIO NAND driver.
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Required properties:
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- compatible: should be "ni,169445-nand-gpio"
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- reg-names: must contain
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"dat" - data register
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- reg: address + size pairs describing the GPIO register sets;
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order must correspond with the order of entries in reg-names
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- #gpio-cells: must be set to 2. The first cell is the pin number and
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the second cell is used to specify the gpio polarity:
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0 = active high
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1 = active low
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- gpio-controller: Marks the device node as a gpio controller.
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Optional properties:
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- no-output: disables driving output on the pins
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Examples:
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gpio1: nand-gpio-out@1f300010 {
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compatible = "ni,169445-nand-gpio";
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reg = <0x1f300010 0x4>;
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reg-names = "dat";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: nand-gpio-in@1f300014 {
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compatible = "ni,169445-nand-gpio";
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reg = <0x1f300014 0x4>;
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reg-names = "dat";
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gpio-controller;
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#gpio-cells = <2>;
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no-output;
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};
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@@ -103,6 +103,7 @@ ettus NI Ettus Research
|
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eukrea Eukréa Electromatique
|
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everest Everest Semiconductor Co. Ltd.
|
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everspin Everspin Technologies, Inc.
|
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exar Exar Corporation
|
||||
excito Excito
|
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ezchip EZchip Semiconductor
|
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faraday Faraday Technology Corporation
|
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|
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@@ -70,6 +70,12 @@ instead of -ENOENT if no GPIO has been assigned to the requested function:
|
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unsigned int index,
|
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enum gpiod_flags flags)
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||||
|
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Note that gpio_get*_optional() functions (and their managed variants), unlike
|
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the rest of gpiolib API, also return NULL when gpiolib support is disabled.
|
||||
This is helpful to driver authors, since they do not need to special case
|
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-ENOSYS return codes. System integrators should however be careful to enable
|
||||
gpiolib on systems that need it.
|
||||
|
||||
For a function using multiple GPIOs all of those can be obtained with one call:
|
||||
|
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struct gpio_descs *gpiod_get_array(struct device *dev,
|
||||
|
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@@ -10315,6 +10315,8 @@ F: include/linux/pwm.h
|
||||
F: drivers/pwm/
|
||||
F: drivers/video/backlight/pwm_bl.c
|
||||
F: include/linux/pwm_backlight.h
|
||||
F: drivers/gpio/gpio-mvebu.c
|
||||
F: Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
|
||||
|
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PXA2xx/PXA3xx SUPPORT
|
||||
M: Daniel Mack <daniel@zonque.org>
|
||||
|
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+28
-18
@@ -204,14 +204,15 @@ config GPIO_GE_FPGA
|
||||
and write pin state) for GPIO implemented in a number of GE single
|
||||
board computers.
|
||||
|
||||
config GPIO_GEMINI
|
||||
bool "Gemini GPIO"
|
||||
depends on ARCH_GEMINI
|
||||
config GPIO_FTGPIO010
|
||||
bool "Faraday FTGPIO010 GPIO"
|
||||
depends on OF_GPIO
|
||||
select GPIO_GENERIC
|
||||
select GPIOLIB_IRQCHIP
|
||||
default (ARCH_GEMINI || ARCH_MOXART)
|
||||
help
|
||||
Support for common GPIOs found in Cortina systems Gemini platforms.
|
||||
Support for common GPIOs from the Faraday FTGPIO010 IP core, found in
|
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Cortina systems Gemini platforms, Moxa ART and others.
|
||||
|
||||
config GPIO_GENERIC_PLATFORM
|
||||
tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
|
||||
@@ -308,14 +309,6 @@ config GPIO_MOCKUP
|
||||
tools/testing/selftests/gpio/gpio-mockup.sh. Reference the usage in
|
||||
it.
|
||||
|
||||
config GPIO_MOXART
|
||||
bool "MOXART GPIO support"
|
||||
depends on ARCH_MOXART || COMPILE_TEST
|
||||
select GPIO_GENERIC
|
||||
help
|
||||
Select this option to enable GPIO driver for
|
||||
MOXA ART SoC devices.
|
||||
|
||||
config GPIO_MPC5200
|
||||
def_bool y
|
||||
depends on PPC_MPC52xx
|
||||
@@ -387,6 +380,12 @@ config GPIO_RCAR
|
||||
help
|
||||
Say yes here to support GPIO on Renesas R-Car SoCs.
|
||||
|
||||
config GPIO_REG
|
||||
bool
|
||||
help
|
||||
A 32-bit single register GPIO fixed in/out implementation. This
|
||||
can be used to represent any register as a set of GPIO signals.
|
||||
|
||||
config GPIO_SPEAR_SPICS
|
||||
bool "ST SPEAr13xx SPI Chip Select as GPIO support"
|
||||
depends on PLAT_SPEAR
|
||||
@@ -505,7 +504,7 @@ config GPIO_XILINX
|
||||
|
||||
config GPIO_XLP
|
||||
tristate "Netlogic XLP GPIO support"
|
||||
depends on OF_GPIO && (CPU_XLP || ARCH_VULCAN || COMPILE_TEST)
|
||||
depends on OF_GPIO && (CPU_XLP || ARCH_VULCAN || ARCH_THUNDER2 || COMPILE_TEST)
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
This driver provides support for GPIO interface on Netlogic XLP MIPS64
|
||||
@@ -557,7 +556,7 @@ menu "Port-mapped I/O GPIO drivers"
|
||||
|
||||
config GPIO_104_DIO_48E
|
||||
tristate "ACCES 104-DIO-48E GPIO support"
|
||||
depends on ISA_BUS_API
|
||||
depends on PC104 && ISA_BUS_API
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
Enables GPIO support for the ACCES 104-DIO-48E series (104-DIO-48E,
|
||||
@@ -567,7 +566,7 @@ config GPIO_104_DIO_48E
|
||||
|
||||
config GPIO_104_IDIO_16
|
||||
tristate "ACCES 104-IDIO-16 GPIO support"
|
||||
depends on ISA_BUS_API
|
||||
depends on PC104 && ISA_BUS_API
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
Enables GPIO support for the ACCES 104-IDIO-16 family (104-IDIO-16,
|
||||
@@ -578,7 +577,7 @@ config GPIO_104_IDIO_16
|
||||
|
||||
config GPIO_104_IDI_48
|
||||
tristate "ACCES 104-IDI-48 GPIO support"
|
||||
depends on ISA_BUS_API
|
||||
depends on PC104 && ISA_BUS_API
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
Enables GPIO support for the ACCES 104-IDI-48 family (104-IDI-48A,
|
||||
@@ -598,7 +597,7 @@ config GPIO_F7188X
|
||||
|
||||
config GPIO_GPIO_MM
|
||||
tristate "Diamond Systems GPIO-MM GPIO support"
|
||||
depends on ISA_BUS_API
|
||||
depends on PC104 && ISA_BUS_API
|
||||
help
|
||||
Enables GPIO support for the Diamond Systems GPIO-MM and GPIO-MM-12.
|
||||
|
||||
@@ -753,7 +752,7 @@ config GPIO_PCA953X
|
||||
4 bits: pca9536, pca9537
|
||||
|
||||
8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554,
|
||||
pca9556, pca9557, pca9574, tca6408, xra1202
|
||||
pca9556, pca9557, pca9574, tca6408, tca9554, xra1202
|
||||
|
||||
16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575,
|
||||
tca6416
|
||||
@@ -845,6 +844,17 @@ config GPIO_ARIZONA
|
||||
help
|
||||
Support for GPIOs on Wolfson Arizona class devices.
|
||||
|
||||
config GPIO_BD9571MWV
|
||||
tristate "ROHM BD9571 GPIO support"
|
||||
depends on MFD_BD9571MWV
|
||||
help
|
||||
Support for GPIOs on ROHM BD9571 PMIC. There are two GPIOs
|
||||
available on the ROHM PMIC in total, both of which can also
|
||||
generate interrupts.
|
||||
|
||||
This driver can also be built as a module. If so, the module
|
||||
will be called gpio-bd9571mwv.
|
||||
|
||||
config GPIO_CRYSTAL_COVE
|
||||
tristate "GPIO support for Crystal Cove PMIC"
|
||||
depends on (X86 || COMPILE_TEST) && INTEL_SOC_PMIC
|
||||
|
||||
@@ -33,6 +33,7 @@ obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o
|
||||
obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o
|
||||
obj-$(CONFIG_GPIO_AXP209) += gpio-axp209.o
|
||||
obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
|
||||
obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o
|
||||
obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o
|
||||
obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
|
||||
obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
|
||||
@@ -48,8 +49,8 @@ obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
|
||||
obj-$(CONFIG_GPIO_ETRAXFS) += gpio-etraxfs.o
|
||||
obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o
|
||||
obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
|
||||
obj-$(CONFIG_GPIO_FTGPIO010) += gpio-ftgpio010.o
|
||||
obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o
|
||||
obj-$(CONFIG_GPIO_GEMINI) += gpio-gemini.o
|
||||
obj-$(CONFIG_GPIO_GPIO_MM) += gpio-gpio-mm.o
|
||||
obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o
|
||||
obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o
|
||||
@@ -80,7 +81,6 @@ obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o
|
||||
obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o
|
||||
obj-$(CONFIG_GPIO_MM_LANTIQ) += gpio-mm-lantiq.o
|
||||
obj-$(CONFIG_GPIO_MOCKUP) += gpio-mockup.o
|
||||
obj-$(CONFIG_GPIO_MOXART) += gpio-moxart.o
|
||||
obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o
|
||||
obj-$(CONFIG_GPIO_MPC8XXX) += gpio-mpc8xxx.o
|
||||
obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o
|
||||
@@ -99,6 +99,7 @@ obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
|
||||
obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
|
||||
obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
|
||||
obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
|
||||
obj-$(CONFIG_GPIO_REG) += gpio-reg.o
|
||||
obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
|
||||
obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
|
||||
obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
|
||||
|
||||
@@ -136,7 +136,7 @@ EXPORT_SYMBOL(devm_gpiod_get_index);
|
||||
* GPIO descriptors returned from this function are automatically disposed on
|
||||
* driver detach.
|
||||
*
|
||||
* On successfull request the GPIO pin is configured in accordance with
|
||||
* On successful request the GPIO pin is configured in accordance with
|
||||
* provided @flags.
|
||||
*/
|
||||
struct gpio_desc *devm_fwnode_get_index_gpiod_from_child(struct device *dev,
|
||||
|
||||
@@ -55,7 +55,7 @@ struct dio48e_gpio {
|
||||
unsigned char io_state[6];
|
||||
unsigned char out_state[6];
|
||||
unsigned char control[2];
|
||||
spinlock_t lock;
|
||||
raw_spinlock_t lock;
|
||||
unsigned base;
|
||||
unsigned char irq_mask;
|
||||
};
|
||||
@@ -78,7 +78,7 @@ static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
unsigned long flags;
|
||||
unsigned control;
|
||||
|
||||
spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
|
||||
/* Check if configuring Port C */
|
||||
if (io_port == 2 || io_port == 5) {
|
||||
@@ -103,7 +103,7 @@ static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
control &= ~BIT(7);
|
||||
outb(control, control_addr);
|
||||
|
||||
spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -120,7 +120,7 @@ static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
||||
unsigned long flags;
|
||||
unsigned control;
|
||||
|
||||
spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
|
||||
/* Check if configuring Port C */
|
||||
if (io_port == 2 || io_port == 5) {
|
||||
@@ -153,7 +153,7 @@ static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
||||
control &= ~BIT(7);
|
||||
outb(control, control_addr);
|
||||
|
||||
spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -167,17 +167,17 @@ static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
unsigned long flags;
|
||||
unsigned port_state;
|
||||
|
||||
spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
|
||||
/* ensure that GPIO is set for input */
|
||||
if (!(dio48egpio->io_state[port] & mask)) {
|
||||
spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
port_state = inb(dio48egpio->base + in_port);
|
||||
|
||||
spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
|
||||
return !!(port_state & mask);
|
||||
}
|
||||
@@ -190,7 +190,7 @@ static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
const unsigned out_port = (port > 2) ? port + 1 : port;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
|
||||
if (value)
|
||||
dio48egpio->out_state[port] |= mask;
|
||||
@@ -199,7 +199,7 @@ static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
|
||||
outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
|
||||
|
||||
spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
}
|
||||
|
||||
static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
|
||||
@@ -225,14 +225,14 @@ static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
|
||||
out_port = (port > 2) ? port + 1 : port;
|
||||
bitmask = mask[BIT_WORD(i)] & bits[BIT_WORD(i)];
|
||||
|
||||
spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
|
||||
/* update output state data and set device gpio register */
|
||||
dio48egpio->out_state[port] &= ~mask[BIT_WORD(i)];
|
||||
dio48egpio->out_state[port] |= bitmask;
|
||||
outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
|
||||
|
||||
spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
|
||||
/* prepare for next gpio register set */
|
||||
mask[BIT_WORD(i)] >>= gpio_reg_size;
|
||||
@@ -255,7 +255,7 @@ static void dio48e_irq_mask(struct irq_data *data)
|
||||
if (offset != 19 && offset != 43)
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
|
||||
if (offset == 19)
|
||||
dio48egpio->irq_mask &= ~BIT(0);
|
||||
@@ -266,7 +266,7 @@ static void dio48e_irq_mask(struct irq_data *data)
|
||||
/* disable interrupts */
|
||||
inb(dio48egpio->base + 0xB);
|
||||
|
||||
spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
}
|
||||
|
||||
static void dio48e_irq_unmask(struct irq_data *data)
|
||||
@@ -280,7 +280,7 @@ static void dio48e_irq_unmask(struct irq_data *data)
|
||||
if (offset != 19 && offset != 43)
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
|
||||
|
||||
if (!dio48egpio->irq_mask) {
|
||||
/* enable interrupts */
|
||||
@@ -293,7 +293,7 @@ static void dio48e_irq_unmask(struct irq_data *data)
|
||||
else
|
||||
dio48egpio->irq_mask |= BIT(1);
|
||||
|
||||
spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
|
||||
}
|
||||
|
||||
static int dio48e_irq_set_type(struct irq_data *data, unsigned flow_type)
|
||||
@@ -329,11 +329,11 @@ static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
|
||||
generic_handle_irq(irq_find_mapping(chip->irqdomain,
|
||||
19 + gpio*24));
|
||||
|
||||
spin_lock(&dio48egpio->lock);
|
||||
raw_spin_lock(&dio48egpio->lock);
|
||||
|
||||
outb(0x00, dio48egpio->base + 0xF);
|
||||
|
||||
spin_unlock(&dio48egpio->lock);
|
||||
raw_spin_unlock(&dio48egpio->lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
@@ -388,7 +388,7 @@ static int dio48e_probe(struct device *dev, unsigned int id)
|
||||
dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
|
||||
dio48egpio->base = base[id];
|
||||
|
||||
spin_lock_init(&dio48egpio->lock);
|
||||
raw_spin_lock_init(&dio48egpio->lock);
|
||||
|
||||
err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
|
||||
if (err) {
|
||||
|
||||
@@ -51,7 +51,7 @@ MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
|
||||
*/
|
||||
struct idi_48_gpio {
|
||||
struct gpio_chip chip;
|
||||
spinlock_t lock;
|
||||
raw_spinlock_t lock;
|
||||
spinlock_t ack_lock;
|
||||
unsigned char irq_mask[6];
|
||||
unsigned base;
|
||||
@@ -112,11 +112,12 @@ static void idi_48_irq_mask(struct irq_data *data)
|
||||
if (!idi48gpio->irq_mask[boundary]) {
|
||||
idi48gpio->cos_enb &= ~BIT(boundary);
|
||||
|
||||
spin_lock_irqsave(&idi48gpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&idi48gpio->lock, flags);
|
||||
|
||||
outb(idi48gpio->cos_enb, idi48gpio->base + 7);
|
||||
|
||||
spin_unlock_irqrestore(&idi48gpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&idi48gpio->lock,
|
||||
flags);
|
||||
}
|
||||
|
||||
return;
|
||||
@@ -145,11 +146,12 @@ static void idi_48_irq_unmask(struct irq_data *data)
|
||||
if (!prev_irq_mask) {
|
||||
idi48gpio->cos_enb |= BIT(boundary);
|
||||
|
||||
spin_lock_irqsave(&idi48gpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&idi48gpio->lock, flags);
|
||||
|
||||
outb(idi48gpio->cos_enb, idi48gpio->base + 7);
|
||||
|
||||
spin_unlock_irqrestore(&idi48gpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&idi48gpio->lock,
|
||||
flags);
|
||||
}
|
||||
|
||||
return;
|
||||
@@ -186,11 +188,11 @@ static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
|
||||
|
||||
spin_lock(&idi48gpio->ack_lock);
|
||||
|
||||
spin_lock(&idi48gpio->lock);
|
||||
raw_spin_lock(&idi48gpio->lock);
|
||||
|
||||
cos_status = inb(idi48gpio->base + 7);
|
||||
|
||||
spin_unlock(&idi48gpio->lock);
|
||||
raw_spin_unlock(&idi48gpio->lock);
|
||||
|
||||
/* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
|
||||
if (cos_status & BIT(6)) {
|
||||
@@ -256,7 +258,7 @@ static int idi_48_probe(struct device *dev, unsigned int id)
|
||||
idi48gpio->chip.get = idi_48_gpio_get;
|
||||
idi48gpio->base = base[id];
|
||||
|
||||
spin_lock_init(&idi48gpio->lock);
|
||||
raw_spin_lock_init(&idi48gpio->lock);
|
||||
spin_lock_init(&idi48gpio->ack_lock);
|
||||
|
||||
err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
|
||||
|
||||
@@ -50,7 +50,7 @@ MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");
|
||||
*/
|
||||
struct idio_16_gpio {
|
||||
struct gpio_chip chip;
|
||||
spinlock_t lock;
|
||||
raw_spinlock_t lock;
|
||||
unsigned long irq_mask;
|
||||
unsigned base;
|
||||
unsigned out_state;
|
||||
@@ -99,7 +99,7 @@ static void idio_16_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
if (offset > 15)
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&idio16gpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&idio16gpio->lock, flags);
|
||||
|
||||
if (value)
|
||||
idio16gpio->out_state |= mask;
|
||||
@@ -111,7 +111,7 @@ static void idio_16_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
else
|
||||
outb(idio16gpio->out_state, idio16gpio->base);
|
||||
|
||||
spin_unlock_irqrestore(&idio16gpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
|
||||
}
|
||||
|
||||
static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
|
||||
@@ -120,7 +120,7 @@ static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
|
||||
struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&idio16gpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&idio16gpio->lock, flags);
|
||||
|
||||
idio16gpio->out_state &= ~*mask;
|
||||
idio16gpio->out_state |= *mask & *bits;
|
||||
@@ -130,7 +130,7 @@ static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
|
||||
if ((*mask >> 8) & 0xFF)
|
||||
outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
|
||||
|
||||
spin_unlock_irqrestore(&idio16gpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
|
||||
}
|
||||
|
||||
static void idio_16_irq_ack(struct irq_data *data)
|
||||
@@ -147,11 +147,11 @@ static void idio_16_irq_mask(struct irq_data *data)
|
||||
idio16gpio->irq_mask &= ~mask;
|
||||
|
||||
if (!idio16gpio->irq_mask) {
|
||||
spin_lock_irqsave(&idio16gpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&idio16gpio->lock, flags);
|
||||
|
||||
outb(0, idio16gpio->base + 2);
|
||||
|
||||
spin_unlock_irqrestore(&idio16gpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -166,11 +166,11 @@ static void idio_16_irq_unmask(struct irq_data *data)
|
||||
idio16gpio->irq_mask |= mask;
|
||||
|
||||
if (!prev_irq_mask) {
|
||||
spin_lock_irqsave(&idio16gpio->lock, flags);
|
||||
raw_spin_lock_irqsave(&idio16gpio->lock, flags);
|
||||
|
||||
inb(idio16gpio->base + 2);
|
||||
|
||||
spin_unlock_irqrestore(&idio16gpio->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -201,11 +201,11 @@ static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
|
||||
for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
|
||||
generic_handle_irq(irq_find_mapping(chip->irqdomain, gpio));
|
||||
|
||||
spin_lock(&idio16gpio->lock);
|
||||
raw_spin_lock(&idio16gpio->lock);
|
||||
|
||||
outb(0, idio16gpio->base + 1);
|
||||
|
||||
spin_unlock(&idio16gpio->lock);
|
||||
raw_spin_unlock(&idio16gpio->lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
@@ -249,7 +249,7 @@ static int idio_16_probe(struct device *dev, unsigned int id)
|
||||
idio16gpio->base = base[id];
|
||||
idio16gpio->out_state = 0xFFFF;
|
||||
|
||||
spin_lock_init(&idio16gpio->lock);
|
||||
raw_spin_lock_init(&idio16gpio->lock);
|
||||
|
||||
err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
|
||||
if (err) {
|
||||
|
||||
+12
-12
@@ -38,7 +38,7 @@
|
||||
*/
|
||||
struct altera_gpio_chip {
|
||||
struct of_mm_gpio_chip mmchip;
|
||||
spinlock_t gpio_lock;
|
||||
raw_spinlock_t gpio_lock;
|
||||
int interrupt_trigger;
|
||||
int mapped_irq;
|
||||
};
|
||||
@@ -53,12 +53,12 @@ static void altera_gpio_irq_unmask(struct irq_data *d)
|
||||
altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
|
||||
mm_gc = &altera_gc->mmchip;
|
||||
|
||||
spin_lock_irqsave(&altera_gc->gpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
|
||||
intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
|
||||
/* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
|
||||
intmask |= BIT(irqd_to_hwirq(d));
|
||||
writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
|
||||
spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
|
||||
}
|
||||
|
||||
static void altera_gpio_irq_mask(struct irq_data *d)
|
||||
@@ -71,12 +71,12 @@ static void altera_gpio_irq_mask(struct irq_data *d)
|
||||
altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
|
||||
mm_gc = &altera_gc->mmchip;
|
||||
|
||||
spin_lock_irqsave(&altera_gc->gpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
|
||||
intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
|
||||
/* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
|
||||
intmask &= ~BIT(irqd_to_hwirq(d));
|
||||
writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
|
||||
spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -140,14 +140,14 @@ static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
|
||||
mm_gc = to_of_mm_gpio_chip(gc);
|
||||
chip = gpiochip_get_data(gc);
|
||||
|
||||
spin_lock_irqsave(&chip->gpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&chip->gpio_lock, flags);
|
||||
data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
|
||||
if (value)
|
||||
data_reg |= BIT(offset);
|
||||
else
|
||||
data_reg &= ~BIT(offset);
|
||||
writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
|
||||
spin_unlock_irqrestore(&chip->gpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
|
||||
}
|
||||
|
||||
static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
|
||||
@@ -160,12 +160,12 @@ static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
|
||||
mm_gc = to_of_mm_gpio_chip(gc);
|
||||
chip = gpiochip_get_data(gc);
|
||||
|
||||
spin_lock_irqsave(&chip->gpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&chip->gpio_lock, flags);
|
||||
/* Set pin as input, assumes software controlled IP */
|
||||
gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
|
||||
gpio_ddr &= ~BIT(offset);
|
||||
writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
|
||||
spin_unlock_irqrestore(&chip->gpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -181,7 +181,7 @@ static int altera_gpio_direction_output(struct gpio_chip *gc,
|
||||
mm_gc = to_of_mm_gpio_chip(gc);
|
||||
chip = gpiochip_get_data(gc);
|
||||
|
||||
spin_lock_irqsave(&chip->gpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&chip->gpio_lock, flags);
|
||||
/* Sets the GPIO value */
|
||||
data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
|
||||
if (value)
|
||||
@@ -194,7 +194,7 @@ static int altera_gpio_direction_output(struct gpio_chip *gc,
|
||||
gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
|
||||
gpio_ddr |= BIT(offset);
|
||||
writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
|
||||
spin_unlock_irqrestore(&chip->gpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -262,7 +262,7 @@ static int altera_gpio_probe(struct platform_device *pdev)
|
||||
if (!altera_gc)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_init(&altera_gc->gpio_lock);
|
||||
raw_spin_lock_init(&altera_gc->gpio_lock);
|
||||
|
||||
if (of_property_read_u32(node, "altr,ngpio", ®))
|
||||
/* By default assume maximum ngpio */
|
||||
|
||||
@@ -17,6 +17,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
#include <linux/mfd/arizona/core.h>
|
||||
@@ -41,13 +42,38 @@ static int arizona_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct arizona_gpio *arizona_gpio = gpiochip_get_data(chip);
|
||||
struct arizona *arizona = arizona_gpio->arizona;
|
||||
unsigned int val;
|
||||
unsigned int reg, val;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(arizona->regmap, ARIZONA_GPIO1_CTRL + offset, &val);
|
||||
reg = ARIZONA_GPIO1_CTRL + offset;
|
||||
ret = regmap_read(arizona->regmap, reg, &val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Resume to read actual registers for input pins */
|
||||
if (val & ARIZONA_GPN_DIR) {
|
||||
ret = pm_runtime_get_sync(chip->parent);
|
||||
if (ret < 0) {
|
||||
dev_err(chip->parent, "Failed to resume: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Register is cached, drop it to ensure a physical read */
|
||||
ret = regcache_drop_region(arizona->regmap, reg, reg);
|
||||
if (ret < 0) {
|
||||
dev_err(chip->parent, "Failed to drop cache: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = regmap_read(arizona->regmap, reg, &val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
pm_runtime_mark_last_busy(chip->parent);
|
||||
pm_runtime_put_autosuspend(chip->parent);
|
||||
}
|
||||
|
||||
if (val & ARIZONA_GPN_LVL)
|
||||
return 1;
|
||||
else
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user