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Merge branch 'next-s3c' of git://aeryn.fluff.org.uk/bjdooks/linux into devel-stable
This commit is contained in:
Russell King
Russell King
@@ -0,0 +1,75 @@
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S3C24XX CPUfreq support
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=======================
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Introduction
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------------
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The S3C24XX series support a number of power saving systems, such as
|
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the ability to change the core, memory and peripheral operating
|
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frequencies. The core control is exported via the CPUFreq driver
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which has a number of different manual or automatic controls over the
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rate the core is running at.
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There are two forms of the driver depending on the specific CPU and
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how the clocks are arranged. The first implementation used as single
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PLL to feed the ARM, memory and peripherals via a series of dividers
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and muxes and this is the implementation that is documented here. A
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newer version where there is a seperate PLL and clock divider for the
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ARM core is available as a seperate driver.
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Layout
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------
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The code core manages the CPU specific drivers, any data that they
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need to register and the interface to the generic drivers/cpufreq
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system. Each CPU registers a driver to control the PLL, clock dividers
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and anything else associated with it. Any board that wants to use this
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framework needs to supply at least basic details of what is required.
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The core registers with drivers/cpufreq at init time if all the data
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necessary has been supplied.
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CPU support
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-----------
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The support for each CPU depends on the facilities provided by the
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SoC and the driver as each device has different PLL and clock chains
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associated with it.
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Slow Mode
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---------
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The SLOW mode where the PLL is turned off altogether and the
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system is fed by the external crystal input is currently not
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supported.
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sysfs
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-----
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The core code exports extra information via sysfs in the directory
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devices/system/cpu/cpu0/arch-freq.
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Board Support
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-------------
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Each board that wants to use the cpufreq code must register some basic
|
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information with the core driver to provide information about what the
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board requires and any restrictions being placed on it.
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The board needs to supply information about whether it needs the IO bank
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timings changing, any maximum frequency limits and information about the
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SDRAM refresh rate.
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Document Author
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---------------
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Ben Dooks, Copyright 2009 Simtec Electronics
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Licensed under GPLv2
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+73
-1
@@ -122,6 +122,13 @@ config ARCH_HAS_ILOG2_U32
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config ARCH_HAS_ILOG2_U64
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bool
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config ARCH_HAS_CPUFREQ
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bool
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help
|
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Internal node to signify that the ARCH has CPUFREQ support
|
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and that the relevant menu configurations are displayed for
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it.
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config GENERIC_HWEIGHT
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bool
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default y
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@@ -206,6 +213,7 @@ config ARCH_AAEC2000
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config ARCH_INTEGRATOR
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bool "ARM Ltd. Integrator family"
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select ARM_AMBA
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select ARCH_HAS_CPUFREQ
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select HAVE_CLK
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select COMMON_CLKDEV
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select ICST525
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@@ -512,6 +520,7 @@ config ARCH_PXA
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bool "PXA2xx/PXA3xx-based"
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depends on MMU
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select ARCH_MTD_XIP
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select ARCH_HAS_CPUFREQ
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select GENERIC_GPIO
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select HAVE_CLK
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select COMMON_CLKDEV
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@@ -554,6 +563,7 @@ config ARCH_SA1100
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select ISA
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select ARCH_SPARSEMEM_ENABLE
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select ARCH_MTD_XIP
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select ARCH_HAS_CPUFREQ
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select GENERIC_GPIO
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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@@ -566,6 +576,7 @@ config ARCH_SA1100
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config ARCH_S3C2410
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bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
|
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select GENERIC_GPIO
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select ARCH_HAS_CPUFREQ
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select HAVE_CLK
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help
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Samsung S3C2410X CPU based systems, such as the Simtec Electronics
|
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@@ -576,9 +587,18 @@ config ARCH_S3C64XX
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bool "Samsung S3C64XX"
|
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select GENERIC_GPIO
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select HAVE_CLK
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select ARCH_HAS_CPUFREQ
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help
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Samsung S3C64XX series based systems
|
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config ARCH_S5PC1XX
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bool "Samsung S5PC1XX"
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select GENERIC_GPIO
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select HAVE_CLK
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select CPU_V7
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help
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Samsung S5PC1XX series based systems
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config ARCH_SHARK
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bool "Shark"
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select CPU_SA110
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@@ -635,6 +655,7 @@ config ARCH_OMAP
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select GENERIC_GPIO
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select HAVE_CLK
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_HAS_CPUFREQ
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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help
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@@ -688,6 +709,7 @@ source "arch/arm/mach-kirkwood/Kconfig"
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source "arch/arm/plat-s3c24xx/Kconfig"
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source "arch/arm/plat-s3c64xx/Kconfig"
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source "arch/arm/plat-s3c/Kconfig"
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source "arch/arm/plat-s5pc1xx/Kconfig"
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if ARCH_S3C2410
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source "arch/arm/mach-s3c2400/Kconfig"
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@@ -705,6 +727,10 @@ endif
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source "arch/arm/plat-stmp3xxx/Kconfig"
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if ARCH_S5PC1XX
|
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source "arch/arm/mach-s5pc100/Kconfig"
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endif
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source "arch/arm/mach-lh7a40x/Kconfig"
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source "arch/arm/mach-h720x/Kconfig"
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@@ -1248,7 +1274,7 @@ endmenu
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menu "CPU Power Management"
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if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX)
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if ARCH_HAS_CPUFREQ
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source "drivers/cpufreq/Kconfig"
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|
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@@ -1283,6 +1309,52 @@ config CPU_FREQ_S3C64XX
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||||
bool "CPUfreq support for Samsung S3C64XX CPUs"
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depends on CPU_FREQ && CPU_S3C6410
|
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||||
config CPU_FREQ_S3C
|
||||
bool
|
||||
help
|
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Internal configuration node for common cpufreq on Samsung SoC
|
||||
|
||||
config CPU_FREQ_S3C24XX
|
||||
bool "CPUfreq driver for Samsung S3C24XX series CPUs"
|
||||
depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
|
||||
select CPU_FREQ_S3C
|
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help
|
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This enables the CPUfreq driver for the Samsung S3C24XX family
|
||||
of CPUs.
|
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|
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For details, take a look at <file:Documentation/cpu-freq>.
|
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|
||||
If in doubt, say N.
|
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|
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config CPU_FREQ_S3C24XX_PLL
|
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bool "Support CPUfreq changing of PLL frequency"
|
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depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
|
||||
help
|
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Compile in support for changing the PLL frequency from the
|
||||
S3C24XX series CPUfreq driver. The PLL takes time to settle
|
||||
after a frequency change, so by default it is not enabled.
|
||||
|
||||
This also means that the PLL tables for the selected CPU(s) will
|
||||
be built which may increase the size of the kernel image.
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|
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config CPU_FREQ_S3C24XX_DEBUG
|
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bool "Debug CPUfreq Samsung driver core"
|
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depends on CPU_FREQ_S3C24XX
|
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help
|
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Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
|
||||
|
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config CPU_FREQ_S3C24XX_IODEBUG
|
||||
bool "Debug CPUfreq Samsung driver IO timing"
|
||||
depends on CPU_FREQ_S3C24XX
|
||||
help
|
||||
Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
|
||||
|
||||
config CPU_FREQ_S3C24XX_DEBUGFS
|
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bool "Export debugfs for CPUFreq"
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depends on CPU_FREQ_S3C24XX && DEBUG_FS
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help
|
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Export status information via debugfs.
|
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|
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endif
|
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source "drivers/cpuidle/Kconfig"
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@@ -158,6 +158,7 @@ machine-$(CONFIG_ARCH_RPC) := rpc
|
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machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
|
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machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
|
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machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410
|
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machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100
|
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machine-$(CONFIG_ARCH_SA1100) := sa1100
|
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machine-$(CONFIG_ARCH_SHARK) := shark
|
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machine-$(CONFIG_ARCH_STMP378X) := stmp378x
|
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@@ -177,6 +178,7 @@ plat-$(CONFIG_PLAT_ORION) := orion
|
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plat-$(CONFIG_PLAT_PXA) := pxa
|
||||
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c
|
||||
plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c
|
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plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c
|
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plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
|
||||
|
||||
ifeq ($(CONFIG_ARCH_EBSA110),y)
|
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|
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File diff suppressed because it is too large
Load Diff
@@ -86,7 +86,7 @@ int show_interrupts(struct seq_file *p, void *v)
|
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unlock:
|
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spin_unlock_irqrestore(&irq_desc[i].lock, flags);
|
||||
} else if (i == NR_IRQS) {
|
||||
#ifdef CONFIG_ARCH_ACORN
|
||||
#ifdef CONFIG_FIQ
|
||||
show_fiq_list(p, v);
|
||||
#endif
|
||||
#ifdef CONFIG_SMP
|
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|
||||
@@ -12,6 +12,7 @@ config CPU_S3C2410
|
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select S3C2410_GPIO
|
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select CPU_LLSERIAL_S3C2410
|
||||
select S3C2410_PM if PM
|
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select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
|
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help
|
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Support for S3C2410 and S3C2410A family from the S3C24XX line
|
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of Samsung Mobile CPUs.
|
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@@ -45,6 +46,22 @@ config MACH_BAST_IDE
|
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Internal node for machines with an BAST style IDE
|
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interface
|
||||
|
||||
# cpu frequency scaling support
|
||||
|
||||
config S3C2410_CPUFREQ
|
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bool
|
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depends on CPU_FREQ_S3C24XX && CPU_S3C2410
|
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select S3C2410_CPUFREQ_UTILS
|
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help
|
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CPU Frequency scaling support for S3C2410
|
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|
||||
config S3C2410_PLLTABLE
|
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bool
|
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depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
|
||||
default y
|
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help
|
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Select the PLL table for the S3C2410
|
||||
|
||||
menu "S3C2410 Machines"
|
||||
|
||||
config ARCH_SMDK2410
|
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@@ -79,6 +96,7 @@ config MACH_N30
|
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config ARCH_BAST
|
||||
bool "Simtec Electronics BAST (EB2410ITX)"
|
||||
select CPU_S3C2410
|
||||
select S3C2410_IOTIMING if S3C2410_CPUFREQ
|
||||
select PM_SIMTEC if PM
|
||||
select SIMTEC_NOR
|
||||
select MACH_BAST_IDE
|
||||
|
||||
@@ -15,6 +15,8 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
|
||||
obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
|
||||
obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
|
||||
obj-$(CONFIG_S3C2410_GPIO) += gpio.o
|
||||
obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o
|
||||
obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o
|
||||
|
||||
# Machine support
|
||||
|
||||
|
||||
@@ -0,0 +1,159 @@
|
||||
/* linux/arch/arm/mach-s3c2410/cpu-freq.c
|
||||
*
|
||||
* Copyright (c) 2006,2008 Simtec Electronics
|
||||
* http://armlinux.simtec.co.uk/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C2410 CPU Frequency scaling
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu-freq-core.h>
|
||||
|
||||
/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
|
||||
|
||||
static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
|
||||
{
|
||||
u32 clkdiv = 0;
|
||||
|
||||
if (cfg->divs.h_divisor == 2)
|
||||
clkdiv |= S3C2410_CLKDIVN_HDIVN;
|
||||
|
||||
if (cfg->divs.p_divisor != cfg->divs.h_divisor)
|
||||
clkdiv |= S3C2410_CLKDIVN_PDIVN;
|
||||
|
||||
__raw_writel(clkdiv, S3C2410_CLKDIVN);
|
||||
}
|
||||
|
||||
static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
|
||||
{
|
||||
unsigned long hclk, fclk, pclk;
|
||||
unsigned int hdiv, pdiv;
|
||||
unsigned long hclk_max;
|
||||
|
||||
fclk = cfg->freq.fclk;
|
||||
hclk_max = cfg->max.hclk;
|
||||
|
||||
cfg->freq.armclk = fclk;
|
||||
|
||||
s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
|
||||
__func__, fclk, hclk_max);
|
||||
|
||||
hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
|
||||
hclk = fclk / hdiv;
|
||||
|
||||
if (hclk > cfg->max.hclk) {
|
||||
s3c_freq_dbg("%s: hclk too big\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
|
||||
pclk = hclk / pdiv;
|
||||
|
||||
if (pclk > cfg->max.pclk) {
|
||||
s3c_freq_dbg("%s: pclk too big\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pdiv *= hdiv;
|
||||
|
||||
/* record the result */
|
||||
cfg->divs.p_divisor = pdiv;
|
||||
cfg->divs.h_divisor = hdiv;
|
||||
|
||||
return 0 ;
|
||||
}
|
||||
|
||||
static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
|
||||
.max = {
|
||||
.fclk = 200000000,
|
||||
.hclk = 100000000,
|
||||
.pclk = 50000000,
|
||||
},
|
||||
|
||||
/* transition latency is about 5ms worst-case, so
|
||||
* set 10ms to be sure */
|
||||
.latency = 10000000,
|
||||
|
||||
.locktime_m = 150,
|
||||
.locktime_u = 150,
|
||||
.locktime_bits = 12,
|
||||
|
||||
.need_pll = 1,
|
||||
|
||||
.name = "s3c2410",
|
||||
.calc_iotiming = s3c2410_iotiming_calc,
|
||||
.set_iotiming = s3c2410_iotiming_set,
|
||||
.get_iotiming = s3c2410_iotiming_get,
|
||||
.resume_clocks = s3c2410_setup_clocks,
|
||||
|
||||
.set_fvco = s3c2410_set_fvco,
|
||||
.set_refresh = s3c2410_cpufreq_setrefresh,
|
||||
.set_divs = s3c2410_cpufreq_setdivs,
|
||||
.calc_divs = s3c2410_cpufreq_calcdivs,
|
||||
|
||||
.debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
|
||||
};
|
||||
|
||||
static int s3c2410_cpufreq_add(struct sys_device *sysdev)
|
||||
{
|
||||
return s3c_cpufreq_register(&s3c2410_cpufreq_info);
|
||||
}
|
||||
|
||||
static struct sysdev_driver s3c2410_cpufreq_driver = {
|
||||
.add = s3c2410_cpufreq_add,
|
||||
};
|
||||
|
||||
static int __init s3c2410_cpufreq_init(void)
|
||||
{
|
||||
return sysdev_driver_register(&s3c2410_sysclass,
|
||||
&s3c2410_cpufreq_driver);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410_cpufreq_init);
|
||||
|
||||
static int s3c2410a_cpufreq_add(struct sys_device *sysdev)
|
||||
{
|
||||
/* alter the maximum freq settings for S3C2410A. If a board knows
|
||||
* it only has a maximum of 200, then it should register its own
|
||||
* limits. */
|
||||
|
||||
s3c2410_cpufreq_info.max.fclk = 266000000;
|
||||
s3c2410_cpufreq_info.max.hclk = 133000000;
|
||||
s3c2410_cpufreq_info.max.pclk = 66500000;
|
||||
s3c2410_cpufreq_info.name = "s3c2410a";
|
||||
|
||||
return s3c2410_cpufreq_add(sysdev);
|
||||
}
|
||||
|
||||
static struct sysdev_driver s3c2410a_cpufreq_driver = {
|
||||
.add = s3c2410a_cpufreq_add,
|
||||
};
|
||||
|
||||
static int __init s3c2410a_cpufreq_init(void)
|
||||
{
|
||||
return sysdev_driver_register(&s3c2410a_sysclass,
|
||||
&s3c2410a_cpufreq_driver);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410a_cpufreq_init);
|
||||
@@ -164,6 +164,17 @@ static int __init s3c2410_dma_drvinit(void)
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410_dma_drvinit);
|
||||
|
||||
static struct sysdev_driver s3c2410a_dma_driver = {
|
||||
.add = s3c2410_dma_add,
|
||||
};
|
||||
|
||||
static int __init s3c2410a_dma_drvinit(void)
|
||||
{
|
||||
return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410a_dma_drvinit);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_S3C2442)
|
||||
|
||||
@@ -28,7 +28,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
|
||||
return NULL;
|
||||
|
||||
chip = &s3c24xx_gpios[pin/32];
|
||||
return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL;
|
||||
return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL;
|
||||
}
|
||||
|
||||
#endif /* __ASM_ARCH_GPIO_CORE_H */
|
||||
|
||||
@@ -164,6 +164,12 @@
|
||||
#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
|
||||
#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
|
||||
#else
|
||||
#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97
|
||||
#endif
|
||||
|
||||
/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
|
||||
#define FIQ_START IRQ_EINT0
|
||||
|
||||
|
||||
@@ -67,6 +67,13 @@
|
||||
#define S3C2443_PA_HSMMC (0x4A800000)
|
||||
#define S3C2443_SZ_HSMMC (256)
|
||||
|
||||
/* S3C2412 memory and IO controls */
|
||||
#define S3C2412_PA_SSMC (0x4F000000)
|
||||
#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
|
||||
|
||||
#define S3C2412_PA_EBI (0x48800000)
|
||||
#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
|
||||
|
||||
/* physical addresses of all the chip-select areas */
|
||||
|
||||
#define S3C2410_CS0 (0x00000000)
|
||||
@@ -103,5 +110,6 @@
|
||||
#define S3C_PA_UART S3C24XX_PA_UART
|
||||
#define S3C_PA_USBHOST S3C2410_PA_USBHOST
|
||||
#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
|
||||
#define S3C_PA_NAND S3C24XX_PA_NAND
|
||||
|
||||
#endif /* __ASM_ARCH_MAP_H */
|
||||
|
||||
@@ -328,13 +328,15 @@
|
||||
|
||||
#define S3C2410_GPD8_VD16 (0x02 << 16)
|
||||
#define S3C2400_GPD8_TOUT3 (0x02 << 16)
|
||||
#define S3C2440_GPD8_SPIMISO1 (0x03 << 16)
|
||||
|
||||
#define S3C2410_GPD9_VD17 (0x02 << 18)
|
||||
#define S3C2400_GPD9_TCLK0 (0x02 << 18)
|
||||
#define S3C2410_GPD9_MASK (0x03 << 18)
|
||||
#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)
|
||||
|
||||
#define S3C2410_GPD10_VD18 (0x02 << 20)
|
||||
#define S3C2400_GPD10_nWAIT (0x02 << 20)
|
||||
#define S3C2440_GPD10_SPICLK1 (0x03 << 20)
|
||||
|
||||
#define S3C2410_GPD11_VD19 (0x02 << 22)
|
||||
|
||||
|
||||
@@ -73,6 +73,16 @@
|
||||
#define S3C2410_BWSCON_WS7 (1<<30)
|
||||
#define S3C2410_BWSCON_ST7 (1<<31)
|
||||
|
||||
/* accesor functions for getting BANK(n) configuration. (n != 0) */
|
||||
|
||||
#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
|
||||
|
||||
#define S3C2410_BWSCON_DW8 (0)
|
||||
#define S3C2410_BWSCON_DW16 (1)
|
||||
#define S3C2410_BWSCON_DW32 (2)
|
||||
#define S3C2410_BWSCON_WS (1 << 2)
|
||||
#define S3C2410_BWSCON_ST (1 << 3)
|
||||
|
||||
/* memory set (rom, ram) */
|
||||
#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
|
||||
#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
|
||||
|
||||
@@ -14,9 +14,11 @@
|
||||
#ifndef __ASM_ARM_REGS_S3C2412_MEM
|
||||
#define __ASM_ARM_REGS_S3C2412_MEM
|
||||
|
||||
#ifndef S3C2412_MEMREG
|
||||
#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
|
||||
#endif
|
||||
#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
|
||||
|
||||
#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
|
||||
#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
|
||||
|
||||
#define S3C2412_BANKCFG S3C2412_MEMREG(0x00)
|
||||
#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04)
|
||||
@@ -26,4 +28,21 @@
|
||||
#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
|
||||
#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14)
|
||||
|
||||
/* EBI control registers */
|
||||
|
||||
#define S3C2412_EBI_PR S3C2412_EBIREG(0x00)
|
||||
#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04)
|
||||
|
||||
/* SSMC control registers */
|
||||
|
||||
#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00)
|
||||
#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00)
|
||||
#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04)
|
||||
#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08)
|
||||
#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C)
|
||||
#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10)
|
||||
#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14)
|
||||
#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18)
|
||||
#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C)
|
||||
|
||||
#endif /* __ASM_ARM_REGS_S3C2412_MEM */
|
||||
|
||||
@@ -30,4 +30,7 @@ extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
|
||||
extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
|
||||
int enable);
|
||||
|
||||
extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
|
||||
int enable);
|
||||
|
||||
#endif /* __ASM_ARCH_SPI_H */
|
||||
|
||||
@@ -39,9 +39,22 @@ static struct sysdev_driver s3c2410_irq_driver = {
|
||||
.resume = s3c24xx_irq_resume,
|
||||
};
|
||||
|
||||
static int s3c2410_irq_init(void)
|
||||
static int __init s3c2410_irq_init(void)
|
||||
{
|
||||
return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410_irq_init);
|
||||
|
||||
static struct sysdev_driver s3c2410a_irq_driver = {
|
||||
.add = s3c2410_irq_add,
|
||||
.suspend = s3c24xx_irq_suspend,
|
||||
.resume = s3c24xx_irq_resume,
|
||||
};
|
||||
|
||||
static int __init s3c2410a_irq_init(void)
|
||||
{
|
||||
return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_irq_driver);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410a_irq_init);
|
||||
|
||||
@@ -45,6 +45,7 @@
|
||||
#include <mach/regs-mem.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
|
||||
#include <plat/hwmon.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/iic.h>
|
||||
#include <mach/fb.h>
|
||||
@@ -59,6 +60,7 @@
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/cpu-freq.h>
|
||||
|
||||
#include "usb-simtec.h"
|
||||
#include "nor-simtec.h"
|
||||
@@ -547,7 +549,35 @@ static struct i2c_board_info bast_i2c_devs[] __initdata = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_hwmon_pdata bast_hwmon_info = {
|
||||
/* LCD contrast (0-6.6V) */
|
||||
.in[0] = &(struct s3c_hwmon_chcfg) {
|
||||
.name = "lcd-contrast",
|
||||
.mult = 3300,
|
||||
.div = 512,
|
||||
},
|
||||
/* LED current feedback */
|
||||
.in[1] = &(struct s3c_hwmon_chcfg) {
|
||||
.name = "led-feedback",
|
||||
.mult = 3300,
|
||||
.div = 1024,
|
||||
},
|
||||
/* LCD feedback (0-6.6V) */
|
||||
.in[2] = &(struct s3c_hwmon_chcfg) {
|
||||
.name = "lcd-feedback",
|
||||
.mult = 3300,
|
||||
.div = 512,
|
||||
},
|
||||
/* Vcore (1.8-2.0V), Vref 3.3V */
|
||||
.in[3] = &(struct s3c_hwmon_chcfg) {
|
||||
.name = "vcore",
|
||||
.mult = 3300,
|
||||
.div = 1024,
|
||||
},
|
||||
};
|
||||
|
||||
/* Standard BAST devices */
|
||||
// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
|
||||
|
||||
static struct platform_device *bast_devices[] __initdata = {
|
||||
&s3c_device_usb,
|
||||
@@ -556,6 +586,8 @@ static struct platform_device *bast_devices[] __initdata = {
|
||||
&s3c_device_i2c0,
|
||||
&s3c_device_rtc,
|
||||
&s3c_device_nand,
|
||||
&s3c_device_adc,
|
||||
&s3c_device_hwmon,
|
||||
&bast_device_dm9k,
|
||||
&bast_device_asix,
|
||||
&bast_device_axpp,
|
||||
@@ -570,6 +602,12 @@ static struct clk *bast_clocks[] __initdata = {
|
||||
&s3c24xx_uclk,
|
||||
};
|
||||
|
||||
static struct s3c_cpufreq_board __initdata bast_cpufreq = {
|
||||
.refresh = 7800, /* 7.8usec */
|
||||
.auto_io = 1,
|
||||
.need_io = 1,
|
||||
};
|
||||
|
||||
static void __init bast_map_io(void)
|
||||
{
|
||||
/* initialise the clocks */
|
||||
@@ -588,6 +626,7 @@ static void __init bast_map_io(void)
|
||||
s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
|
||||
|
||||
s3c_device_nand.dev.platform_data = &bast_nand_info;
|
||||
s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
|
||||
|
||||
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
@@ -608,6 +647,8 @@ static void __init bast_init(void)
|
||||
|
||||
usb_simtec_init();
|
||||
nor_simtec_init();
|
||||
|
||||
s3c_cpufreq_setboard(&bast_cpufreq);
|
||||
}
|
||||
|
||||
MACHINE_START(BAST, "Simtec-BAST")
|
||||
|
||||
@@ -0,0 +1,95 @@
|
||||
/* arch/arm/mach-s3c2410/pll.c
|
||||
*
|
||||
* Copyright (c) 2006,2007 Simtec Electronics
|
||||
* http://armlinux.simtec.co.uk/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* Vincent Sanders <vince@arm.linux.org.uk>
|
||||
*
|
||||
* S3C2410 CPU PLL tables
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/cpu-freq-core.h>
|
||||
|
||||
static struct cpufreq_frequency_table pll_vals_12MHz[] = {
|
||||
{ .frequency = 34000000, .index = PLLVAL(82, 2, 3), },
|
||||
{ .frequency = 45000000, .index = PLLVAL(82, 1, 3), },
|
||||
{ .frequency = 51000000, .index = PLLVAL(161, 3, 3), },
|
||||
{ .frequency = 48000000, .index = PLLVAL(120, 2, 3), },
|
||||
{ .frequency = 56000000, .index = PLLVAL(142, 2, 3), },
|
||||
{ .frequency = 68000000, .index = PLLVAL(82, 2, 2), },
|
||||
{ .frequency = 79000000, .index = PLLVAL(71, 1, 2), },
|
||||
{ .frequency = 85000000, .index = PLLVAL(105, 2, 2), },
|
||||
{ .frequency = 90000000, .index = PLLVAL(112, 2, 2), },
|
||||
{ .frequency = 101000000, .index = PLLVAL(127, 2, 2), },
|
||||
{ .frequency = 113000000, .index = PLLVAL(105, 1, 2), },
|
||||
{ .frequency = 118000000, .index = PLLVAL(150, 2, 2), },
|
||||
{ .frequency = 124000000, .index = PLLVAL(116, 1, 2), },
|
||||
{ .frequency = 135000000, .index = PLLVAL(82, 2, 1), },
|
||||
{ .frequency = 147000000, .index = PLLVAL(90, 2, 1), },
|
||||
{ .frequency = 152000000, .index = PLLVAL(68, 1, 1), },
|
||||
{ .frequency = 158000000, .index = PLLVAL(71, 1, 1), },
|
||||
{ .frequency = 170000000, .index = PLLVAL(77, 1, 1), },
|
||||
{ .frequency = 180000000, .index = PLLVAL(82, 1, 1), },
|
||||
{ .frequency = 186000000, .index = PLLVAL(85, 1, 1), },
|
||||
{ .frequency = 192000000, .index = PLLVAL(88, 1, 1), },
|
||||
{ .frequency = 203000000, .index = PLLVAL(161, 3, 1), },
|
||||
|
||||
/* 2410A extras */
|
||||
|
||||
{ .frequency = 210000000, .index = PLLVAL(132, 2, 1), },
|
||||
{ .frequency = 226000000, .index = PLLVAL(105, 1, 1), },
|
||||
{ .frequency = 266000000, .index = PLLVAL(125, 1, 1), },
|
||||
{ .frequency = 268000000, .index = PLLVAL(126, 1, 1), },
|
||||
{ .frequency = 270000000, .index = PLLVAL(127, 1, 1), },
|
||||
};
|
||||
|
||||
static int s3c2410_plls_add(struct sys_device *dev)
|
||||
{
|
||||
return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
|
||||
}
|
||||
|
||||
static struct sysdev_driver s3c2410_plls_drv = {
|
||||
.add = s3c2410_plls_add,
|
||||
};
|
||||
|
||||
static int __init s3c2410_pll_init(void)
|
||||
{
|
||||
return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_plls_drv);
|
||||
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410_pll_init);
|
||||
|
||||
static struct sysdev_driver s3c2410a_plls_drv = {
|
||||
.add = s3c2410_plls_add,
|
||||
};
|
||||
|
||||
static int __init s3c2410a_pll_init(void)
|
||||
{
|
||||
return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_plls_drv);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410a_pll_init);
|
||||
@@ -119,6 +119,18 @@ static int __init s3c2410_pm_drvinit(void)
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410_pm_drvinit);
|
||||
|
||||
static struct sysdev_driver s3c2410a_pm_driver = {
|
||||
.add = s3c2410_pm_add,
|
||||
.resume = s3c2410_pm_resume,
|
||||
};
|
||||
|
||||
static int __init s3c2410a_pm_drvinit(void)
|
||||
{
|
||||
return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2410a_pm_drvinit);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_S3C2440)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user