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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull "ARM: SoC specific updates" from Arnd Bergmann: "These changes are all specific to an soc family or the code for one soc. Lots of work for Tegra3 this time, but also a lot of other platforms. There will be another (smaller) set of soc patches later in the merge window for stuff that has dependencies on external trees or that was sent just before the merge window opened. The asoc tree added a few devices to the i.mx platform, which conflict with other devices added in the same place here. The tegra Makefile conflicts between a number of branches, mostly because of changes regarding localtimer.c, which was removed in the end. Signed-off-by: Arnd Bergmann <arnd@arndb.de>" Fix up some trivial conflicts, including the mentioned Tegra Makefile. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (51 commits) ARM: EXYNOS: fix cycle count for periodic mode of clock event timers ARM: EXYNOS: add support JPEG ARM: EXYNOS: Add DMC1, allow PPMU access for DMC ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata() ARM: SAMSUNG: Add __init attribute to samsung_bl_set() ARM: S5PV210: Add usb otg phy control ARM: S3C64XX: Add usb otg phy control ARM: EXYNOS: Enable l2 configuration through device tree ARM: EXYNOS: remove useless code to save/restore L2 ARM: EXYNOS: save L2 settings during bootup ARM: S5P: add L2 early resume code ARM: EXYNOS: Add support AFTR mode on EXYNOS4210 ARM: mx35: Setup the AIPS registers ARM: mx5: Use common function for configuring AIPS ARM: mx3: Setup AIPS registers ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI ARM: defconfig: imx_v6_v7: build in REGULATOR_FIXED_VOLTAGE ARM: imx: update imx_v6_v7_defconfig ARM: tegra: Demote EMC clock inconsistency BUG to WARN ...
This commit is contained in:
Linus Torvalds
@@ -1131,6 +1131,7 @@ config PLAT_VERSATILE
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config ARM_TIMER_SP804
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bool
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select CLKSRC_MMIO
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select HAVE_SCHED_CLOCK
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source arch/arm/mm/Kconfig
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@@ -0,0 +1,37 @@
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/*
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* at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
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*
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* Copyright (C) 2012 Atmel,
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* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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/dts-v1/;
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/include/ "at91sam9x5.dtsi"
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/include/ "at91sam9x5cm.dtsi"
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/ {
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model = "Atmel AT91SAM9G25-EK";
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compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
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chosen {
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bootargs = "128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
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};
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ahb {
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apb {
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dbgu: serial@fffff200 {
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status = "okay";
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};
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usart0: serial@f801c000 {
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status = "okay";
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};
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macb0: ethernet@f802c000 {
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phy-mode = "rmii";
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status = "okay";
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};
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};
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};
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};
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@@ -0,0 +1,172 @@
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/*
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* at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
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* applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
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* AT91SAM9X25, AT91SAM9X35 SoC
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*
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* Copyright (C) 2012 Atmel,
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* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Atmel AT91SAM9x5 family SoC";
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compatible = "atmel,at91sam9x5";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &dbgu;
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serial1 = &usart0;
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serial2 = &usart1;
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serial3 = &usart2;
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gpio0 = &pioA;
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gpio1 = &pioB;
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gpio2 = &pioC;
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gpio3 = &pioD;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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};
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cpus {
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cpu@0 {
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compatible = "arm,arm926ejs";
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};
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};
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memory@20000000 {
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reg = <0x20000000 0x10000000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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aic: interrupt-controller@fffff000 {
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#interrupt-cells = <2>;
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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interrupt-parent;
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reg = <0xfffff000 0x200>;
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};
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pit: timer@fffffe30 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffe30 0xf>;
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interrupts = <1 4>;
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};
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tcb0: timer@f8008000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf8008000 0x100>;
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interrupts = <17 4>;
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};
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tcb1: timer@f800c000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf800c000 0x100>;
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interrupts = <17 4>;
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};
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dma0: dma-controller@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <20 4>;
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};
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dma1: dma-controller@ffffee00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffee00 0x200>;
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interrupts = <21 4>;
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};
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pioA: gpio@fffff400 {
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffff400 0x100>;
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interrupts = <2 4>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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pioB: gpio@fffff600 {
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffff600 0x100>;
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interrupts = <2 4>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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pioC: gpio@fffff800 {
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffff800 0x100>;
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interrupts = <3 4>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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pioD: gpio@fffffa00 {
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffffa00 0x100>;
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interrupts = <3 4>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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interrupts = <1 4>;
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status = "disabled";
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};
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usart0: serial@f801c000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf801c000 0x200>;
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interrupts = <5 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart1: serial@f8020000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf8020000 0x200>;
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interrupts = <6 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart2: serial@f8024000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf8024000 0x200>;
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interrupts = <7 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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macb0: ethernet@f802c000 {
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compatible = "cdns,at32ap7000-macb", "cdns,macb";
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reg = <0xf802c000 0x100>;
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interrupts = <24 4>;
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status = "disabled";
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};
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macb1: ethernet@f8030000 {
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compatible = "cdns,at32ap7000-macb", "cdns,macb";
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reg = <0xf8030000 0x100>;
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interrupts = <27 4>;
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status = "disabled";
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};
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};
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};
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};
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@@ -0,0 +1,14 @@
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/*
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* at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
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*
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* Copyright (C) 2012 Atmel,
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* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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/ {
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memory@20000000 {
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reg = <0x20000000 0x8000000>;
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};
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};
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@@ -26,6 +26,7 @@
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/sched_clock.h>
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#include <asm/hardware/arm_timer.h>
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static long __init sp804_get_clock_rate(const char *name)
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@@ -67,7 +68,16 @@ static long __init sp804_get_clock_rate(const char *name)
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return rate;
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}
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void __init sp804_clocksource_init(void __iomem *base, const char *name)
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static void __iomem *sched_clock_base;
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static u32 sp804_read(void)
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{
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return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
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}
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void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
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const char *name,
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int use_sched_clock)
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{
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long rate = sp804_get_clock_rate(name);
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@@ -83,6 +93,11 @@ void __init sp804_clocksource_init(void __iomem *base, const char *name)
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clocksource_mmio_init(base + TIMER_VALUE, name,
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rate, 200, 32, clocksource_mmio_readl_down);
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if (use_sched_clock) {
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sched_clock_base = base;
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setup_sched_clock(sp804_read, 32, rate);
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}
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}
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@@ -5,6 +5,7 @@ CONFIG_SYSVIPC=y
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CONFIG_LOG_BUF_SHIFT=18
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CONFIG_CGROUPS=y
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CONFIG_RELAY=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_EXPERT=y
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# CONFIG_SLUB_DEBUG is not set
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# CONFIG_COMPAT_BRK is not set
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@@ -12,7 +13,6 @@ CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODVERSIONS=y
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CONFIG_MODULE_SRCVERSION_ALL=y
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# CONFIG_LBDAF is not set
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_ARCH_MXC=y
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CONFIG_MACH_MX31LILLY=y
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@@ -26,7 +26,6 @@ CONFIG_MACH_ARMADILLO5X0=y
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CONFIG_MACH_KZM_ARM11_01=y
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CONFIG_MACH_PCM043=y
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CONFIG_MACH_MX35_3DS=y
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CONFIG_MACH_EUKREA_CPUIMX35=y
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CONFIG_MACH_VPR200=y
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CONFIG_MACH_IMX51_DT=y
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CONFIG_MACH_MX51_3DS=y
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@@ -83,7 +82,6 @@ CONFIG_NETDEVICES=y
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# CONFIG_NET_VENDOR_BROADCOM is not set
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# CONFIG_NET_VENDOR_CHELSIO is not set
|
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# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
CONFIG_FEC=y
|
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# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
@@ -126,6 +124,7 @@ CONFIG_WATCHDOG=y
|
||||
CONFIG_IMX2_WDT=y
|
||||
CONFIG_MFD_MC13XXX=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_MC13892=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -77,10 +77,10 @@ CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=m
|
||||
CONFIG_I2C=y
|
||||
# CONFIG_I2C_COMPAT is not set
|
||||
CONFIG_I2C_CHARDEV=m
|
||||
CONFIG_I2C_MXS=m
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MXS=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_GPIO=m
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
@@ -90,6 +90,20 @@ CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_DISPLAY_SUPPORT=m
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_TIMER=y
|
||||
CONFIG_SND_PCM=y
|
||||
CONFIG_SND_JACK=y
|
||||
CONFIG_SND_DRIVERS=y
|
||||
CONFIG_SND_ARM=y
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_MXS_SOC=y
|
||||
CONFIG_SND_SOC_MXS_SGTL5000=y
|
||||
CONFIG_SND_SOC_I2C_AND_SPI=y
|
||||
CONFIG_SND_SOC_SGTL5000=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_MXS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
|
||||
@@ -1,2 +1,15 @@
|
||||
void sp804_clocksource_init(void __iomem *, const char *);
|
||||
void __sp804_clocksource_and_sched_clock_init(void __iomem *,
|
||||
const char *, int);
|
||||
|
||||
static inline void sp804_clocksource_init(void __iomem *base, const char *name)
|
||||
{
|
||||
__sp804_clocksource_and_sched_clock_init(base, name, 0);
|
||||
}
|
||||
|
||||
static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base,
|
||||
const char *name)
|
||||
{
|
||||
__sp804_clocksource_and_sched_clock_init(base, name, 1);
|
||||
}
|
||||
|
||||
void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
|
||||
|
||||
@@ -102,6 +102,15 @@ config ARCH_AT91SAM9G45
|
||||
select HAVE_AT91_DBGU1
|
||||
select AT91_SAM9G45_RESET
|
||||
|
||||
config ARCH_AT91SAM9X5
|
||||
bool "AT91SAM9x5 family"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
select HAVE_AT91_DBGU0
|
||||
select AT91_SAM9G45_RESET
|
||||
|
||||
config ARCH_AT91X40
|
||||
bool "AT91x40"
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
|
||||
@@ -20,6 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_d
|
||||
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o
|
||||
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
|
||||
|
||||
# AT91RM9200 board-specific support
|
||||
|
||||
@@ -0,0 +1,373 @@
|
||||
/*
|
||||
* Chip-specific setup code for the AT91SAM9x5 family
|
||||
*
|
||||
* Copyright (C) 2010-2012 Atmel Corporation.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/at91sam9x5.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/board.h>
|
||||
|
||||
#include "soc.h"
|
||||
#include "generic.h"
|
||||
#include "clock.h"
|
||||
#include "sam9_smc.h"
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Clocks
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* The peripheral clocks.
|
||||
*/
|
||||
static struct clk pioAB_clk = {
|
||||
.name = "pioAB_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioCD_clk = {
|
||||
.name = "pioCD_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk smd_clk = {
|
||||
.name = "smd_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_SMD,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart0_clk = {
|
||||
.name = "usart0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_USART0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart1_clk = {
|
||||
.name = "usart1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_USART1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart2_clk = {
|
||||
.name = "usart2_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_USART2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* USART3 clock - Only for sam9g25/sam9x25 */
|
||||
static struct clk usart3_clk = {
|
||||
.name = "usart3_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_USART3,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi0_clk = {
|
||||
.name = "twi0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi1_clk = {
|
||||
.name = "twi1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi2_clk = {
|
||||
.name = "twi2_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mmc0_clk = {
|
||||
.name = "mci0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi0_clk = {
|
||||
.name = "spi0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi1_clk = {
|
||||
.name = "spi1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uart0_clk = {
|
||||
.name = "uart0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_UART0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uart1_clk = {
|
||||
.name = "uart1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_UART1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tcb0_clk = {
|
||||
.name = "tcb0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_TCB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pwm_clk = {
|
||||
.name = "pwm_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_PWM,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk adc_clk = {
|
||||
.name = "adc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_ADC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk dma0_clk = {
|
||||
.name = "dma0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk dma1_clk = {
|
||||
.name = "dma1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uhphs_clk = {
|
||||
.name = "uhphs_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk udphs_clk = {
|
||||
.name = "udphs_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
|
||||
static struct clk macb0_clk = {
|
||||
.name = "pclk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
|
||||
static struct clk lcdc_clk = {
|
||||
.name = "lcdc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* isi clock - Only for sam9g25 */
|
||||
static struct clk isi_clk = {
|
||||
.name = "isi_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_ISI,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mmc1_clk = {
|
||||
.name = "mci1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* emac1 clock - Only for sam9x25 */
|
||||
static struct clk macb1_clk = {
|
||||
.name = "pclk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc_clk = {
|
||||
.name = "ssc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_SSC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* can0 clock - Only for sam9x35 */
|
||||
static struct clk can0_clk = {
|
||||
.name = "can0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
/* can1 clock - Only for sam9x35 */
|
||||
static struct clk can1_clk = {
|
||||
.name = "can1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
|
||||
static struct clk *periph_clocks[] __initdata = {
|
||||
&pioAB_clk,
|
||||
&pioCD_clk,
|
||||
&smd_clk,
|
||||
&usart0_clk,
|
||||
&usart1_clk,
|
||||
&usart2_clk,
|
||||
&twi0_clk,
|
||||
&twi1_clk,
|
||||
&twi2_clk,
|
||||
&mmc0_clk,
|
||||
&spi0_clk,
|
||||
&spi1_clk,
|
||||
&uart0_clk,
|
||||
&uart1_clk,
|
||||
&tcb0_clk,
|
||||
&pwm_clk,
|
||||
&adc_clk,
|
||||
&dma0_clk,
|
||||
&dma1_clk,
|
||||
&uhphs_clk,
|
||||
&udphs_clk,
|
||||
&mmc1_clk,
|
||||
&ssc_clk,
|
||||
// irq0
|
||||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
/* lookup table for DT entries */
|
||||
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
|
||||
CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
|
||||
CLKDEV_CON_ID("pioA", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioB", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioC", &pioCD_clk),
|
||||
CLKDEV_CON_ID("pioD", &pioCD_clk),
|
||||
/* additional fake clock for macb_hclk */
|
||||
CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
|
||||
};
|
||||
|
||||
/*
|
||||
* The two programmable clocks.
|
||||
* You must configure pin multiplexing to bring these signals out.
|
||||
*/
|
||||
static struct clk pck0 = {
|
||||
.name = "pck0",
|
||||
.pmc_mask = AT91_PMC_PCK0,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 0,
|
||||
};
|
||||
static struct clk pck1 = {
|
||||
.name = "pck1",
|
||||
.pmc_mask = AT91_PMC_PCK1,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 1,
|
||||
};
|
||||
|
||||
static void __init at91sam9x5_register_clocks(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
||||
clk_register(periph_clocks[i]);
|
||||
|
||||
clkdev_add_table(periph_clocks_lookups,
|
||||
ARRAY_SIZE(periph_clocks_lookups));
|
||||
|
||||
if (cpu_is_at91sam9g25()
|
||||
|| cpu_is_at91sam9x25())
|
||||
clk_register(&usart3_clk);
|
||||
|
||||
if (cpu_is_at91sam9g25()
|
||||
|| cpu_is_at91sam9x25()
|
||||
|| cpu_is_at91sam9g35()
|
||||
|| cpu_is_at91sam9x35())
|
||||
clk_register(&macb0_clk);
|
||||
|
||||
if (cpu_is_at91sam9g15()
|
||||
|| cpu_is_at91sam9g35()
|
||||
|| cpu_is_at91sam9x35())
|
||||
clk_register(&lcdc_clk);
|
||||
|
||||
if (cpu_is_at91sam9g25())
|
||||
clk_register(&isi_clk);
|
||||
|
||||
if (cpu_is_at91sam9x25())
|
||||
clk_register(&macb1_clk);
|
||||
|
||||
if (cpu_is_at91sam9x25()
|
||||
|| cpu_is_at91sam9x35()) {
|
||||
clk_register(&can0_clk);
|
||||
clk_register(&can1_clk);
|
||||
}
|
||||
|
||||
clk_register(&pck0);
|
||||
clk_register(&pck1);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT91SAM9x5 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9x5_map_io(void)
|
||||
{
|
||||
at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
|
||||
}
|
||||
|
||||
static void __init at91sam9x5_ioremap_registers(void)
|
||||
{
|
||||
if (of_at91sam926x_pit_init() < 0)
|
||||
panic("Impossible to find PIT\n");
|
||||
}
|
||||
|
||||
void __init at91sam9x5_initialize(void)
|
||||
{
|
||||
arm_pm_restart = at91sam9g45_restart;
|
||||
at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
|
||||
|
||||
/* Register GPIO subsystem (using DT) */
|
||||
at91_gpio_init(NULL, 0);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT91SAM9x5 devices (temporary before modification of code)
|
||||
* -------------------------------------------------------------------- */
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||
void __init at91_set_serial_console(unsigned portnr) {}
|
||||
struct platform_device *atmel_default_console_device = NULL;
|
||||
|
||||
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Interrupt initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* The default interrupt priority levels (0 = lowest, 7 = highest).
|
||||
*/
|
||||
static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
||||
7, /* Advanced Interrupt Controller (FIQ) */
|
||||
7, /* System Peripherals */
|
||||
1, /* Parallel IO Controller A and B */
|
||||
1, /* Parallel IO Controller C and D */
|
||||
4, /* Soft Modem */
|
||||
5, /* USART 0 */
|
||||
5, /* USART 1 */
|
||||
5, /* USART 2 */
|
||||
5, /* USART 3 */
|
||||
6, /* Two-Wire Interface 0 */
|
||||
6, /* Two-Wire Interface 1 */
|
||||
6, /* Two-Wire Interface 2 */
|
||||
0, /* Multimedia Card Interface 0 */
|
||||
5, /* Serial Peripheral Interface 0 */
|
||||
5, /* Serial Peripheral Interface 1 */
|
||||
5, /* UART 0 */
|
||||
5, /* UART 1 */
|
||||
0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
0, /* Pulse Width Modulation Controller */
|
||||
0, /* ADC Controller */
|
||||
0, /* DMA Controller 0 */
|
||||
0, /* DMA Controller 1 */
|
||||
2, /* USB Host High Speed port */
|
||||
2, /* USB Device High speed port */
|
||||
3, /* Ethernet MAC 0 */
|
||||
3, /* LDC Controller or Image Sensor Interface */
|
||||
0, /* Multimedia Card Interface 1 */
|
||||
3, /* Ethernet MAC 1 */
|
||||
4, /* Synchronous Serial Interface */
|
||||
4, /* CAN Controller 0 */
|
||||
4, /* CAN Controller 1 */
|
||||
0, /* Advanced Interrupt Controller (IRQ0) */
|
||||
};
|
||||
|
||||
struct at91_init_soc __initdata at91sam9x5_soc = {
|
||||
.map_io = at91sam9x5_map_io,
|
||||
.default_irq_priority = at91sam9x5_default_irq_priority,
|
||||
.ioremap_registers = at91sam9x5_ioremap_registers,
|
||||
.register_clocks = at91sam9x5_register_clocks,
|
||||
.init = at91sam9x5_initialize,
|
||||
};
|
||||
@@ -109,6 +109,7 @@ static void __init at91_dt_device_init(void)
|
||||
|
||||
static const char *at91_dt_board_compat[] __initdata = {
|
||||
"atmel,at91sam9m10g45ek",
|
||||
"atmel,at91sam9x5ek",
|
||||
"calao,usb-a9g20",
|
||||
NULL
|
||||
};
|
||||
|
||||
+64
-19
@@ -48,24 +48,37 @@
|
||||
* Chips have some kind of clocks : group them by functionality
|
||||
*/
|
||||
#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45())
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|
||||
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|
||||
|| cpu_is_at91sam9g45())
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|
||||
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
|
||||
|
||||
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45()))
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5()))
|
||||
|
||||
#define cpu_has_upll() (cpu_is_at91sam9g45())
|
||||
#define cpu_has_upll() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|
||||
/* USB host HS & FS */
|
||||
#define cpu_has_uhp() (!cpu_is_at91sam9rl())
|
||||
|
||||
/* USB device FS only */
|
||||
#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45()))
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5()))
|
||||
|
||||
#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|
||||
#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|
||||
#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
|
||||
|
||||
static LIST_HEAD(clocks);
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
@@ -138,13 +151,6 @@ static void pmc_uckr_mode(struct clk *clk, int is_on)
|
||||
{
|
||||
unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
|
||||
|
||||
if (cpu_is_at91sam9g45()) {
|
||||
if (is_on)
|
||||
uckr |= AT91_PMC_BIASEN;
|
||||
else
|
||||
uckr &= ~AT91_PMC_BIASEN;
|
||||
}
|
||||
|
||||
if (is_on) {
|
||||
is_on = AT91_PMC_LOCKU;
|
||||
at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
|
||||
@@ -209,11 +215,24 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
|
||||
return &utmi_clk;
|
||||
else if (cpu_has_pllb())
|
||||
return &pllb;
|
||||
break;
|
||||
/* alternate PMC: can use master clock */
|
||||
case AT91_PMC_CSS_MASTER:
|
||||
return &mck;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int pmc_prescaler_divider(u32 reg)
|
||||
{
|
||||
if (cpu_has_alt_prescaler()) {
|
||||
return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
|
||||
} else {
|
||||
return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
static void __clk_enable(struct clk *clk)
|
||||
{
|
||||
if (clk->parent)
|
||||
@@ -315,12 +334,22 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned prescale;
|
||||
unsigned long prescale_offset, css_mask;
|
||||
unsigned long actual;
|
||||
|
||||
if (!clk_is_programmable(clk))
|
||||
return -EINVAL;
|
||||
if (clk->users)
|
||||
return -EBUSY;
|
||||
|
||||
if (cpu_has_alt_prescaler()) {
|
||||
prescale_offset = PMC_ALT_PRES_OFFSET;
|
||||
css_mask = AT91_PMC_ALT_PCKR_CSS;
|
||||
} else {
|
||||
prescale_offset = PMC_PRES_OFFSET;
|
||||
css_mask = AT91_PMC_CSS;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&clk_lock, flags);
|
||||
|
||||
actual = clk->parent->rate_hz;
|
||||
@@ -329,8 +358,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
u32 pckr;
|
||||
|
||||
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
||||
pckr &= AT91_PMC_CSS; /* clock selection */
|
||||
pckr |= prescale << 2;
|
||||
pckr &= css_mask; /* keep clock selection */
|
||||
pckr |= prescale << prescale_offset;
|
||||
at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
|
||||
clk->rate_hz = actual;
|
||||
break;
|
||||
@@ -377,11 +406,17 @@ static void __init init_programmable_clock(struct clk *clk)
|
||||
{
|
||||
struct clk *parent;
|
||||
u32 pckr;
|
||||
unsigned int css_mask;
|
||||
|
||||
if (cpu_has_alt_prescaler())
|
||||
css_mask = AT91_PMC_ALT_PCKR_CSS;
|
||||
else
|
||||
css_mask = AT91_PMC_CSS;
|
||||
|
||||
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
||||
parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
|
||||
parent = at91_css_to_clk(pckr & css_mask);
|
||||
clk->parent = parent;
|
||||
clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
|
||||
clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
|
||||
@@ -663,7 +698,7 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||
if (pll_overclock)
|
||||
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
|
||||
|
||||
if (cpu_is_at91sam9g45()) {
|
||||
if (cpu_has_plladiv2()) {
|
||||
mckr = at91_sys_read(AT91_PMC_MCKR);
|
||||
plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
|
||||
}
|
||||
@@ -685,6 +720,10 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||
* (obtain the USB High Speed 480 MHz when input is 12 MHz)
|
||||
*/
|
||||
utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
|
||||
|
||||
/* UTMI bias and PLL are managed at the same time */
|
||||
if (cpu_has_upll())
|
||||
utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -703,7 +742,7 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||
mckr = at91_sys_read(AT91_PMC_MCKR);
|
||||
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
|
||||
freq = mck.parent->rate_hz;
|
||||
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
|
||||
freq /= pmc_prescaler_divider(mckr); /* prescale */
|
||||
if (cpu_is_at91rm9200()) {
|
||||
mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||
} else if (cpu_is_at91sam9g20()) {
|
||||
@@ -711,13 +750,19 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||
freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
|
||||
if (mckr & AT91_PMC_PDIV)
|
||||
freq /= 2; /* processor clock division */
|
||||
} else if (cpu_is_at91sam9g45()) {
|
||||
} else if (cpu_has_mdiv3()) {
|
||||
mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
|
||||
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||
} else {
|
||||
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||
}
|
||||
|
||||
if (cpu_has_alt_prescaler()) {
|
||||
/* Programmable clocks can use MCK */
|
||||
mck.type |= CLK_TYPE_PRIMARY;
|
||||
mck.id = 4;
|
||||
}
|
||||
|
||||
/* Register the PMC's standard clocks */
|
||||
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
|
||||
at91_clk_add(standard_pmc_clocks[i]);
|
||||
|
||||
@@ -45,9 +45,13 @@
|
||||
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
|
||||
|
||||
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
|
||||
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
||||
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */
|
||||
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
||||
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
||||
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
|
||||
#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
|
||||
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
||||
#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
|
||||
#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
|
||||
#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
|
||||
|
||||
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
|
||||
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
|
||||
@@ -72,14 +76,24 @@
|
||||
#define AT91_PMC_CSS_PLLA (2 << 0)
|
||||
#define AT91_PMC_CSS_PLLB (3 << 0)
|
||||
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
|
||||
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
|
||||
#define AT91_PMC_PRES_1 (0 << 2)
|
||||
#define AT91_PMC_PRES_2 (1 << 2)
|
||||
#define AT91_PMC_PRES_4 (2 << 2)
|
||||
#define AT91_PMC_PRES_8 (3 << 2)
|
||||
#define AT91_PMC_PRES_16 (4 << 2)
|
||||
#define AT91_PMC_PRES_32 (5 << 2)
|
||||
#define AT91_PMC_PRES_64 (6 << 2)
|
||||
#define PMC_PRES_OFFSET 2
|
||||
#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
|
||||
#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET)
|
||||
#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET)
|
||||
#define PMC_ALT_PRES_OFFSET 4
|
||||
#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */
|
||||
#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET)
|
||||
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
|
||||
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
|
||||
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
|
||||
@@ -103,7 +117,14 @@
|
||||
#define AT91_PMC_USBS_UPLL (1 << 0)
|
||||
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
|
||||
|
||||
#define AT91_PMC_SMD (AT91_PMC + 0x3c) /* Soft Modem Clock Register [some SAM9 only] */
|
||||
#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
|
||||
#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
|
||||
#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
|
||||
|
||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
|
||||
#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
|
||||
#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
|
||||
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
|
||||
#define AT91_PMC_CSSMCK_CSS (0 << 8)
|
||||
#define AT91_PMC_CSSMCK_MCK (1 << 8)
|
||||
@@ -120,10 +141,25 @@
|
||||
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
||||
#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
|
||||
#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
|
||||
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
|
||||
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Write Protect Mode Register [some SAM9] */
|
||||
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
|
||||
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
|
||||
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
|
||||
#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
|
||||
|
||||
#define AT91_PMC_WPSR (AT91_PMC + 0xe8) /* Write Protect Status Register [some SAM9] */
|
||||
#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
|
||||
|
||||
#define AT91_PMC_PCR (AT91_PMC + 0x10c) /* Peripheral Control Register [some SAM9] */
|
||||
#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
|
||||
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */
|
||||
#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */
|
||||
#define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV)
|
||||
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Chip-specific header file for the AT91SAM9x5 family
|
||||
*
|
||||
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9x5 datasheet.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9X5_H
|
||||
#define AT91SAM9X5_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
|
||||
#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
|
||||
#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
|
||||
#define AT91SAM9X5_ID_USART0 5 /* USART 0 */
|
||||
#define AT91SAM9X5_ID_USART1 6 /* USART 1 */
|
||||
#define AT91SAM9X5_ID_USART2 7 /* USART 2 */
|
||||
#define AT91SAM9X5_ID_USART3 8 /* USART 3 */
|
||||
#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */
|
||||
#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */
|
||||
#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */
|
||||
#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */
|
||||
#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9X5_ID_UART0 15 /* UART 0 */
|
||||
#define AT91SAM9X5_ID_UART1 16 /* UART 1 */
|
||||
#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */
|
||||
#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */
|
||||
#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */
|
||||
#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */
|
||||
#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */
|
||||
#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */
|
||||
#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */
|
||||
#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */
|
||||
#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */
|
||||
#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */
|
||||
#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */
|
||||
#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */
|
||||
#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */
|
||||
#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9X5_BASE_USART0 0xf801c000
|
||||
#define AT91SAM9X5_BASE_USART1 0xf8020000
|
||||
#define AT91SAM9X5_BASE_USART2 0xf8024000
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
|
||||
/*
|
||||
* Base addresses for early serial code (uncompress.h)
|
||||
*/
|
||||
#define AT91_DBGU AT91_BASE_DBGU0
|
||||
#define AT91_USART0 AT91SAM9X5_BASE_USART0
|
||||
#define AT91_USART1 AT91SAM9X5_BASE_USART1
|
||||
#define AT91_USART2 AT91SAM9X5_BASE_USART2
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
|
||||
|
||||
#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Matrix-centric header file for the AT91SAM9x5 family
|
||||
*
|
||||
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||
*
|
||||
* Only EBI related registers.
|
||||
* Write Protect register definitions may be useful.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9X5_MATRIX_H
|
||||
#define AT91SAM9X5_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
|
||||
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
|
||||
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
|
||||
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
|
||||
#define AT91_MATRIX_MP_OFF (0 << 25)
|
||||
#define AT91_MATRIX_MP_ON (1 << 25)
|
||||
|
||||
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
||||
@@ -34,6 +34,8 @@
|
||||
#include <mach/at91sam9rl.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
#include <mach/at91sam9g45.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9X5)
|
||||
#include <mach/at91sam9x5.h>
|
||||
#elif defined(CONFIG_ARCH_AT91X40)
|
||||
#include <mach/at91x40.h>
|
||||
#else
|
||||
|
||||
@@ -470,6 +470,11 @@ static struct clk exynos4_init_clocks_off[] = {
|
||||
.devname = "s5p-mipi-csis.1",
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}, {
|
||||
.name = "jpeg",
|
||||
.id = 0,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 6),
|
||||
}, {
|
||||
.name = "fimc",
|
||||
.devname = "exynos4-fimc.0",
|
||||
|
||||
@@ -26,10 +26,12 @@
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include <mach/regs-irq.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/pmu.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clock.h>
|
||||
@@ -45,6 +47,8 @@
|
||||
#include <plat/regs-serial.h>
|
||||
|
||||
#include "common.h"
|
||||
#define L2_AUX_VAL 0x7C470001
|
||||
#define L2_AUX_MASK 0xC200ffff
|
||||
|
||||
static const char name_exynos4210[] = "EXYNOS4210";
|
||||
static const char name_exynos4212[] = "EXYNOS4212";
|
||||
@@ -173,7 +177,12 @@ static struct map_desc exynos4_iodesc[] __initdata = {
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_DMC0,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
|
||||
.length = SZ_4K,
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_DMC1,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_USB_HSPHY,
|
||||
@@ -433,23 +442,48 @@ core_initcall(exynos4_core_init);
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
static int __init exynos4_l2x0_cache_init(void)
|
||||
{
|
||||
/* TAG, Data Latency Control: 2cycle */
|
||||
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
|
||||
int ret;
|
||||
ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
|
||||
if (!ret) {
|
||||
l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
|
||||
clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
|
||||
else if (soc_is_exynos4212() || soc_is_exynos4412())
|
||||
__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
|
||||
if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
|
||||
l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
|
||||
/* TAG, Data Latency Control: 2 cycles */
|
||||
l2x0_saved_regs.tag_latency = 0x110;
|
||||
|
||||
/* L2X0 Prefetch Control */
|
||||
__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
|
||||
if (soc_is_exynos4212() || soc_is_exynos4412())
|
||||
l2x0_saved_regs.data_latency = 0x120;
|
||||
else
|
||||
l2x0_saved_regs.data_latency = 0x110;
|
||||
|
||||
/* L2X0 Power Control */
|
||||
__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
|
||||
S5P_VA_L2CC + L2X0_POWER_CTRL);
|
||||
l2x0_saved_regs.prefetch_ctrl = 0x30000007;
|
||||
l2x0_saved_regs.pwr_ctrl =
|
||||
(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
|
||||
|
||||
l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
|
||||
l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
|
||||
|
||||
__raw_writel(l2x0_saved_regs.tag_latency,
|
||||
S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
|
||||
__raw_writel(l2x0_saved_regs.data_latency,
|
||||
S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
|
||||
|
||||
/* L2X0 Prefetch Control */
|
||||
__raw_writel(l2x0_saved_regs.prefetch_ctrl,
|
||||
S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
|
||||
|
||||
/* L2X0 Power Control */
|
||||
__raw_writel(l2x0_saved_regs.pwr_ctrl,
|
||||
S5P_VA_L2CC + L2X0_POWER_CTRL);
|
||||
|
||||
clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
|
||||
clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
|
||||
}
|
||||
|
||||
l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -11,25 +11,53 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/cpuidle.h>
|
||||
#include <linux/cpu_pm.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/time.h>
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/suspend.h>
|
||||
#include <asm/unified.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
#include <mach/pmu.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
|
||||
S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
|
||||
(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
|
||||
#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
|
||||
S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
|
||||
(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
|
||||
|
||||
#define S5P_CHECK_AFTR 0xFCBA0D10
|
||||
|
||||
static int exynos4_enter_idle(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index);
|
||||
static int exynos4_enter_lowpower(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index);
|
||||
|
||||
static struct cpuidle_state exynos4_cpuidle_set[] = {
|
||||
static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
|
||||
[0] = {
|
||||
.enter = exynos4_enter_idle,
|
||||
.exit_latency = 1,
|
||||
.target_residency = 100000,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.name = "IDLE",
|
||||
.name = "C0",
|
||||
.desc = "ARM clock gating(WFI)",
|
||||
},
|
||||
[1] = {
|
||||
.enter = exynos4_enter_lowpower,
|
||||
.exit_latency = 300,
|
||||
.target_residency = 100000,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.name = "C1",
|
||||
.desc = "ARM power down",
|
||||
},
|
||||
};
|
||||
|
||||
static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
|
||||
@@ -39,9 +67,102 @@ static struct cpuidle_driver exynos4_idle_driver = {
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
|
||||
static void exynos4_set_wakeupmask(void)
|
||||
{
|
||||
__raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
|
||||
}
|
||||
|
||||
static unsigned int g_pwr_ctrl, g_diag_reg;
|
||||
|
||||
static void save_cpu_arch_register(void)
|
||||
{
|
||||
/*read power control register*/
|
||||
asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
|
||||
/*read diagnostic register*/
|
||||
asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
|
||||
return;
|
||||
}
|
||||
|
||||
static void restore_cpu_arch_register(void)
|
||||
{
|
||||
/*write power control register*/
|
||||
asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
|
||||
/*write diagnostic register*/
|
||||
asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
|
||||
return;
|
||||
}
|
||||
|
||||
static int idle_finisher(unsigned long flags)
|
||||
{
|
||||
cpu_do_idle();
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
struct timeval before, after;
|
||||
int idle_time;
|
||||
unsigned long tmp;
|
||||
|
||||
local_irq_disable();
|
||||
do_gettimeofday(&before);
|
||||
|
||||
exynos4_set_wakeupmask();
|
||||
|
||||
/* Set value of power down register for aftr mode */
|
||||
exynos4_sys_powerdown_conf(SYS_AFTR);
|
||||
|
||||
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
|
||||
__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
|
||||
|
||||
save_cpu_arch_register();
|
||||
|
||||
/* Setting Central Sequence Register for power down mode */
|
||||
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
|
||||
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
|
||||
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
|
||||
|
||||
cpu_pm_enter();
|
||||
cpu_suspend(0, idle_finisher);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
scu_enable(S5P_VA_SCU);
|
||||
#endif
|
||||
cpu_pm_exit();
|
||||
|
||||
restore_cpu_arch_register();
|
||||
|
||||
/*
|
||||
* If PMU failed while entering sleep mode, WFI will be
|
||||
* ignored by PMU and then exiting cpu_do_idle().
|
||||
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
|
||||
* in this situation.
|
||||
*/
|
||||
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
|
||||
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
|
||||
tmp |= S5P_CENTRAL_LOWPWR_CFG;
|
||||
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
|
||||
}
|
||||
|
||||
/* Clear wakeup state register */
|
||||
__raw_writel(0x0, S5P_WAKEUP_STAT);
|
||||
|
||||
do_gettimeofday(&after);
|
||||
|
||||
local_irq_enable();
|
||||
idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
|
||||
(after.tv_usec - before.tv_usec);
|
||||
|
||||
dev->last_residency = idle_time;
|
||||
return index;
|
||||
}
|
||||
|
||||
static int exynos4_enter_idle(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
int index)
|
||||
{
|
||||
struct timeval before, after;
|
||||
int idle_time;
|
||||
@@ -60,6 +181,22 @@ static int exynos4_enter_idle(struct cpuidle_device *dev,
|
||||
return index;
|
||||
}
|
||||
|
||||
static int exynos4_enter_lowpower(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
int new_index = index;
|
||||
|
||||
/* This mode only can be entered when other core's are offline */
|
||||
if (num_online_cpus() > 1)
|
||||
new_index = drv->safe_state_index;
|
||||
|
||||
if (new_index == 0)
|
||||
return exynos4_enter_idle(dev, drv, new_index);
|
||||
else
|
||||
return exynos4_enter_core0_aftr(dev, drv, new_index);
|
||||
}
|
||||
|
||||
static int __init exynos4_init_cpuidle(void)
|
||||
{
|
||||
int i, max_cpuidle_state, cpu_id;
|
||||
@@ -74,19 +211,25 @@ static int __init exynos4_init_cpuidle(void)
|
||||
memcpy(&drv->states[i], &exynos4_cpuidle_set[i],
|
||||
sizeof(struct cpuidle_state));
|
||||
}
|
||||
drv->safe_state_index = 0;
|
||||
cpuidle_register_driver(&exynos4_idle_driver);
|
||||
|
||||
for_each_cpu(cpu_id, cpu_online_mask) {
|
||||
device = &per_cpu(exynos4_cpuidle_device, cpu_id);
|
||||
device->cpu = cpu_id;
|
||||
|
||||
device->state_count = drv->state_count;
|
||||
if (cpu_id == 0)
|
||||
device->state_count = (sizeof(exynos4_cpuidle_set) /
|
||||
sizeof(struct cpuidle_state));
|
||||
else
|
||||
device->state_count = 1; /* Support IDLE only */
|
||||
|
||||
if (cpuidle_register_device(device)) {
|
||||
printk(KERN_ERR "CPUidle register device failed\n,");
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(exynos4_init_cpuidle);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user