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Merge tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc clock driver changes from Olof Johansson: "The new clock subsystem was merged in linux-3.4 without any users, this now moves the first three platforms over to it: imx, mxs and spear. The series also contains the changes for the clock subsystem itself, since Mike preferred to have it together with the platforms that require these changes, in order to avoid interdependencies and conflicts." Fix up trivial conflicts in arch/arm/mach-kirkwood/common.c (code removed in one branch, added OF support in another) and drivers/dma/imx-sdma.c (independent changes next to each other). * tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (97 commits) clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate(). clk: Provide dummy clk_unregister() SPEAr: Update defconfigs SPEAr: Add SMI NOR partition info in dts files SPEAr: Switch to common clock framework SPEAr: Call clk_prepare() before calling clk_enable SPEAr: clk: Add General Purpose Timer Synthesizer clock SPEAr: clk: Add Fractional Synthesizer clock SPEAr: clk: Add Auxiliary Synthesizer clock SPEAr: clk: Add VCO-PLL Synthesizer clock SPEAr: Add DT bindings for SPEAr's timer ARM i.MX: remove now unused clock files ARM: i.MX6: implement clocks using common clock framework ARM i.MX35: implement clocks using common clock framework ARM i.MX5: implement clocks using common clock framework ARM: Kirkwood: Replace clock gating ARM: Orion: Audio: Add clk/clkdev support ARM: Orion: PCIE: Add support for clk ARM: Orion: XOR: Add support for clk ARM: Orion: CESA: Add support for clk ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,18 @@
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* SPEAr ARM Timer
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** Timer node required properties:
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- compatible : Should be:
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"st,spear-timer"
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- reg: Address range of the timer registers
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- interrupt-parent: Should be the phandle for the interrupt controller
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that services interrupts for this device
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- interrupt: Should contain the timer interrupt number
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Example:
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timer@f0000000 {
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compatible = "st,spear-timer";
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reg = <0xf0000000 0x400>;
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interrupts = <2>;
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};
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+11
-3
@@ -1905,6 +1905,16 @@ F: Documentation/filesystems/coda.txt
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F: fs/coda/
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F: include/linux/coda*.h
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COMMON CLK FRAMEWORK
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M: Mike Turquette <mturquette@ti.com>
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M: Mike Turquette <mturquette@linaro.org>
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L: linux-arm-kernel@lists.infradead.org (same as CLK API & CLKDEV)
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T: git git://git.linaro.org/people/mturquette/linux.git
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S: Maintained
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F: drivers/clk/clk.c
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F: drivers/clk/clk-*
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F: include/linux/clk-pr*
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COMMON INTERNET FILE SYSTEM (CIFS)
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M: Steve French <sfrench@samba.org>
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L: linux-cifs@vger.kernel.org
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@@ -6368,9 +6378,7 @@ L: spear-devel@list.st.com
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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W: http://www.st.com/spear
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S: Maintained
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F: arch/arm/mach-spear*/clock.c
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F: arch/arm/plat-spear/clock.c
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F: arch/arm/plat-spear/include/plat/clock.h
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F: drivers/clk/spear/
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SPI SUBSYSTEM
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M: Grant Likely <grant.likely@secretlab.ca>
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@@ -456,6 +456,7 @@ config ARCH_MXS
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select ARCH_REQUIRE_GPIOLIB
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select COMMON_CLK
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select HAVE_CLK_PREPARE
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select PINCTRL
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help
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@@ -947,6 +948,7 @@ config PLAT_SPEAR
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select ARM_AMBA
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select ARCH_REQUIRE_GPIOLIB
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select CLKDEV_LOOKUP
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select COMMON_CLK
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select CLKSRC_MMIO
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select GENERIC_CLOCKEVENTS
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select HAVE_CLK
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@@ -1101,6 +1103,7 @@ config PLAT_ORION
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bool
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select CLKSRC_MMIO
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select GENERIC_IRQ_CHIP
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select COMMON_CLK
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config PLAT_PXA
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bool
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@@ -87,6 +87,31 @@
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smi: flash@fc000000 {
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status = "okay";
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clock-rate=<50000000>;
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flash@f8000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xf8000000 0x800000>;
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st,smi-fast-mode;
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partition@0 {
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label = "xloader";
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reg = <0x0 0x10000>;
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};
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partition@10000 {
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label = "u-boot";
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reg = <0x10000 0x40000>;
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};
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partition@50000 {
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label = "linux";
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reg = <0x50000 0x2c0000>;
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};
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partition@310000 {
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label = "rootfs";
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reg = <0x310000 0x4f0000>;
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};
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};
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};
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spi0: spi@d0100000 {
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@@ -103,11 +103,27 @@
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clock-rate=<50000000>;
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flash@f8000000 {
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label = "m25p64";
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reg = <0xf8000000 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xf8000000 0x800000>;
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st,smi-fast-mode;
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partition@0 {
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label = "xloader";
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reg = <0x0 0x10000>;
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};
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partition@10000 {
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label = "u-boot";
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reg = <0x10000 0x40000>;
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};
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partition@50000 {
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label = "linux";
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reg = <0x50000 0x2c0000>;
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};
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partition@310000 {
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label = "rootfs";
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reg = <0x310000 0x4f0000>;
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};
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};
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};
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@@ -110,6 +110,31 @@
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smi: flash@fc000000 {
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status = "okay";
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clock-rate=<50000000>;
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flash@f8000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xf8000000 0x800000>;
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st,smi-fast-mode;
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partition@0 {
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label = "xloader";
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reg = <0x0 0x10000>;
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};
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partition@10000 {
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label = "u-boot";
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reg = <0x10000 0x40000>;
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};
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partition@50000 {
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label = "linux";
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reg = <0x50000 0x2c0000>;
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};
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partition@310000 {
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label = "rootfs";
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reg = <0x310000 0x4f0000>;
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};
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};
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};
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spi0: spi@d0100000 {
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@@ -139,6 +139,12 @@
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interrupts = <12>;
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status = "disabled";
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};
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timer@f0000000 {
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compatible = "st,spear-timer";
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reg = <0xf0000000 0x400>;
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interrupts = <2>;
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};
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};
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};
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};
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@@ -33,6 +33,35 @@
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status = "okay";
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};
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smi: flash@fc000000 {
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status = "okay";
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clock-rate=<50000000>;
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flash@f8000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xf8000000 0x800000>;
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st,smi-fast-mode;
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partition@0 {
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label = "xloader";
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reg = <0x0 0x10000>;
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};
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partition@10000 {
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label = "u-boot";
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reg = <0x10000 0x40000>;
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};
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partition@50000 {
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label = "linux";
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reg = <0x50000 0x2c0000>;
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};
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partition@310000 {
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label = "rootfs";
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reg = <0x310000 0x4f0000>;
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};
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};
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};
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apb {
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serial@d0000000 {
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status = "okay";
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@@ -177,6 +177,12 @@
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interrupts = <28>;
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status = "disabled";
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};
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timer@f0000000 {
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compatible = "st,spear-timer";
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reg = <0xf0000000 0x400>;
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interrupts = <16>;
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};
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};
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};
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};
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@@ -14,6 +14,9 @@ CONFIG_BINFMT_MISC=y
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CONFIG_NET=y
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_MTD=y
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CONFIG_MTD_OF_PARTS=y
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CONFIG_MTD_CHAR=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_FSMC=y
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CONFIG_BLK_DEV_RAM=y
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@@ -73,6 +76,7 @@ CONFIG_MSDOS_FS=m
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CONFIG_VFAT_FS=m
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CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
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CONFIG_TMPFS=y
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CONFIG_JFFS2_FS=y
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CONFIG_NLS_DEFAULT="utf8"
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ASCII=m
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@@ -8,11 +8,13 @@ CONFIG_MODVERSIONS=y
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_PLAT_SPEAR=y
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CONFIG_ARCH_SPEAR6XX=y
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CONFIG_BOARD_SPEAR600_DT=y
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CONFIG_BINFMT_MISC=y
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CONFIG_NET=y
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_MTD=y
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CONFIG_MTD_OF_PARTS=y
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CONFIG_MTD_CHAR=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_FSMC=y
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CONFIG_BLK_DEV_RAM=y
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@@ -64,6 +66,7 @@ CONFIG_MSDOS_FS=m
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CONFIG_VFAT_FS=m
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CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
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CONFIG_TMPFS=y
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CONFIG_JFFS2_FS=y
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CONFIG_NLS_DEFAULT="utf8"
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ASCII=m
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+25
-14
@@ -13,7 +13,7 @@
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/ata_platform.h>
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#include <linux/gpio.h>
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#include <asm/page.h>
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@@ -67,6 +67,19 @@ void __init dove_map_io(void)
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iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
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}
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/*****************************************************************************
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* CLK tree
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****************************************************************************/
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static struct clk *tclk;
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static void __init clk_init(void)
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{
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
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get_tclk());
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orion_clkdev_init(tclk);
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}
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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@@ -89,8 +102,7 @@ void __init dove_ehci1_init(void)
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void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
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{
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orion_ge00_init(eth_data,
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DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
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0, get_tclk());
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DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 0);
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}
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/*****************************************************************************
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@@ -116,7 +128,7 @@ void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
|
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void __init dove_uart0_init(void)
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{
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orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
|
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IRQ_DOVE_UART_0, get_tclk());
|
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IRQ_DOVE_UART_0, tclk);
|
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}
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|
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/*****************************************************************************
|
||||
@@ -125,7 +137,7 @@ void __init dove_uart0_init(void)
|
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void __init dove_uart1_init(void)
|
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{
|
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orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
|
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IRQ_DOVE_UART_1, get_tclk());
|
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IRQ_DOVE_UART_1, tclk);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
@@ -134,7 +146,7 @@ void __init dove_uart1_init(void)
|
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void __init dove_uart2_init(void)
|
||||
{
|
||||
orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
|
||||
IRQ_DOVE_UART_2, get_tclk());
|
||||
IRQ_DOVE_UART_2, tclk);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
@@ -143,7 +155,7 @@ void __init dove_uart2_init(void)
|
||||
void __init dove_uart3_init(void)
|
||||
{
|
||||
orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
|
||||
IRQ_DOVE_UART_3, get_tclk());
|
||||
IRQ_DOVE_UART_3, tclk);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
@@ -151,12 +163,12 @@ void __init dove_uart3_init(void)
|
||||
****************************************************************************/
|
||||
void __init dove_spi0_init(void)
|
||||
{
|
||||
orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
|
||||
orion_spi_init(DOVE_SPI0_PHYS_BASE);
|
||||
}
|
||||
|
||||
void __init dove_spi1_init(void)
|
||||
{
|
||||
orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
|
||||
orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
@@ -272,18 +284,17 @@ void __init dove_sdio1_init(void)
|
||||
|
||||
void __init dove_init(void)
|
||||
{
|
||||
int tclk;
|
||||
|
||||
tclk = get_tclk();
|
||||
|
||||
printk(KERN_INFO "Dove 88AP510 SoC, ");
|
||||
printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
|
||||
printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
|
||||
|
||||
#ifdef CONFIG_CACHE_TAUROS2
|
||||
tauros2_init();
|
||||
#endif
|
||||
dove_setup_cpu_mbus();
|
||||
|
||||
/* Setup root of clk tree */
|
||||
clk_init();
|
||||
|
||||
/* internal devices that every board has */
|
||||
dove_rtc_init();
|
||||
dove_xor0_init();
|
||||
|
||||
@@ -20,7 +20,6 @@
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/orion_spi.h>
|
||||
#include <linux/spi/flash.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
@@ -34,6 +34,7 @@ config ARCH_MX53
|
||||
config SOC_IMX1
|
||||
bool
|
||||
select ARCH_MX1
|
||||
select COMMON_CLK
|
||||
select CPU_ARM920T
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MXC_AVIC
|
||||
@@ -42,12 +43,14 @@ config SOC_IMX21
|
||||
bool
|
||||
select MACH_MX21
|
||||
select CPU_ARM926T
|
||||
select COMMON_CLK
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MXC_AVIC
|
||||
|
||||
config SOC_IMX25
|
||||
bool
|
||||
select ARCH_MX25
|
||||
select COMMON_CLK
|
||||
select CPU_ARM926T
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select MXC_AVIC
|
||||
@@ -56,6 +59,7 @@ config SOC_IMX27
|
||||
bool
|
||||
select MACH_MX27
|
||||
select CPU_ARM926T
|
||||
select COMMON_CLK
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MXC_AVIC
|
||||
|
||||
@@ -64,12 +68,14 @@ config SOC_IMX31
|
||||
select CPU_V6
|
||||
select IMX_HAVE_PLATFORM_MXC_RNGA
|
||||
select MXC_AVIC
|
||||
select COMMON_CLK
|
||||
select SMP_ON_UP if SMP
|
||||
|
||||
config SOC_IMX35
|
||||
bool
|
||||
select CPU_V6
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select COMMON_CLK
|
||||
select HAVE_EPIT
|
||||
select MXC_AVIC
|
||||
select SMP_ON_UP if SMP
|
||||
@@ -77,6 +83,7 @@ config SOC_IMX35
|
||||
config SOC_IMX5
|
||||
select CPU_V7
|
||||
select MXC_TZIC
|
||||
select COMMON_CLK
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_MX5
|
||||
@@ -815,6 +822,7 @@ config SOC_IMX6Q
|
||||
bool "i.MX6 Quad support"
|
||||
select ARM_CPU_SUSPEND if PM
|
||||
select ARM_GIC
|
||||
select COMMON_CLK
|
||||
select CPU_V7
|
||||
select HAVE_ARM_SCU
|
||||
select HAVE_IMX_GPC
|
||||
|
||||
@@ -1,15 +1,18 @@
|
||||
obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
|
||||
obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
|
||||
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
|
||||
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
|
||||
obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
|
||||
obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
|
||||
obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
|
||||
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-imx3.o
|
||||
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
|
||||
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
|
||||
|
||||
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
|
||||
clk-pfd.o clk-busy.o
|
||||
|
||||
# Support for CMOS sensor interface
|
||||
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
|
||||
@@ -70,7 +73,7 @@ obj-$(CONFIG_CPU_V7) += head-v7.o
|
||||
AFLAGS_head-v7.o :=-Wa,-march=armv7-a
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
|
||||
obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
|
||||
|
||||
ifeq ($(CONFIG_PM),y)
|
||||
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
|
||||
|
||||
@@ -0,0 +1,189 @@
|
||||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2012 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/err.h>
|
||||
#include "clk.h"
|
||||
|
||||
static int clk_busy_wait(void __iomem *reg, u8 shift)
|
||||
{
|
||||
unsigned long timeout = jiffies + msecs_to_jiffies(10);
|
||||
|
||||
while (readl_relaxed(reg) & (1 << shift))
|
||||
if (time_after(jiffies, timeout))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct clk_busy_divider {
|
||||
struct clk_divider div;
|
||||
const struct clk_ops *div_ops;
|
||||
void __iomem *reg;
|
||||
u8 shift;
|
||||
};
|
||||
|
||||
static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_divider *div = container_of(hw, struct clk_divider, hw);
|
||||
|
||||
return container_of(div, struct clk_busy_divider, div);
|
||||
}
|
||||
|
||||
static unsigned long clk_busy_divider_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_busy_divider *busy = to_clk_busy_divider(hw);
|
||||
|
||||
return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate);
|
||||
}
|
||||
|
||||
static long clk_busy_divider_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_busy_divider *busy = to_clk_busy_divider(hw);
|
||||
|
||||
return busy->div_ops->round_rate(&busy->div.hw, rate, prate);
|
||||
}
|
||||
|
||||
static int clk_busy_divider_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_busy_divider *busy = to_clk_busy_divider(hw);
|
||||
int ret;
|
||||
|
||||
ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate);
|
||||
if (!ret)
|
||||
ret = clk_busy_wait(busy->reg, busy->shift);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct clk_ops clk_busy_divider_ops = {
|
||||
.recalc_rate = clk_busy_divider_recalc_rate,
|
||||
.round_rate = clk_busy_divider_round_rate,
|
||||
.set_rate = clk_busy_divider_set_rate,
|
||||
};
|
||||
|
||||
struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
void __iomem *busy_reg, u8 busy_shift)
|
||||
{
|
||||
struct clk_busy_divider *busy;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
busy = kzalloc(sizeof(*busy), GFP_KERNEL);
|
||||
if (!busy)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
busy->reg = busy_reg;
|
||||
busy->shift = busy_shift;
|
||||
|
||||
busy->div.reg = reg;
|
||||
busy->div.shift = shift;
|
||||
busy->div.width = width;
|
||||
busy->div.lock = &imx_ccm_lock;
|
||||
busy->div_ops = &clk_divider_ops;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_busy_divider_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
busy->div.hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &busy->div.hw);
|
||||
if (!clk)
|
||||
kfree(busy);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk_busy_mux {
|
||||
struct clk_mux mux;
|
||||
const struct clk_ops *mux_ops;
|
||||
void __iomem *reg;
|
||||
u8 shift;
|
||||
};
|
||||
|
||||
static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux *mux = container_of(hw, struct clk_mux, hw);
|
||||
|
||||
return container_of(mux, struct clk_busy_mux, mux);
|
||||
}
|
||||
|
||||
static u8 clk_busy_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_busy_mux *busy = to_clk_busy_mux(hw);
|
||||
|
||||
return busy->mux_ops->get_parent(&busy->mux.hw);
|
||||
}
|
||||
|
||||
static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_busy_mux *busy = to_clk_busy_mux(hw);
|
||||
int ret;
|
||||
|
||||
ret = busy->mux_ops->set_parent(&busy->mux.hw, index);
|
||||
if (!ret)
|
||||
ret = clk_busy_wait(busy->reg, busy->shift);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct clk_ops clk_busy_mux_ops = {
|
||||
.get_parent = clk_busy_mux_get_parent,
|
||||
.set_parent = clk_busy_mux_set_parent,
|
||||
};
|
||||
|
||||
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
|
||||
u8 width, void __iomem *busy_reg, u8 busy_shift,
|
||||
const char **parent_names, int num_parents)
|
||||
{
|
||||
struct clk_busy_mux *busy;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
busy = kzalloc(sizeof(*busy), GFP_KERNEL);
|
||||
if (!busy)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
busy->reg = busy_reg;
|
||||
busy->shift = busy_shift;
|
||||
|
||||
busy->mux.reg = reg;
|
||||
busy->mux.shift = shift;
|
||||
busy->mux.width = width;
|
||||
busy->mux.lock = &imx_ccm_lock;
|
||||
busy->mux_ops = &clk_mux_ops;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_busy_mux_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
|
||||
busy->mux.hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &busy->mux.hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(busy);
|
||||
|
||||
return clk;
|
||||
}
|
||||
@@ -0,0 +1,118 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
|
||||
* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Gated clock implementation
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
/**
|
||||
* DOC: basic gatable clock which can gate and ungate it's ouput
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_(un)prepare only ensures parent is (un)prepared
|
||||
* enable - clk_enable and clk_disable are functional & control gating
|
||||
* rate - inherits rate from parent. No clk_set_rate support
|
||||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
static int clk_gate2_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate *gate = to_clk_gate(hw);
|
||||
u32 reg;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (gate->lock)
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
reg = readl(gate->reg);
|
||||
reg |= 3 << gate->bit_idx;
|
||||
writel(reg, gate->reg);
|
||||
|
||||
if (gate->lock)
|
||||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clk_gate2_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate *gate = to_clk_gate(hw);
|
||||
u32 reg;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (gate->lock)
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
reg = readl(gate->reg);
|
||||
reg &= ~(3 << gate->bit_idx);
|
||||
writel(reg, gate->reg);
|
||||
|
||||
if (gate->lock)
|
||||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
}
|
||||
|
||||
static int clk_gate2_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
u32 reg;
|
||||
struct clk_gate *gate = to_clk_gate(hw);
|
||||
|
||||
reg = readl(gate->reg);
|
||||
|
||||
if (((reg >> gate->bit_idx) & 3) == 3)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops clk_gate2_ops = {
|
||||
.enable = clk_gate2_enable,
|
||||
.disable = clk_gate2_disable,
|
||||
.is_enabled = clk_gate2_is_enabled,
|
||||
};
|
||||
|
||||
struct clk *clk_register_gate2(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate2_flags, spinlock_t *lock)
|
||||
{
|
||||
struct clk_gate *gate;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
/* struct clk_gate assignments */
|
||||
gate->reg = reg;
|
||||
gate->bit_idx = bit_idx;
|
||||
gate->flags = clk_gate2_flags;
|
||||
gate->lock = lock;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_gate2_ops;
|
||||
init.flags = flags;
|
||||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
|
||||
gate->hw.init = &init;
|
||||
|
||||
clk = clk_register(dev, &gate->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(clk);
|
||||
|
||||
return clk;
|
||||
}
|
||||
@@ -0,0 +1,115 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include "clk.h"
|
||||
|
||||
/* CCM register addresses */
|
||||
#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
|
||||
|
||||
#define CCM_CSCR IO_ADDR_CCM(0x0)
|
||||
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
|
||||
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
|
||||
#define CCM_PCDR IO_ADDR_CCM(0x20)
|
||||
|
||||
/* SCM register addresses */
|
||||
#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
|
||||
|
||||
#define SCM_GCCR IO_ADDR_SCM(0xc)
|
||||
|
||||
static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
|
||||
static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem",
|
||||
"fclk", };
|
||||
enum imx1_clks {
|
||||
dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, spll, mcu,
|
||||
fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate,
|
||||
mma_gate, usbd_gate, clk_max
|
||||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
|
||||
int __init mx1_clocks_init(unsigned long fref)
|
||||
{
|
||||
int i;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[clk32] = imx_clk_fixed("clk32", fref);
|
||||
clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
|
||||
clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
|
||||
clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
|
||||
clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
|
||||
ARRAY_SIZE(prem_sel_clks));
|
||||
clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
|
||||
clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
|
||||
clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
|
||||
clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1);
|
||||
clk[hclk] = imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4);
|
||||
clk[clk48m] = imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3);
|
||||
clk[per1] = imx_clk_divider("per1", "spll", CCM_PCDR, 0, 4);
|
||||
clk[per2] = imx_clk_divider("per2", "spll", CCM_PCDR, 4, 4);
|
||||
clk[per3] = imx_clk_divider("per3", "spll", CCM_PCDR, 16, 7);
|
||||
clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
|
||||
ARRAY_SIZE(clko_sel_clks));
|
||||
clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 4);
|
||||
clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
|
||||
clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
|
||||
clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("imx1 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_register_clkdev(clk[dma_gate], "ahb", "imx-dma");
|
||||
clk_register_clkdev(clk[csi_gate], NULL, "mx1-camera.0");
|
||||
clk_register_clkdev(clk[mma_gate], "mma", NULL);
|
||||
clk_register_clkdev(clk[usbd_gate], NULL, "imx_udc.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
|
||||
clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.2");
|
||||
clk_register_clkdev(clk[hclk], NULL, "imx-i2c.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
|
||||
clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
|
||||
clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
|
||||
clk_register_clkdev(clk[per2], NULL, "imx-mmc.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx-fb.0");
|
||||
clk_register_clkdev(clk[dummy], "ipg", "imx-fb.0");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "imx-fb.0");
|
||||
clk_register_clkdev(clk[hclk], "mshc", NULL);
|
||||
clk_register_clkdev(clk[per3], "ssi", NULL);
|
||||
clk_register_clkdev(clk[clk32], NULL, "mxc_rtc.0");
|
||||
clk_register_clkdev(clk[clko], "clko", NULL);
|
||||
|
||||
mxc_timer_init(NULL, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
|
||||
MX1_TIM1_INT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,186 @@
|
||||
/*
|
||||
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
|
||||
* Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
|
||||
|
||||
/* Register offsets */
|
||||
#define CCM_CSCR IO_ADDR_CCM(0x0)
|
||||
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
|
||||
#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
|
||||
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
|
||||
#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
|
||||
#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
|
||||
#define CCM_PCDR0 IO_ADDR_CCM(0x18)
|
||||
#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
|
||||
#define CCM_PCCR0 IO_ADDR_CCM(0x20)
|
||||
#define CCM_PCCR1 IO_ADDR_CCM(0x24)
|
||||
#define CCM_CCSR IO_ADDR_CCM(0x28)
|
||||
#define CCM_PMCTL IO_ADDR_CCM(0x2c)
|
||||
#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
|
||||
#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
|
||||
|
||||
static const char *mpll_sel_clks[] = { "fpm", "ckih", };
|
||||
static const char *spll_sel_clks[] = { "fpm", "ckih", };
|
||||
|
||||
enum imx21_clks {
|
||||
ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
|
||||
per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
|
||||
uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
|
||||
pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
|
||||
lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
|
||||
per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
|
||||
ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
|
||||
emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
|
||||
gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
|
||||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
|
||||
/*
|
||||
* must be called very early to get information about the
|
||||
* available clock rate when the timer framework starts
|
||||
*/
|
||||
int __init mx21_clocks_init(unsigned long lref, unsigned long href)
|
||||
{
|
||||
int i;
|
||||
|
||||
clk[ckil] = imx_clk_fixed("ckil", lref);
|
||||
clk[ckih] = imx_clk_fixed("ckih", href);
|
||||
clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
|
||||
clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
|
||||
ARRAY_SIZE(mpll_sel_clks));
|
||||
clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
|
||||
ARRAY_SIZE(spll_sel_clks));
|
||||
clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
||||
clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
|
||||
clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
|
||||
clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
|
||||
clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
|
||||
clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
|
||||
clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
|
||||
clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
|
||||
clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
|
||||
clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
|
||||
clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
|
||||
clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
|
||||
clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
|
||||
clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
|
||||
clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
|
||||
clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
|
||||
clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
|
||||
clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
|
||||
clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
|
||||
clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
|
||||
clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
|
||||
clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
|
||||
clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
|
||||
clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
|
||||
clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
|
||||
clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
|
||||
clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
|
||||
clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
|
||||
clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
|
||||
clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
|
||||
clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
|
||||
clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
|
||||
clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
|
||||
clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
|
||||
clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
|
||||
clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
|
||||
clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
|
||||
clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
|
||||
clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
|
||||
clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX21 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_register_clkdev(clk[per1], "per1", NULL);
|
||||
clk_register_clkdev(clk[per2], "per2", NULL);
|
||||
clk_register_clkdev(clk[per3], "per3", NULL);
|
||||
clk_register_clkdev(clk[per4], "per4", NULL);
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
|
||||
clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
|
||||
clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
|
||||
clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
|
||||
clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
|
||||
clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
|
||||
clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
|
||||
clk_register_clkdev(clk[per3], "per", "imx-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx-fb.0");
|
||||
clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
|
||||
clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
|
||||
clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand.0");
|
||||
clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx-dma");
|
||||
clk_register_clkdev(clk[dma_gate], "ipg", "imx-dma");
|
||||
clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[i2c_gate], NULL, "imx-i2c.0");
|
||||
clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
|
||||
clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
|
||||
clk_register_clkdev(clk[brom_gate], "brom", NULL);
|
||||
clk_register_clkdev(clk[emma_gate], "emma", NULL);
|
||||
clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
|
||||
clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
|
||||
clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
|
||||
clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
|
||||
clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
|
||||
clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
|
||||
clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
|
||||
|
||||
mxc_timer_init(NULL, MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
|
||||
MX21_INT_GPT1);
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,248 @@
|
||||
/*
|
||||
* Copyright (C) 2009 by Sascha Hauer, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/mx25.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
|
||||
|
||||
#define CCM_MPCTL 0x00
|
||||
#define CCM_UPCTL 0x04
|
||||
#define CCM_CCTL 0x08
|
||||
#define CCM_CGCR0 0x0C
|
||||
#define CCM_CGCR1 0x10
|
||||
#define CCM_CGCR2 0x14
|
||||
#define CCM_PCDR0 0x18
|
||||
#define CCM_PCDR1 0x1C
|
||||
#define CCM_PCDR2 0x20
|
||||
#define CCM_PCDR3 0x24
|
||||
#define CCM_RCSR 0x28
|
||||
#define CCM_CRDR 0x2C
|
||||
#define CCM_DCVR0 0x30
|
||||
#define CCM_DCVR1 0x34
|
||||
#define CCM_DCVR2 0x38
|
||||
#define CCM_DCVR3 0x3c
|
||||
#define CCM_LTR0 0x40
|
||||
#define CCM_LTR1 0x44
|
||||
#define CCM_LTR2 0x48
|
||||
#define CCM_LTR3 0x4c
|
||||
#define CCM_MCR 0x64
|
||||
|
||||
#define ccm(x) (CRM_BASE + (x))
|
||||
|
||||
static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
|
||||
static const char *per_sel_clks[] = { "ahb", "upll", };
|
||||
|
||||
enum mx25_clks {
|
||||
dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
|
||||
per0_sel, per1_sel, per2_sel, per3_sel, per4_sel, per5_sel, per6_sel,
|
||||
per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
|
||||
per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
|
||||
per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
|
||||
csi_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, gpt_ipg_per, i2c_ipg_per,
|
||||
lcdc_ipg_per, nfc_ipg_per, ssi1_ipg_per, ssi2_ipg_per, uart_ipg_per,
|
||||
csi_ahb, esdhc1_ahb, esdhc2_ahb, fec_ahb, lcdc_ahb, sdma_ahb,
|
||||
usbotg_ahb, can1_ipg, can2_ipg, csi_ipg, cspi1_ipg, cspi2_ipg,
|
||||
cspi3_ipg, dryice_ipg, esdhc1_ipg, esdhc2_ipg, fec_ipg, iim_ipg,
|
||||
kpp_ipg, lcdc_ipg, pwm1_ipg, pwm2_ipg, pwm3_ipg, pwm4_ipg, sdma_ipg,
|
||||
ssi1_ipg, ssi2_ipg, tsc_ipg, uart1_ipg, uart2_ipg, uart3_ipg,
|
||||
uart4_ipg, uart5_ipg, wdt_ipg, clk_max
|
||||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
|
||||
int __init mx25_clocks_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[osc] = imx_clk_fixed("osc", 24000000);
|
||||
clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
|
||||
clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
|
||||
clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
|
||||
clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
|
||||
clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2);
|
||||
clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2);
|
||||
clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6);
|
||||
clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
|
||||
clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per3_sel] = imx_clk_mux("per3_sel", ccm(CCM_MCR), 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per4_sel] = imx_clk_mux("per4_sel", ccm(CCM_MCR), 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per5_sel] = imx_clk_mux("per5_sel", ccm(CCM_MCR), 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per6_sel] = imx_clk_mux("per6_sel", ccm(CCM_MCR), 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per7_sel] = imx_clk_mux("per7_sel", ccm(CCM_MCR), 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per8_sel] = imx_clk_mux("per8_sel", ccm(CCM_MCR), 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per9_sel] = imx_clk_mux("per9_sel", ccm(CCM_MCR), 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per10_sel] = imx_clk_mux("per10_sel", ccm(CCM_MCR), 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per11_sel] = imx_clk_mux("per11_sel", ccm(CCM_MCR), 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per12_sel] = imx_clk_mux("per12_sel", ccm(CCM_MCR), 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
|
||||
clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);
|
||||
clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);
|
||||
clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
|
||||
clk[per3] = imx_clk_divider("per3", "per3_sel", ccm(CCM_PCDR0), 24, 6);
|
||||
clk[per4] = imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6);
|
||||
clk[per5] = imx_clk_divider("per5", "per5_sel", ccm(CCM_PCDR1), 8, 6);
|
||||
clk[per6] = imx_clk_divider("per6", "per6_sel", ccm(CCM_PCDR1), 16, 6);
|
||||
clk[per7] = imx_clk_divider("per7", "per7_sel", ccm(CCM_PCDR1), 24, 6);
|
||||
clk[per8] = imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6);
|
||||
clk[per9] = imx_clk_divider("per9", "per9_sel", ccm(CCM_PCDR2), 8, 6);
|
||||
clk[per10] = imx_clk_divider("per10", "per10_sel", ccm(CCM_PCDR2), 16, 6);
|
||||
clk[per11] = imx_clk_divider("per11", "per11_sel", ccm(CCM_PCDR2), 24, 6);
|
||||
clk[per12] = imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6);
|
||||
clk[per13] = imx_clk_divider("per13", "per13_sel", ccm(CCM_PCDR3), 8, 6);
|
||||
clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
|
||||
clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
|
||||
clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
|
||||
clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3);
|
||||
clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4);
|
||||
clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5);
|
||||
clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6);
|
||||
clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per8", ccm(CCM_CGCR0), 7);
|
||||
clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "ipg_per", ccm(CCM_CGCR0), 8);
|
||||
clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
|
||||
clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
|
||||
clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
|
||||
clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
|
||||
clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
|
||||
clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
|
||||
clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
|
||||
clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
|
||||
clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
|
||||
clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
|
||||
clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2);
|
||||
clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3);
|
||||
clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4);
|
||||
clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1), 5);
|
||||
clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6);
|
||||
clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7);
|
||||
clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8);
|
||||
clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
|
||||
clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
|
||||
clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
|
||||
clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
|
||||
clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
|
||||
clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
|
||||
clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
|
||||
clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0);
|
||||
clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1);
|
||||
clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2);
|
||||
clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6);
|
||||
clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
|
||||
clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
|
||||
clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
|
||||
clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14);
|
||||
clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15);
|
||||
clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
|
||||
clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
|
||||
clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
|
||||
clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX25 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
/* i.mx25 has the i.mx21 type uart */
|
||||
clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
|
||||
clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc");
|
||||
clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
|
||||
clk_register_clkdev(clk[nfc_ipg_per], NULL, "mxc_nand.0");
|
||||
/* i.mx25 has the i.mx35 type cspi */
|
||||
clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
|
||||
clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
|
||||
clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
|
||||
clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
|
||||
clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
|
||||
clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
|
||||
clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
|
||||
clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
|
||||
clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
|
||||
clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
|
||||
clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
|
||||
clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
|
||||
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.0");
|
||||
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.1");
|
||||
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.2");
|
||||
clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
|
||||
clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
|
||||
clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
|
||||
clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
|
||||
clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
|
||||
clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
|
||||
clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
|
||||
clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
|
||||
clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
|
||||
clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
|
||||
clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
|
||||
clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
|
||||
clk_register_clkdev(clk[csi_ipg_per], "per", "mx2-camera.0");
|
||||
clk_register_clkdev(clk[csi_ipg], "ipg", "mx2-camera.0");
|
||||
clk_register_clkdev(clk[csi_ahb], "ahb", "mx2-camera.0");
|
||||
clk_register_clkdev(clk[dummy], "audmux", NULL);
|
||||
clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
|
||||
clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
|
||||
/* i.mx25 has the i.mx35 type sdma */
|
||||
clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
|
||||
clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
|
||||
clk_register_clkdev(clk[iim_ipg], "iim", NULL);
|
||||
|
||||
mxc_timer_init(NULL, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
|
||||
return 0;
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user