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Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc-merge

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This commit is contained in:
Linus Torvalds
2005-11-18 07:22:51 -08:00
parent 811803c557 f365cfd0d8
commit 2656c076e3
35 changed files with 670 additions and 6817 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/powerpc/Kconfig
-13
View File
@@ -598,19 +598,6 @@ config ARCH_MEMORY_PROBE
def_bool y
depends on MEMORY_HOTPLUG
# Some NUMA nodes have memory ranges that span
# other nodes. Even though a pfn is valid and
# between a node's start and end pfns, it may not
# reside on that node.
#
# This is a relatively temporary hack that should
# be able to go away when sparsemem is fully in
# place
config NODES_SPAN_OTHER_NODES
def_bool y
depends on NEED_MULTIPLE_NODES
config PPC_64K_PAGES
bool "64k page size"
depends on PPC64
arch/powerpc/Makefile
+4 -5
View File
@@ -33,6 +33,8 @@ endif
export CROSS32CC CROSS32AS CROSS32LD CROSS32OBJCOPY
KBUILD_DEFCONFIG := $(shell uname -m)_defconfig
ifeq ($(CONFIG_PPC64),y)
OLDARCH := ppc64
SZ := 64
@@ -111,9 +113,6 @@ cpu-as-$(CONFIG_E200) += -Wa,-me200
AFLAGS += $(cpu-as-y)
CFLAGS += $(cpu-as-y)
# Default to the common case.
KBUILD_DEFCONFIG := common_defconfig
head-y := arch/powerpc/kernel/head_32.o
head-$(CONFIG_PPC64) := arch/powerpc/kernel/head_64.o
head-$(CONFIG_8xx) := arch/powerpc/kernel/head_8xx.o
@@ -125,11 +124,11 @@ head-$(CONFIG_PPC64) += arch/powerpc/kernel/entry_64.o
head-$(CONFIG_PPC_FPU) += arch/powerpc/kernel/fpu.o
core-y += arch/powerpc/kernel/ \
arch/$(OLDARCH)/kernel/ \
arch/powerpc/mm/ \
arch/powerpc/lib/ \
arch/powerpc/sysdev/ \
arch/powerpc/platforms/
core-$(CONFIG_PPC32) += arch/ppc/kernel/
core-$(CONFIG_MATH_EMULATION) += arch/ppc/math-emu/
core-$(CONFIG_XMON) += arch/powerpc/xmon/
core-$(CONFIG_APUS) += arch/ppc/amiga/
@@ -165,7 +164,7 @@ define archhelp
@echo ' (your) ~/bin/installkernel or'
@echo ' (distribution) /sbin/installkernel or'
@echo ' install to $$(INSTALL_PATH) and run lilo'
@echo ' *_defconfig - Select default config from arch/$(ARCH)/ppc/configs'
@echo ' *_defconfig - Select default config from arch/$(ARCH)/configs'
endef
archclean:
arch/powerpc/boot/crt0.S
+11 -12
View File
@@ -14,43 +14,42 @@
.text
.globl _zimage_start
_zimage_start:
bl reloc_offset
bl 1f
reloc_offset:
1:
mflr r0
lis r9,reloc_offset@ha
addi r9,r9,reloc_offset@l
lis r9,1b@ha
addi r9,r9,1b@l
subf. r0,r9,r0
beq clear_caches
beq 3f
reloc_got2:
lis r9,__got2_start@ha
addi r9,r9,__got2_start@l
lis r8,__got2_end@ha
addi r8,r8,__got2_end@l
subf. r8,r9,r8
beq clear_caches
beq 3f
srwi. r8,r8,2
mtctr r8
add r9,r0,r9
reloc_got2_loop:
2:
lwz r8,0(r9)
add r8,r8,r0
stw r8,0(r9)
addi r9,r9,4
bdnz reloc_got2_loop
bdnz 2b
clear_caches:
3:
lis r9,_start@h
add r9,r0,r9
lis r8,_etext@ha
addi r8,r8,_etext@l
add r8,r0,r8
1: dcbf r0,r9
4: dcbf r0,r9
icbi r0,r9
addi r9,r9,0x20
cmplwi 0,r9,8
blt 1b
blt 4b
sync
isync
arch/ppc64/defconfig → arch/powerpc/configs/ppc64_defconfig
+243 -105
View File
File diff suppressed because it is too large Load Diff
arch/powerpc/configs/pseries_defconfig
-1
View File
@@ -165,7 +165,6 @@ CONFIG_SPARSEMEM_EXTREME=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
CONFIG_NODES_SPAN_OTHER_NODES=y
# CONFIG_PPC_64K_PAGES is not set
CONFIG_SCHED_SMT=y
CONFIG_PROC_DEVICETREE=y
arch/powerpc/kernel/Makefile
+5 -2
View File
@@ -12,12 +12,12 @@ CFLAGS_btext.o += -fPIC
endif
obj-y := semaphore.o cputable.o ptrace.o syscalls.o \
irq.o signal_32.o pmc.o vdso.o
irq.o align.o signal_32.o pmc.o vdso.o
obj-y += vdso32/
obj-$(CONFIG_PPC64) += setup_64.o binfmt_elf32.o sys_ppc32.o \
signal_64.o ptrace32.o systbl.o \
paca.o ioctl32.o cpu_setup_power4.o \
firmware.o sysfs.o udbg.o
firmware.o sysfs.o udbg.o idle_64.o
obj-$(CONFIG_PPC64) += vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o
obj-$(CONFIG_POWER4) += idle_power4.o
@@ -35,6 +35,7 @@ obj-$(CONFIG_PPC_PSERIES) += udbg_16550.o
obj-$(CONFIG_PPC_MAPLE) += udbg_16550.o
udbgscc-$(CONFIG_PPC64) := udbg_scc.o
obj-$(CONFIG_PPC_PMAC) += $(udbgscc-y)
obj64-$(CONFIG_PPC_MULTIPLATFORM) += nvram_64.o
ifeq ($(CONFIG_PPC_MERGE),y)
@@ -78,5 +79,7 @@ smpobj-$(CONFIG_SMP) += smp.o
endif
obj-$(CONFIG_PPC64) += $(obj64-y)
extra-$(CONFIG_PPC_FPU) += fpu.o
extra-$(CONFIG_PPC64) += entry_64.o
arch/ppc64/kernel/align.c → arch/powerpc/kernel/align.c
+265 -131
View File
File diff suppressed because it is too large Load Diff
arch/ppc64/kernel/idle.c → arch/powerpc/kernel/idle_64.c
View File
arch/powerpc/kernel/misc_32.S
-8
View File
@@ -27,14 +27,6 @@
.text
.align 5
_GLOBAL(__delay)
cmpwi 0,r3,0
mtctr r3
beqlr
1: bdnz 1b
blr
/*
* This returns the high 64 bits of the product of two 64-bit numbers.
*/
arch/ppc64/kernel/nvram.c → arch/powerpc/kernel/nvram_64.c
View File
arch/powerpc/kernel/rtas-rtc.c
+3 -3
View File
@@ -15,7 +15,7 @@ unsigned long __init rtas_get_boot_time(void)
{
int ret[8];
int error, wait_time;
unsigned long max_wait_tb;
u64 max_wait_tb;
max_wait_tb = get_tb() + tb_ticks_per_usec * 1000 * MAX_RTC_WAIT;
do {
@@ -45,7 +45,7 @@ void rtas_get_rtc_time(struct rtc_time *rtc_tm)
{
int ret[8];
int error, wait_time;
unsigned long max_wait_tb;
u64 max_wait_tb;
max_wait_tb = get_tb() + tb_ticks_per_usec * 1000 * MAX_RTC_WAIT;
do {
@@ -80,7 +80,7 @@ void rtas_get_rtc_time(struct rtc_time *rtc_tm)
int rtas_set_rtc_time(struct rtc_time *tm)
{
int error, wait_time;
unsigned long max_wait_tb;
u64 max_wait_tb;
max_wait_tb = get_tb() + tb_ticks_per_usec * 1000 * MAX_RTC_WAIT;
do {
arch/powerpc/kernel/time.c
+28
View File
@@ -130,6 +130,34 @@ unsigned long tb_last_stamp;
*/
DEFINE_PER_CPU(unsigned long, last_jiffy);
void __delay(unsigned long loops)
{
unsigned long start;
int diff;
if (__USE_RTC()) {
start = get_rtcl();
do {
/* the RTCL register wraps at 1000000000 */
diff = get_rtcl() - start;
if (diff < 0)
diff += 1000000000;
} while (diff < loops);
} else {
start = get_tbl();
while (get_tbl() - start < loops)
HMT_low();
HMT_medium();
}
}
EXPORT_SYMBOL(__delay);
void udelay(unsigned long usecs)
{
__delay(tb_ticks_per_usec * usecs);
}
EXPORT_SYMBOL(udelay);
static __inline__ void timer_check_rtc(void)
{
/*
arch/powerpc/platforms/chrp/setup.c
+10 -1
View File
@@ -257,6 +257,13 @@ void __init chrp_setup_arch(void)
if (rtas_token("display-character") >= 0)
ppc_md.progress = rtas_progress;
/* use RTAS time-of-day routines if available */
if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
ppc_md.get_boot_time = rtas_get_boot_time;
ppc_md.get_rtc_time = rtas_get_rtc_time;
ppc_md.set_rtc_time = rtas_set_rtc_time;
}
#ifdef CONFIG_BOOTX_TEXT
if (ppc_md.progress == NULL && boot_text_mapped)
ppc_md.progress = btext_progress;
@@ -505,9 +512,11 @@ void __init chrp_init(void)
ppc_md.halt = rtas_halt;
ppc_md.time_init = chrp_time_init;
ppc_md.calibrate_decr = chrp_calibrate_decr;
/* this may get overridden with rtas routines later... */
ppc_md.set_rtc_time = chrp_set_rtc_time;
ppc_md.get_rtc_time = chrp_get_rtc_time;
ppc_md.calibrate_decr = chrp_calibrate_decr;
#ifdef CONFIG_SMP
smp_ops = &chrp_smp_ops;
arch/powerpc/platforms/chrp/smp.c
+1
View File
@@ -34,6 +34,7 @@
#include <asm/machdep.h>
#include <asm/smp.h>
#include <asm/mpic.h>
#include <asm/rtas.h>
static void __devinit smp_chrp_kick_cpu(int nr)
{
arch/powerpc/platforms/chrp/time.c
+1 -2
View File
@@ -87,7 +87,6 @@ int chrp_set_rtc_time(struct rtc_time *tmarg)
chrp_cmos_clock_write((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
tm.tm_year -= 1900;
if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
BIN_TO_BCD(tm.tm_sec);
BIN_TO_BCD(tm.tm_min);
@@ -156,7 +155,7 @@ void chrp_get_rtc_time(struct rtc_time *tm)
BCD_TO_BIN(mon);
BCD_TO_BIN(year);
}
if ((year += 1900) < 1970)
if (year < 70)
year += 100;
tm->tm_sec = sec;
tm->tm_min = min;
arch/powerpc/platforms/maple/time.c
+10 -1
View File
@@ -158,6 +158,11 @@ int maple_set_rtc_time(struct rtc_time *tm)
return 0;
}
static struct resource rtc_iores = {
.name = "rtc",
.flags = IORESOURCE_BUSY,
};
unsigned long __init maple_get_boot_time(void)
{
struct rtc_time tm;
@@ -172,7 +177,11 @@ unsigned long __init maple_get_boot_time(void)
printk(KERN_INFO "Maple: No device node for RTC, assuming "
"legacy address (0x%x)\n", maple_rtc_addr);
}
rtc_iores.start = maple_rtc_addr;
rtc_iores.end = maple_rtc_addr + 7;
request_resource(&ioport_resource, &rtc_iores);
maple_get_rtc_time(&tm);
return mktime(tm.tm_year+1900, tm.tm_mon+1, tm.tm_mday,
tm.tm_hour, tm.tm_min, tm.tm_sec);
arch/powerpc/platforms/pseries/eeh.c
+2 -1
View File
@@ -86,7 +86,8 @@ static int ibm_read_slot_reset_state;
static int ibm_read_slot_reset_state2;
static int ibm_slot_error_detail;
static int eeh_subsystem_enabled;
int eeh_subsystem_enabled;
EXPORT_SYMBOL(eeh_subsystem_enabled);
/* Lock to avoid races due to multiple reports of an error */
static DEFINE_SPINLOCK(confirm_error_lock);
arch/powerpc/platforms/pseries/setup.c
+2 -2
View File
@@ -504,7 +504,7 @@ static void pseries_dedicated_idle(void)
lpaca->lppaca.idle = 1;
if (!need_resched()) {
start_snooze = __get_tb() +
start_snooze = get_tb() +
*smt_snooze_delay * tb_ticks_per_usec;
while (!need_resched() && !cpu_is_offline(cpu)) {
@@ -518,7 +518,7 @@ static void pseries_dedicated_idle(void)
HMT_very_low();
if (*smt_snooze_delay != 0 &&
__get_tb() > start_snooze) {
get_tb() > start_snooze) {
HMT_medium();
dedicated_idle_sleep(cpu);
}
arch/ppc/kernel/Makefile
+2 -2
View File
@@ -13,7 +13,7 @@ extra-$(CONFIG_POWER4) += idle_power4.o
extra-y += vmlinux.lds
obj-y := entry.o traps.o idle.o time.o misc.o \
process.o align.o \
process.o \
setup.o \
ppc_htab.o
obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o
@@ -38,7 +38,7 @@ endif
# These are here while we do the architecture merge
else
obj-y := idle.o align.o
obj-y := idle.o
obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o
obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o
obj-$(CONFIG_MODULES) += module.o
arch/ppc/kernel/align.c
-410
View File
@@ -1,410 +0,0 @@
/*
* align.c - handle alignment exceptions for the Power PC.
*
* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
* Copyright (c) 1998-1999 TiVo, Inc.
* PowerPC 403GCX modifications.
* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
* PowerPC 403GCX/405GP modifications.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/cache.h>
struct aligninfo {
unsigned char len;
unsigned char flags;
};
#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
#define OPCD(inst) (((inst) & 0xFC000000) >> 26)
#define RS(inst) (((inst) & 0x03E00000) >> 21)
#define RA(inst) (((inst) & 0x001F0000) >> 16)
#define IS_XFORM(code) ((code) == 31)
#endif
#define INVALID { 0, 0 }
#define LD 1 /* load */
#define ST 2 /* store */
#define SE 4 /* sign-extend value */
#define F 8 /* to/from fp regs */
#define U 0x10 /* update index register */
#define M 0x20 /* multiple load/store */
#define S 0x40 /* single-precision fp, or byte-swap value */
#define SX 0x40 /* byte count in XER */
#define HARD 0x80 /* string, stwcx. */
#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
/*
* The PowerPC stores certain bits of the instruction that caused the
* alignment exception in the DSISR register. This array maps those
* bits to information about the operand length and what the
* instruction would do.
*/
static struct aligninfo aligninfo[128] = {
{ 4, LD }, /* 00 0 0000: lwz / lwarx */
INVALID, /* 00 0 0001 */
{ 4, ST }, /* 00 0 0010: stw */
INVALID, /* 00 0 0011 */
{ 2, LD }, /* 00 0 0100: lhz */
{ 2, LD+SE }, /* 00 0 0101: lha */
{ 2, ST }, /* 00 0 0110: sth */
{ 4, LD+M }, /* 00 0 0111: lmw */
{ 4, LD+F+S }, /* 00 0 1000: lfs */
{ 8, LD+F }, /* 00 0 1001: lfd */
{ 4, ST+F+S }, /* 00 0 1010: stfs */
{ 8, ST+F }, /* 00 0 1011: stfd */
INVALID, /* 00 0 1100 */
INVALID, /* 00 0 1101: ld/ldu/lwa */
INVALID, /* 00 0 1110 */
INVALID, /* 00 0 1111: std/stdu */
{ 4, LD+U }, /* 00 1 0000: lwzu */
INVALID, /* 00 1 0001 */
{ 4, ST+U }, /* 00 1 0010: stwu */
INVALID, /* 00 1 0011 */
{ 2, LD+U }, /* 00 1 0100: lhzu */
{ 2, LD+SE+U }, /* 00 1 0101: lhau */
{ 2, ST+U }, /* 00 1 0110: sthu */
{ 4, ST+M }, /* 00 1 0111: stmw */
{ 4, LD+F+S+U }, /* 00 1 1000: lfsu */
{ 8, LD+F+U }, /* 00 1 1001: lfdu */
{ 4, ST+F+S+U }, /* 00 1 1010: stfsu */
{ 8, ST+F+U }, /* 00 1 1011: stfdu */
INVALID, /* 00 1 1100 */
INVALID, /* 00 1 1101 */
INVALID, /* 00 1 1110 */
INVALID, /* 00 1 1111 */
INVALID, /* 01 0 0000: ldx */
INVALID, /* 01 0 0001 */
INVALID, /* 01 0 0010: stdx */
INVALID, /* 01 0 0011 */
INVALID, /* 01 0 0100 */
INVALID, /* 01 0 0101: lwax */
INVALID, /* 01 0 0110 */
INVALID, /* 01 0 0111 */
{ 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
{ 4, LD+M+HARD }, /* 01 0 1001: lswi */
{ 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
{ 4, ST+M+HARD }, /* 01 0 1011: stswi */
INVALID, /* 01 0 1100 */
INVALID, /* 01 0 1101 */
INVALID, /* 01 0 1110 */
INVALID, /* 01 0 1111 */
INVALID, /* 01 1 0000: ldux */
INVALID, /* 01 1 0001 */
INVALID, /* 01 1 0010: stdux */
INVALID, /* 01 1 0011 */
INVALID, /* 01 1 0100 */
INVALID, /* 01 1 0101: lwaux */
INVALID, /* 01 1 0110 */
INVALID, /* 01 1 0111 */
INVALID, /* 01 1 1000 */
INVALID, /* 01 1 1001 */
INVALID, /* 01 1 1010 */
INVALID, /* 01 1 1011 */
INVALID, /* 01 1 1100 */
INVALID, /* 01 1 1101 */
INVALID, /* 01 1 1110 */
INVALID, /* 01 1 1111 */
INVALID, /* 10 0 0000 */
INVALID, /* 10 0 0001 */
{ 0, ST+HARD }, /* 10 0 0010: stwcx. */
INVALID, /* 10 0 0011 */
INVALID, /* 10 0 0100 */
INVALID, /* 10 0 0101 */
INVALID, /* 10 0 0110 */
INVALID, /* 10 0 0111 */
{ 4, LD+S }, /* 10 0 1000: lwbrx */
INVALID, /* 10 0 1001 */
{ 4, ST+S }, /* 10 0 1010: stwbrx */
INVALID, /* 10 0 1011 */
{ 2, LD+S }, /* 10 0 1100: lhbrx */
INVALID, /* 10 0 1101 */
{ 2, ST+S }, /* 10 0 1110: sthbrx */
INVALID, /* 10 0 1111 */
INVALID, /* 10 1 0000 */
INVALID, /* 10 1 0001 */
INVALID, /* 10 1 0010 */
INVALID, /* 10 1 0011 */
INVALID, /* 10 1 0100 */
INVALID, /* 10 1 0101 */
INVALID, /* 10 1 0110 */
INVALID, /* 10 1 0111 */
INVALID, /* 10 1 1000 */
INVALID, /* 10 1 1001 */
INVALID, /* 10 1 1010 */
INVALID, /* 10 1 1011 */
INVALID, /* 10 1 1100 */
INVALID, /* 10 1 1101 */
INVALID, /* 10 1 1110 */
{ 0, ST+HARD }, /* 10 1 1111: dcbz */
{ 4, LD }, /* 11 0 0000: lwzx */
INVALID, /* 11 0 0001 */
{ 4, ST }, /* 11 0 0010: stwx */
INVALID, /* 11 0 0011 */
{ 2, LD }, /* 11 0 0100: lhzx */
{ 2, LD+SE }, /* 11 0 0101: lhax */
{ 2, ST }, /* 11 0 0110: sthx */
INVALID, /* 11 0 0111 */
{ 4, LD+F+S }, /* 11 0 1000: lfsx */
{ 8, LD+F }, /* 11 0 1001: lfdx */
{ 4, ST+F+S }, /* 11 0 1010: stfsx */
{ 8, ST+F }, /* 11 0 1011: stfdx */
INVALID, /* 11 0 1100 */
INVALID, /* 11 0 1101: lmd */
INVALID, /* 11 0 1110 */
INVALID, /* 11 0 1111: stmd */
{ 4, LD+U }, /* 11 1 0000: lwzux */
INVALID, /* 11 1 0001 */
{ 4, ST+U }, /* 11 1 0010: stwux */
INVALID, /* 11 1 0011 */
{ 2, LD+U }, /* 11 1 0100: lhzux */
{ 2, LD+SE+U }, /* 11 1 0101: lhaux */
{ 2, ST+U }, /* 11 1 0110: sthux */
INVALID, /* 11 1 0111 */
{ 4, LD+F+S+U }, /* 11 1 1000: lfsux */
{ 8, LD+F+U }, /* 11 1 1001: lfdux */
{ 4, ST+F+S+U }, /* 11 1 1010: stfsux */
{ 8, ST+F+U }, /* 11 1 1011: stfdux */
INVALID, /* 11 1 1100 */
INVALID, /* 11 1 1101 */
INVALID, /* 11 1 1110 */
INVALID, /* 11 1 1111 */
};
#define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
int
fix_alignment(struct pt_regs *regs)
{
int instr, nb, flags;
#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
int opcode, f1, f2, f3;
#endif
int i, t;
int reg, areg;
int offset, nb0;
unsigned char __user *addr;
unsigned char *rptr;
union {
long l;
float f;
double d;
unsigned char v[8];
} data;
CHECK_FULL_REGS(regs);
#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
/* The 4xx-family & Book-E processors have no DSISR register,
* so we emulate it.
* The POWER4 has a DSISR register but doesn't set it on
* an alignment fault. -- paulus
*/
if (__get_user(instr, (unsigned int __user *) regs->nip))
return 0;
opcode = OPCD(instr);
reg = RS(instr);
areg = RA(instr);
if (!IS_XFORM(opcode)) {
f1 = 0;
f2 = (instr & 0x04000000) >> 26;
f3 = (instr & 0x78000000) >> 27;
} else {
f1 = (instr & 0x00000006) >> 1;
f2 = (instr & 0x00000040) >> 6;
f3 = (instr & 0x00000780) >> 7;
}
instr = ((f1 << 5) | (f2 << 4) | f3);
#else
reg = (regs->dsisr >> 5) & 0x1f; /* source/dest register */
areg = regs->dsisr & 0x1f; /* register to update */
instr = (regs->dsisr >> 10) & 0x7f;
#endif
nb = aligninfo[instr].len;
if (nb == 0) {
long __user *p;
int i;
if (instr != DCBZ)
return 0; /* too hard or invalid instruction */
/*
* The dcbz (data cache block zero) instruction
* gives an alignment fault if used on non-cacheable
* memory. We handle the fault mainly for the
* case when we are running with the cache disabled
* for debugging.
*/
p = (long __user *) (regs->dar & -L1_CACHE_BYTES);
if (user_mode(regs)
&& !access_ok(VERIFY_WRITE, p, L1_CACHE_BYTES))
return -EFAULT;
for (i = 0; i < L1_CACHE_BYTES / sizeof(long); ++i)
if (__put_user(0, p+i))
return -EFAULT;
return 1;
}
flags = aligninfo[instr].flags;
if ((flags & (LD|ST)) == 0)
return 0;
/* For the 4xx-family & Book-E processors, the 'dar' field of the
* pt_regs structure is overloaded and is really from the DEAR.
*/
addr = (unsigned char __user *)regs->dar;
if (flags & M) {
/* lmw, stmw, lswi/x, stswi/x */
nb0 = 0;
if (flags & HARD) {
if (flags & SX) {
nb = regs->xer & 127;
if (nb == 0)
return 1;
} else {
if (__get_user(instr,
(unsigned int __user *)regs->nip))
return 0;
nb = (instr >> 11) & 0x1f;
if (nb == 0)
nb = 32;
}
if (nb + reg * 4 > 128) {
nb0 = nb + reg * 4 - 128;
nb = 128 - reg * 4;
}
} else {
/* lwm, stmw */
nb = (32 - reg) * 4;
}
if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
return -EFAULT; /* bad address */
rptr = (unsigned char *) &regs->gpr[reg];
if (flags & LD) {
for (i = 0; i < nb; ++i)
if (__get_user(rptr[i], addr+i))
return -EFAULT;
if (nb0 > 0) {
rptr = (unsigned char *) &regs->gpr[0];
addr += nb;
for (i = 0; i < nb0; ++i)
if (__get_user(rptr[i], addr+i))
return -EFAULT;
}
for (; (i & 3) != 0; ++i)
rptr[i] = 0;
} else {
for (i = 0; i < nb; ++i)
if (__put_user(rptr[i], addr+i))
return -EFAULT;
if (nb0 > 0) {
rptr = (unsigned char *) &regs->gpr[0];
addr += nb;
for (i = 0; i < nb0; ++i)
if (__put_user(rptr[i], addr+i))
return -EFAULT;
}
}
return 1;
}
offset = 0;
if (nb < 4) {
/* read/write the least significant bits */
data.l = 0;
offset = 4 - nb;
}
/* Verify the address of the operand */
if (user_mode(regs)) {
if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb))
return -EFAULT; /* bad address */
}
if (flags & F) {
preempt_disable();
if (regs->msr & MSR_FP)
giveup_fpu(current);
preempt_enable();
}
/* If we read the operand, copy it in, else get register values */
if (flags & LD) {
for (i = 0; i < nb; ++i)
if (__get_user(data.v[offset+i], addr+i))
return -EFAULT;
} else if (flags & F) {
data.d = current->thread.fpr[reg];
} else {
data.l = regs->gpr[reg];
}
switch (flags & ~U) {
case LD+SE: /* sign extend */
if (data.v[2] >= 0x80)
data.v[0] = data.v[1] = -1;
break;
case LD+S: /* byte-swap */
case ST+S:
if (nb == 2) {
SWAP(data.v[2], data.v[3]);
} else {
SWAP(data.v[0], data.v[3]);
SWAP(data.v[1], data.v[2]);
}
break;
/* Single-precision FP load and store require conversions... */
case LD+F+S:
#ifdef CONFIG_PPC_FPU
preempt_disable();
enable_kernel_fp();
cvt_fd(&data.f, &data.d, &current->thread);
preempt_enable();
#else
return 0;
#endif
break;
case ST+F+S:
#ifdef CONFIG_PPC_FPU
preempt_disable();
enable_kernel_fp();
cvt_df(&data.d, &data.f, &current->thread);
preempt_enable();
#else
return 0;
#endif
break;
}
if (flags & ST) {
for (i = 0; i < nb; ++i)
if (__put_user(data.v[offset+i], addr+i))
return -EFAULT;
} else if (flags & F) {
current->thread.fpr[reg] = data.d;
} else {
regs->gpr[reg] = data.l;
}
if (flags & U)
regs->gpr[areg] = regs->dar;
return 1;
}

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