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Merge branches 'alignment', 'fixes', 'l2c' (early part) and 'misc' into for-next
This commit is contained in:
Russell King
@@ -41,16 +41,9 @@ fffe8000 fffeffff DTCM mapping area for platforms with
|
||||
fffe0000 fffe7fff ITCM mapping area for platforms with
|
||||
ITCM mounted inside the CPU.
|
||||
|
||||
fff00000 fffdffff Fixmap mapping region. Addresses provided
|
||||
ffc00000 ffdfffff Fixmap mapping region. Addresses provided
|
||||
by fix_to_virt() will be located here.
|
||||
|
||||
ffc00000 ffefffff DMA memory mapping region. Memory returned
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||||
by the dma_alloc_xxx functions will be
|
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dynamically mapped here.
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||||
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ff000000 ffbfffff Reserved for future expansion of DMA
|
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mapping region.
|
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|
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fee00000 feffffff Mapping of PCI I/O space. This is a static
|
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mapping within the vmalloc space.
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@@ -8,6 +8,7 @@ Required properties:
|
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|
||||
- compatible : should be one of
|
||||
"arm,armv8-pmuv3"
|
||||
"arm,cortex-a17-pmu"
|
||||
"arm,cortex-a15-pmu"
|
||||
"arm,cortex-a12-pmu"
|
||||
"arm,cortex-a9-pmu"
|
||||
|
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+6
-60
@@ -165,12 +165,9 @@ config TRACE_IRQFLAGS_SUPPORT
|
||||
bool
|
||||
default y
|
||||
|
||||
config RWSEM_GENERIC_SPINLOCK
|
||||
bool
|
||||
default y
|
||||
|
||||
config RWSEM_XCHGADD_ALGORITHM
|
||||
bool
|
||||
default y
|
||||
|
||||
config ARCH_HAS_ILOG2_U32
|
||||
bool
|
||||
@@ -1105,11 +1102,6 @@ source "arch/arm/firmware/Kconfig"
|
||||
|
||||
source arch/arm/mm/Kconfig
|
||||
|
||||
config ARM_NR_BANKS
|
||||
int
|
||||
default 16 if ARCH_EP93XX
|
||||
default 8
|
||||
|
||||
config IWMMXT
|
||||
bool "Enable iWMMXt support"
|
||||
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
|
||||
@@ -1230,19 +1222,6 @@ config ARM_ERRATA_742231
|
||||
register of the Cortex-A9 which reduces the linefill issuing
|
||||
capabilities of the processor.
|
||||
|
||||
config PL310_ERRATA_588369
|
||||
bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
|
||||
depends on CACHE_L2X0
|
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help
|
||||
The PL310 L2 cache controller implements three types of Clean &
|
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Invalidate maintenance operations: by Physical Address
|
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(offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
|
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They are architecturally defined to behave as the execution of a
|
||||
clean operation followed immediately by an invalidate operation,
|
||||
both performing to the same memory location. This functionality
|
||||
is not correctly implemented in PL310 as clean lines are not
|
||||
invalidated as a result of these operations.
|
||||
|
||||
config ARM_ERRATA_643719
|
||||
bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
|
||||
depends on CPU_V7 && SMP
|
||||
@@ -1265,17 +1244,6 @@ config ARM_ERRATA_720789
|
||||
tables. The workaround changes the TLB flushing routines to invalidate
|
||||
entries regardless of the ASID.
|
||||
|
||||
config PL310_ERRATA_727915
|
||||
bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
|
||||
depends on CACHE_L2X0
|
||||
help
|
||||
PL310 implements the Clean & Invalidate by Way L2 cache maintenance
|
||||
operation (offset 0x7FC). This operation runs in background so that
|
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PL310 can handle normal accesses while it is in progress. Under very
|
||||
rare circumstances, due to this erratum, write data can be lost when
|
||||
PL310 treats a cacheable write transaction during a Clean &
|
||||
Invalidate by Way operation.
|
||||
|
||||
config ARM_ERRATA_743622
|
||||
bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
|
||||
depends on CPU_V7
|
||||
@@ -1301,21 +1269,6 @@ config ARM_ERRATA_751472
|
||||
operation is received by a CPU before the ICIALLUIS has completed,
|
||||
potentially leading to corrupted entries in the cache or TLB.
|
||||
|
||||
config PL310_ERRATA_753970
|
||||
bool "PL310 errata: cache sync operation may be faulty"
|
||||
depends on CACHE_PL310
|
||||
help
|
||||
This option enables the workaround for the 753970 PL310 (r3p0) erratum.
|
||||
|
||||
Under some condition the effect of cache sync operation on
|
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the store buffer still remains when the operation completes.
|
||||
This means that the store buffer is always asked to drain and
|
||||
this prevents it from merging any further writes. The workaround
|
||||
is to replace the normal offset of cache sync operation (0x730)
|
||||
by another offset targeting an unmapped PL310 register 0x740.
|
||||
This has the same effect as the cache sync operation: store buffer
|
||||
drain and waiting for all buffers empty.
|
||||
|
||||
config ARM_ERRATA_754322
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||||
bool "ARM errata: possible faulty MMU translations following an ASID switch"
|
||||
depends on CPU_V7
|
||||
@@ -1364,18 +1317,6 @@ config ARM_ERRATA_764369
|
||||
relevant cache maintenance functions and sets a specific bit
|
||||
in the diagnostic control register of the SCU.
|
||||
|
||||
config PL310_ERRATA_769419
|
||||
bool "PL310 errata: no automatic Store Buffer drain"
|
||||
depends on CACHE_L2X0
|
||||
help
|
||||
On revisions of the PL310 prior to r3p2, the Store Buffer does
|
||||
not automatically drain. This can cause normal, non-cacheable
|
||||
writes to be retained when the memory system is idle, leading
|
||||
to suboptimal I/O performance for drivers using coherent DMA.
|
||||
This option adds a write barrier to the cpu_idle loop so that,
|
||||
on systems with an outer cache, the store buffer is drained
|
||||
explicitly.
|
||||
|
||||
config ARM_ERRATA_775420
|
||||
bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
|
||||
depends on CPU_V7
|
||||
@@ -2295,6 +2236,11 @@ config ARCH_SUSPEND_POSSIBLE
|
||||
config ARM_CPU_SUSPEND
|
||||
def_bool PM_SLEEP
|
||||
|
||||
config ARCH_HIBERNATION_POSSIBLE
|
||||
bool
|
||||
depends on MMU
|
||||
default y if ARCH_SUSPEND_POSSIBLE
|
||||
|
||||
endmenu
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|
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source "net/Kconfig"
|
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@@ -7,6 +7,8 @@
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#define do_extend_cmdline 0
|
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#endif
|
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|
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#define NR_BANKS 16
|
||||
|
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static int node_offset(void *fdt, const char *node_path)
|
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{
|
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int offset = fdt_path_offset(fdt, node_path);
|
||||
|
||||
@@ -36,7 +36,7 @@
|
||||
ranges = <0x40000000 0x40000000 0xa0000000>;
|
||||
|
||||
l2-cache-controller@c0030000 {
|
||||
compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xc0030000 0x1000>;
|
||||
interrupts = <0 59 0>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
|
||||
@@ -48,7 +48,7 @@
|
||||
ranges = <0x40000000 0x40000000 0x80000000>;
|
||||
|
||||
l2-cache-controller@80040000 {
|
||||
compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x80040000 0x1000>;
|
||||
interrupts = <59>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
|
||||
@@ -433,8 +433,12 @@ static void bL_switcher_restore_cpus(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for_each_cpu(i, &bL_switcher_removed_logical_cpus)
|
||||
cpu_up(i);
|
||||
for_each_cpu(i, &bL_switcher_removed_logical_cpus) {
|
||||
struct device *cpu_dev = get_cpu_device(i);
|
||||
int ret = device_online(cpu_dev);
|
||||
if (ret)
|
||||
dev_err(cpu_dev, "switcher: unable to restore CPU\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int bL_switcher_halve_cpus(void)
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@@ -521,7 +525,7 @@ static int bL_switcher_halve_cpus(void)
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = cpu_down(i);
|
||||
ret = device_offline(get_cpu_device(i));
|
||||
if (ret) {
|
||||
bL_switcher_restore_cpus();
|
||||
return ret;
|
||||
|
||||
@@ -106,14 +106,14 @@ void mcpm_cpu_power_down(void)
|
||||
BUG();
|
||||
}
|
||||
|
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int mcpm_cpu_power_down_finish(unsigned int cpu, unsigned int cluster)
|
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int mcpm_wait_for_cpu_powerdown(unsigned int cpu, unsigned int cluster)
|
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{
|
||||
int ret;
|
||||
|
||||
if (WARN_ON_ONCE(!platform_ops || !platform_ops->power_down_finish))
|
||||
if (WARN_ON_ONCE(!platform_ops || !platform_ops->wait_for_powerdown))
|
||||
return -EUNATCH;
|
||||
|
||||
ret = platform_ops->power_down_finish(cpu, cluster);
|
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ret = platform_ops->wait_for_powerdown(cpu, cluster);
|
||||
if (ret)
|
||||
pr_warn("%s: cpu %u, cluster %u failed to power down (%d)\n",
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__func__, cpu, cluster, ret);
|
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|
||||
@@ -62,7 +62,7 @@ static int mcpm_cpu_kill(unsigned int cpu)
|
||||
|
||||
cpu_to_pcpu(cpu, &pcpu, &pcluster);
|
||||
|
||||
return !mcpm_cpu_power_down_finish(pcpu, pcluster);
|
||||
return !mcpm_wait_for_cpu_powerdown(pcpu, pcluster);
|
||||
}
|
||||
|
||||
static int mcpm_cpu_disable(unsigned int cpu)
|
||||
|
||||
@@ -21,6 +21,7 @@ generic-y += parport.h
|
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generic-y += poll.h
|
||||
generic-y += preempt.h
|
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generic-y += resource.h
|
||||
generic-y += rwsem.h
|
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generic-y += sections.h
|
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generic-y += segment.h
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generic-y += sembuf.h
|
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@@ -312,7 +312,7 @@
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* you cannot return to the original mode.
|
||||
*/
|
||||
.macro safe_svcmode_maskall reg:req
|
||||
#if __LINUX_ARM_ARCH__ >= 6
|
||||
#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
|
||||
mrs \reg , cpsr
|
||||
eor \reg, \reg, #HYP_MODE
|
||||
tst \reg, #MODE_MASK
|
||||
|
||||
@@ -212,7 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
|
||||
static inline void __flush_icache_all(void)
|
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{
|
||||
__flush_icache_preferred();
|
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dsb();
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||||
dsb(ishst);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -487,4 +487,6 @@ int set_memory_rw(unsigned long addr, int numpages);
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int set_memory_x(unsigned long addr, int numpages);
|
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int set_memory_nx(unsigned long addr, int numpages);
|
||||
|
||||
void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
|
||||
void *kaddr, unsigned long len);
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||||
#endif
|
||||
|
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@@ -72,6 +72,7 @@
|
||||
#define ARM_CPU_PART_CORTEX_A15 0xC0F0
|
||||
#define ARM_CPU_PART_CORTEX_A7 0xC070
|
||||
#define ARM_CPU_PART_CORTEX_A12 0xC0D0
|
||||
#define ARM_CPU_PART_CORTEX_A17 0xC0E0
|
||||
|
||||
#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
|
||||
#define ARM_CPU_XSCALE_ARCH_V1 0x2000
|
||||
|
||||
@@ -1,24 +1,11 @@
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#ifndef _ASM_FIXMAP_H
|
||||
#define _ASM_FIXMAP_H
|
||||
|
||||
/*
|
||||
* Nothing too fancy for now.
|
||||
*
|
||||
* On ARM we already have well known fixed virtual addresses imposed by
|
||||
* the architecture such as the vector page which is located at 0xffff0000,
|
||||
* therefore a second level page table is already allocated covering
|
||||
* 0xfff00000 upwards.
|
||||
*
|
||||
* The cache flushing code in proc-xscale.S uses the virtual area between
|
||||
* 0xfffe0000 and 0xfffeffff.
|
||||
*/
|
||||
|
||||
#define FIXADDR_START 0xfff00000UL
|
||||
#define FIXADDR_TOP 0xfffe0000UL
|
||||
#define FIXADDR_START 0xffc00000UL
|
||||
#define FIXADDR_TOP 0xffe00000UL
|
||||
#define FIXADDR_SIZE (FIXADDR_TOP - FIXADDR_START)
|
||||
|
||||
#define FIX_KMAP_BEGIN 0
|
||||
#define FIX_KMAP_END (FIXADDR_SIZE >> PAGE_SHIFT)
|
||||
#define FIX_KMAP_NR_PTES (FIXADDR_SIZE >> PAGE_SHIFT)
|
||||
|
||||
#define __fix_to_virt(x) (FIXADDR_START + ((x) << PAGE_SHIFT))
|
||||
#define __virt_to_fix(x) (((x) - FIXADDR_START) >> PAGE_SHIFT)
|
||||
@@ -27,7 +14,7 @@ extern void __this_fixmap_does_not_exist(void);
|
||||
|
||||
static inline unsigned long fix_to_virt(const unsigned int idx)
|
||||
{
|
||||
if (idx >= FIX_KMAP_END)
|
||||
if (idx >= FIX_KMAP_NR_PTES)
|
||||
__this_fixmap_does_not_exist();
|
||||
return __fix_to_virt(idx);
|
||||
}
|
||||
|
||||
@@ -31,14 +31,6 @@
|
||||
#undef CPU_DABORT_HANDLER
|
||||
#undef MULTI_DABORT
|
||||
|
||||
#if defined(CONFIG_CPU_ARM710)
|
||||
# ifdef CPU_DABORT_HANDLER
|
||||
# define MULTI_DABORT 1
|
||||
# else
|
||||
# define CPU_DABORT_HANDLER cpu_arm7_data_abort
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_ABRT_EV4
|
||||
# ifdef CPU_DABORT_HANDLER
|
||||
# define MULTI_DABORT 1
|
||||
|
||||
@@ -26,8 +26,8 @@
|
||||
#define L2X0_CACHE_TYPE 0x004
|
||||
#define L2X0_CTRL 0x100
|
||||
#define L2X0_AUX_CTRL 0x104
|
||||
#define L2X0_TAG_LATENCY_CTRL 0x108
|
||||
#define L2X0_DATA_LATENCY_CTRL 0x10C
|
||||
#define L310_TAG_LATENCY_CTRL 0x108
|
||||
#define L310_DATA_LATENCY_CTRL 0x10C
|
||||
#define L2X0_EVENT_CNT_CTRL 0x200
|
||||
#define L2X0_EVENT_CNT1_CFG 0x204
|
||||
#define L2X0_EVENT_CNT0_CFG 0x208
|
||||
@@ -54,53 +54,93 @@
|
||||
#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
|
||||
#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
|
||||
#define L2X0_LOCKDOWN_STRIDE 0x08
|
||||
#define L2X0_ADDR_FILTER_START 0xC00
|
||||
#define L2X0_ADDR_FILTER_END 0xC04
|
||||
#define L310_ADDR_FILTER_START 0xC00
|
||||
#define L310_ADDR_FILTER_END 0xC04
|
||||
#define L2X0_TEST_OPERATION 0xF00
|
||||
#define L2X0_LINE_DATA 0xF10
|
||||
#define L2X0_LINE_TAG 0xF30
|
||||
#define L2X0_DEBUG_CTRL 0xF40
|
||||
#define L2X0_PREFETCH_CTRL 0xF60
|
||||
#define L2X0_POWER_CTRL 0xF80
|
||||
#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)
|
||||
#define L2X0_STNDBY_MODE_EN (1 << 0)
|
||||
#define L310_PREFETCH_CTRL 0xF60
|
||||
#define L310_POWER_CTRL 0xF80
|
||||
#define L310_DYNAMIC_CLK_GATING_EN (1 << 1)
|
||||
#define L310_STNDBY_MODE_EN (1 << 0)
|
||||
|
||||
/* Registers shifts and masks */
|
||||
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
|
||||
#define L2X0_CACHE_ID_PART_L210 (1 << 6)
|
||||
#define L2X0_CACHE_ID_PART_L220 (2 << 6)
|
||||
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
|
||||
#define L2X0_CACHE_ID_RTL_MASK 0x3f
|
||||
#define L2X0_CACHE_ID_RTL_R0P0 0x0
|
||||
#define L2X0_CACHE_ID_RTL_R1P0 0x2
|
||||
#define L2X0_CACHE_ID_RTL_R2P0 0x4
|
||||
#define L2X0_CACHE_ID_RTL_R3P0 0x5
|
||||
#define L2X0_CACHE_ID_RTL_R3P1 0x6
|
||||
#define L2X0_CACHE_ID_RTL_R3P2 0x8
|
||||
#define L210_CACHE_ID_RTL_R0P2_02 0x00
|
||||
#define L210_CACHE_ID_RTL_R0P1 0x01
|
||||
#define L210_CACHE_ID_RTL_R0P2_01 0x02
|
||||
#define L210_CACHE_ID_RTL_R0P3 0x03
|
||||
#define L210_CACHE_ID_RTL_R0P4 0x0b
|
||||
#define L210_CACHE_ID_RTL_R0P5 0x0f
|
||||
#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06
|
||||
#define L310_CACHE_ID_RTL_R0P0 0x00
|
||||
#define L310_CACHE_ID_RTL_R1P0 0x02
|
||||
#define L310_CACHE_ID_RTL_R2P0 0x04
|
||||
#define L310_CACHE_ID_RTL_R3P0 0x05
|
||||
#define L310_CACHE_ID_RTL_R3P1 0x06
|
||||
#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07
|
||||
#define L310_CACHE_ID_RTL_R3P2 0x08
|
||||
#define L310_CACHE_ID_RTL_R3P3 0x09
|
||||
|
||||
#define L2X0_AUX_CTRL_MASK 0xc0000fff
|
||||
/* L2C auxiliary control register - bits common to L2C-210/220/310 */
|
||||
#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17
|
||||
#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17)
|
||||
#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17)
|
||||
#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)
|
||||
#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)
|
||||
#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)
|
||||
/* L2C-210/220 common bits */
|
||||
#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
|
||||
#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7
|
||||
#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0)
|
||||
#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
|
||||
#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)
|
||||
#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3)
|
||||
#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
|
||||
#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)
|
||||
#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6)
|
||||
#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
|
||||
#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)
|
||||
#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
|
||||
#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
|
||||
#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
|
||||
#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
|
||||
#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
|
||||
#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
|
||||
#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28
|
||||
#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29
|
||||
#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30
|
||||
#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9)
|
||||
#define L2X0_AUX_CTRL_ASSOC_SHIFT 13
|
||||
#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13)
|
||||
/* L2C-210 specific bits */
|
||||
#define L210_AUX_CTRL_WRAP_DISABLE BIT(12)
|
||||
#define L210_AUX_CTRL_WA_OVERRIDE BIT(23)
|
||||
#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)
|
||||
/* L2C-220 specific bits */
|
||||
#define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
|
||||
#define L220_AUX_CTRL_FWA_SHIFT 23
|
||||
#define L220_AUX_CTRL_FWA_MASK (3 << 23)
|
||||
#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)
|
||||
#define L220_AUX_CTRL_NS_INT_CTRL BIT(27)
|
||||
/* L2C-310 specific bits */
|
||||
#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
|
||||
#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
|
||||
#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
|
||||
#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
|
||||
#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
|
||||
#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
|
||||
#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
|
||||
#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
|
||||
#define L310_AUX_CTRL_DATA_PREFETCH BIT(28)
|
||||
#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29)
|
||||
#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
|
||||
|
||||
#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0
|
||||
#define L2X0_LATENCY_CTRL_RD_SHIFT 4
|
||||
#define L2X0_LATENCY_CTRL_WR_SHIFT 8
|
||||
#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
|
||||
#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
|
||||
#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
|
||||
|
||||
#define L2X0_ADDR_FILTER_EN 1
|
||||
#define L310_ADDR_FILTER_EN 1
|
||||
|
||||
#define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f
|
||||
#define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23)
|
||||
#define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24)
|
||||
#define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27)
|
||||
#define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28)
|
||||
#define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29)
|
||||
#define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30)
|
||||
|
||||
#define L2X0_CTRL_EN 1
|
||||
|
||||
|
||||
@@ -18,6 +18,7 @@
|
||||
} while (0)
|
||||
|
||||
extern pte_t *pkmap_page_table;
|
||||
extern pte_t *fixmap_page_table;
|
||||
|
||||
extern void *kmap_high(struct page *page);
|
||||
extern void kunmap_high(struct page *page);
|
||||
|
||||
@@ -179,6 +179,12 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
|
||||
/* PCI fixed i/o mapping */
|
||||
#define PCI_IO_VIRT_BASE 0xfee00000
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
void pci_ioremap_set_mem_type(int mem_type);
|
||||
#else
|
||||
static inline void pci_ioremap_set_mem_type(int mem_type) {}
|
||||
#endif
|
||||
|
||||
extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
|
||||
|
||||
/*
|
||||
|
||||
@@ -14,7 +14,6 @@
|
||||
#include <linux/reboot.h>
|
||||
|
||||
struct tag;
|
||||
struct meminfo;
|
||||
struct pt_regs;
|
||||
struct smp_operations;
|
||||
#ifdef CONFIG_SMP
|
||||
@@ -45,10 +44,12 @@ struct machine_desc {
|
||||
unsigned char reserve_lp1 :1; /* never has lp1 */
|
||||
unsigned char reserve_lp2 :1; /* never has lp2 */
|
||||
enum reboot_mode reboot_mode; /* default restart mode */
|
||||
unsigned l2c_aux_val; /* L2 cache aux value */
|
||||
unsigned l2c_aux_mask; /* L2 cache aux mask */
|
||||
void (*l2c_write_sec)(unsigned long, unsigned);
|
||||
struct smp_operations *smp; /* SMP operations */
|
||||
bool (*smp_init)(void);
|
||||
void (*fixup)(struct tag *, char **,
|
||||
struct meminfo *);
|
||||
void (*fixup)(struct tag *, char **);
|
||||
void (*init_meminfo)(void);
|
||||
void (*reserve)(void);/* reserve mem blocks */
|
||||
void (*map_io)(void);/* IO mapping function */
|
||||
|
||||
@@ -98,14 +98,14 @@ int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster);
|
||||
* previously in which case the caller should take appropriate action.
|
||||
*
|
||||
* On success, the CPU is not guaranteed to be truly halted until
|
||||
* mcpm_cpu_power_down_finish() subsequently returns non-zero for the
|
||||
* mcpm_wait_for_cpu_powerdown() subsequently returns non-zero for the
|
||||
* specified cpu. Until then, other CPUs should make sure they do not
|
||||
* trash memory the target CPU might be executing/accessing.
|
||||
*/
|
||||
void mcpm_cpu_power_down(void);
|
||||
|
||||
/**
|
||||
* mcpm_cpu_power_down_finish - wait for a specified CPU to halt, and
|
||||
* mcpm_wait_for_cpu_powerdown - wait for a specified CPU to halt, and
|
||||
* make sure it is powered off
|
||||
*
|
||||
* @cpu: CPU number within given cluster
|
||||
@@ -127,7 +127,7 @@ void mcpm_cpu_power_down(void);
|
||||
* - zero if the CPU is in a safely parked state
|
||||
* - nonzero otherwise (e.g., timeout)
|
||||
*/
|
||||
int mcpm_cpu_power_down_finish(unsigned int cpu, unsigned int cluster);
|
||||
int mcpm_wait_for_cpu_powerdown(unsigned int cpu, unsigned int cluster);
|
||||
|
||||
/**
|
||||
* mcpm_cpu_suspend - bring the calling CPU in a suspended state
|
||||
@@ -171,7 +171,7 @@ int mcpm_cpu_powered_up(void);
|
||||
struct mcpm_platform_ops {
|
||||
int (*power_up)(unsigned int cpu, unsigned int cluster);
|
||||
void (*power_down)(void);
|
||||
int (*power_down_finish)(unsigned int cpu, unsigned int cluster);
|
||||
int (*wait_for_powerdown)(unsigned int cpu, unsigned int cluster);
|
||||
void (*suspend)(u64);
|
||||
void (*powered_up)(void);
|
||||
};
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user