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[PATCH] FRV: Use the generic IRQ stuff
Make the FRV arch use the generic IRQ code rather than having its own routines for doing so. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
David Howells
committed by
Linus Torvalds
Linus Torvalds
parent
8d6b5eeea5
commit
1bcbba3060
+7
-1
@@ -27,7 +27,7 @@ config GENERIC_CALIBRATE_DELAY
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config GENERIC_HARDIRQS
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bool
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default n
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default y
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config GENERIC_TIME
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bool
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@@ -251,6 +251,12 @@ config MB93091_NO_MB
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endchoice
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endif
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config FUJITSU_MB93493
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bool "MB93493 Multimedia chip"
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help
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Select this option if the MB93493 multimedia chip is going to be
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used.
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choice
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prompt "GP-Relative data support"
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default GPREL_DATA_8
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@@ -10,15 +10,14 @@ extra-y:= head.o init_task.o vmlinux.lds
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obj-y := $(heads-y) entry.o entry-table.o break.o switch_to.o kernel_thread.o \
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process.o traps.o ptrace.o signal.o dma.o \
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sys_frv.o time.o semaphore.o setup.o frv_ksyms.o \
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debug-stub.o irq.o irq-routing.o sleep.o uaccess.o
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debug-stub.o irq.o sleep.o uaccess.o
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obj-$(CONFIG_GDBSTUB) += gdb-stub.o gdb-io.o
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obj-$(CONFIG_MB93091_VDK) += irq-mb93091.o
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obj-$(CONFIG_MB93093_PDK) += irq-mb93093.o
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obj-$(CONFIG_FUJITSU_MB93493) += irq-mb93493.o
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obj-$(CONFIG_PM) += pm.o cmode.o
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obj-$(CONFIG_MB93093_PDK) += pm-mb93093.o
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obj-$(CONFIG_FUJITSU_MB93493) += irq-mb93493.o
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obj-$(CONFIG_SYSCTL) += sysctl.o
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obj-$(CONFIG_FUTEX) += futex.o
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obj-$(CONFIG_MODULES) += module.o
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+106
-61
@@ -24,7 +24,6 @@
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#include <asm/delay.h>
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#include <asm/irq.h>
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#include <asm/irc-regs.h>
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#include <asm/irq-routing.h>
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#define __reg16(ADDR) (*(volatile unsigned short *)(ADDR))
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@@ -33,83 +32,129 @@
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#define __get_IFR() ({ __reg16(0xffc0000c); })
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#define __clr_IFR(M) do { __reg16(0xffc0000c) = ~(M); wmb(); } while(0)
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static void frv_fpga_doirq(struct irq_source *source);
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static void frv_fpga_control(struct irq_group *group, int irq, int on);
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/*****************************************************************************/
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/*
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* FPGA IRQ multiplexor
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* on-motherboard FPGA PIC operations
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*/
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static struct irq_source frv_fpga[4] = {
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#define __FPGA(X, M) \
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[X] = { \
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.muxname = "fpga."#X, \
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.irqmask = M, \
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.doirq = frv_fpga_doirq, \
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}
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__FPGA(0, 0x0028),
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__FPGA(1, 0x0050),
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__FPGA(2, 0x1c00),
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__FPGA(3, 0x6386),
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};
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static struct irq_group frv_fpga_irqs = {
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.first_irq = IRQ_BASE_FPGA,
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.control = frv_fpga_control,
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.sources = {
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[ 1] = &frv_fpga[3],
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[ 2] = &frv_fpga[3],
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[ 3] = &frv_fpga[0],
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[ 4] = &frv_fpga[1],
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[ 5] = &frv_fpga[0],
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[ 6] = &frv_fpga[1],
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[ 7] = &frv_fpga[3],
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[ 8] = &frv_fpga[3],
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[ 9] = &frv_fpga[3],
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[10] = &frv_fpga[2],
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[11] = &frv_fpga[2],
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[12] = &frv_fpga[2],
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[13] = &frv_fpga[3],
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[14] = &frv_fpga[3],
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},
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};
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static void frv_fpga_control(struct irq_group *group, int index, int on)
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static void frv_fpga_enable(unsigned int irq)
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{
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uint16_t imr = __get_IMR();
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if (on)
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imr &= ~(1 << index);
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else
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imr |= 1 << index;
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imr &= ~(1 << (irq - IRQ_BASE_FPGA));
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__set_IMR(imr);
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}
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static void frv_fpga_doirq(struct irq_source *source)
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static void frv_fpga_disable(unsigned int irq)
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{
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uint16_t mask, imr;
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uint16_t imr = __get_IMR();
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imr = __get_IMR();
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mask = source->irqmask & ~imr & __get_IFR();
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if (mask) {
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__set_IMR(imr | mask);
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__clr_IFR(mask);
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distribute_irqs(&frv_fpga_irqs, mask);
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__set_IMR(imr);
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}
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imr |= 1 << (irq - IRQ_BASE_FPGA);
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__set_IMR(imr);
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}
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static void frv_fpga_ack(unsigned int irq)
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{
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__clr_IFR(1 << (irq - IRQ_BASE_FPGA));
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}
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static void frv_fpga_end(unsigned int irq)
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{
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}
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static struct irq_chip frv_fpga_pic = {
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.name = "mb93091",
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.enable = frv_fpga_enable,
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.disable = frv_fpga_disable,
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.ack = frv_fpga_ack,
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.mask = frv_fpga_disable,
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.unmask = frv_fpga_enable,
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.end = frv_fpga_end,
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};
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/*
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* FPGA PIC interrupt handler
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*/
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static irqreturn_t fpga_interrupt(int irq, void *_mask, struct pt_regs *regs)
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{
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uint16_t imr, mask = (unsigned long) _mask;
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irqreturn_t iret = 0;
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imr = __get_IMR();
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mask = mask & ~imr & __get_IFR();
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/* poll all the triggered IRQs */
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while (mask) {
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int irq;
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asm("scan %1,gr0,%0" : "=r"(irq) : "r"(mask));
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irq = 31 - irq;
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mask &= ~(1 << irq);
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if (__do_IRQ(IRQ_BASE_FPGA + irq, regs))
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iret |= IRQ_HANDLED;
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}
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return iret;
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}
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/*
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* define an interrupt action for each FPGA PIC output
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* - use dev_id to indicate the FPGA PIC input to output mappings
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*/
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static struct irqaction fpga_irq[4] = {
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[0] = {
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.handler = fpga_interrupt,
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.flags = IRQF_DISABLED | IRQF_SHARED,
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.mask = CPU_MASK_NONE,
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.name = "fpga.0",
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.dev_id = (void *) 0x0028UL,
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},
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[1] = {
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.handler = fpga_interrupt,
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.flags = IRQF_DISABLED | IRQF_SHARED,
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.mask = CPU_MASK_NONE,
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.name = "fpga.1",
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.dev_id = (void *) 0x0050UL,
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},
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[2] = {
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.handler = fpga_interrupt,
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.flags = IRQF_DISABLED | IRQF_SHARED,
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.mask = CPU_MASK_NONE,
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.name = "fpga.2",
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.dev_id = (void *) 0x1c00UL,
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},
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[3] = {
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.handler = fpga_interrupt,
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.flags = IRQF_DISABLED | IRQF_SHARED,
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.mask = CPU_MASK_NONE,
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.name = "fpga.3",
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.dev_id = (void *) 0x6386UL,
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}
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};
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/*
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* initialise the motherboard FPGA's PIC
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*/
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void __init fpga_init(void)
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{
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int irq;
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/* all PIC inputs are all set to be low-level driven, apart from the
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* NMI button (15) which is fixed at falling-edge
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*/
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__set_IMR(0x7ffe);
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__clr_IFR(0x0000);
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frv_irq_route_external(&frv_fpga[0], IRQ_CPU_EXTERNAL0);
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frv_irq_route_external(&frv_fpga[1], IRQ_CPU_EXTERNAL1);
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frv_irq_route_external(&frv_fpga[2], IRQ_CPU_EXTERNAL2);
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frv_irq_route_external(&frv_fpga[3], IRQ_CPU_EXTERNAL3);
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frv_irq_set_group(&frv_fpga_irqs);
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for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++)
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set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);
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set_irq_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);
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/* the FPGA drives the first four external IRQ inputs on the CPU PIC */
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setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]);
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setup_irq(IRQ_CPU_EXTERNAL1, &fpga_irq[1]);
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setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[2]);
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setup_irq(IRQ_CPU_EXTERNAL3, &fpga_irq[3]);
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}
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@@ -1,6 +1,6 @@
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/* irq-mb93093.c: MB93093 FPGA interrupt handling
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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@@ -24,7 +24,6 @@
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#include <asm/delay.h>
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#include <asm/irq.h>
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#include <asm/irc-regs.h>
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#include <asm/irq-routing.h>
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#define __reg16(ADDR) (*(volatile unsigned short *)(__region_CS2 + (ADDR)))
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@@ -33,66 +32,100 @@
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#define __get_IFR() ({ __reg16(0x02); })
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#define __clr_IFR(M) do { __reg16(0x02) = ~(M); wmb(); } while(0)
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static void frv_fpga_doirq(struct irq_source *source);
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static void frv_fpga_control(struct irq_group *group, int irq, int on);
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/*****************************************************************************/
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/*
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* FPGA IRQ multiplexor
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* off-CPU FPGA PIC operations
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*/
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static struct irq_source frv_fpga[4] = {
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#define __FPGA(X, M) \
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[X] = { \
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.muxname = "fpga."#X, \
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.irqmask = M, \
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.doirq = frv_fpga_doirq, \
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}
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__FPGA(0, 0x0700),
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};
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static struct irq_group frv_fpga_irqs = {
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.first_irq = IRQ_BASE_FPGA,
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.control = frv_fpga_control,
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.sources = {
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[ 8] = &frv_fpga[0],
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[ 9] = &frv_fpga[0],
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[10] = &frv_fpga[0],
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},
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};
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static void frv_fpga_control(struct irq_group *group, int index, int on)
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static void frv_fpga_enable(unsigned int irq)
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{
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uint16_t imr = __get_IMR();
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if (on)
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imr &= ~(1 << index);
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else
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imr |= 1 << index;
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imr &= ~(1 << (irq - IRQ_BASE_FPGA));
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__set_IMR(imr);
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}
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static void frv_fpga_doirq(struct irq_source *source)
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static void frv_fpga_disable(unsigned int irq)
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{
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uint16_t mask, imr;
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uint16_t imr = __get_IMR();
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imr = __get_IMR();
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mask = source->irqmask & ~imr & __get_IFR();
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if (mask) {
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__set_IMR(imr | mask);
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__clr_IFR(mask);
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distribute_irqs(&frv_fpga_irqs, mask);
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__set_IMR(imr);
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}
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imr |= 1 << (irq - IRQ_BASE_FPGA);
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__set_IMR(imr);
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}
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static void frv_fpga_ack(unsigned int irq)
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{
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__clr_IFR(1 << (irq - IRQ_BASE_FPGA));
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}
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static void frv_fpga_end(unsigned int irq)
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{
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}
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static struct irq_chip frv_fpga_pic = {
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.name = "mb93093",
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.enable = frv_fpga_enable,
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.disable = frv_fpga_disable,
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.ack = frv_fpga_ack,
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.mask = frv_fpga_disable,
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.unmask = frv_fpga_enable,
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.end = frv_fpga_end,
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};
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/*
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* FPGA PIC interrupt handler
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*/
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static irqreturn_t fpga_interrupt(int irq, void *_mask, struct pt_regs *regs)
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{
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uint16_t imr, mask = (unsigned long) _mask;
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irqreturn_t iret = 0;
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imr = __get_IMR();
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mask = mask & ~imr & __get_IFR();
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/* poll all the triggered IRQs */
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while (mask) {
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int irq;
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asm("scan %1,gr0,%0" : "=r"(irq) : "r"(mask));
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irq = 31 - irq;
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mask &= ~(1 << irq);
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if (__do_IRQ(IRQ_BASE_FPGA + irq, regs))
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iret |= IRQ_HANDLED;
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}
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return iret;
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}
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/*
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* define an interrupt action for each FPGA PIC output
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* - use dev_id to indicate the FPGA PIC input to output mappings
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*/
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static struct irqaction fpga_irq[1] = {
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[0] = {
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.handler = fpga_interrupt,
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.flags = IRQF_DISABLED,
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.mask = CPU_MASK_NONE,
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.name = "fpga.0",
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.dev_id = (void *) 0x0700UL,
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}
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};
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/*
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* initialise the motherboard FPGA's PIC
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*/
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void __init fpga_init(void)
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{
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int irq;
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/* all PIC inputs are all set to be edge triggered */
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__set_IMR(0x0700);
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__clr_IFR(0x0000);
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frv_irq_route_external(&frv_fpga[0], IRQ_CPU_EXTERNAL2);
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frv_irq_set_group(&frv_fpga_irqs);
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for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)
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set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
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/* the FPGA drives external IRQ input #2 on the CPU PIC */
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setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
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}
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+111
-62
@@ -1,6 +1,6 @@
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/* irq-mb93493.c: MB93493 companion chip interrupt handler
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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@@ -24,84 +24,133 @@
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#include <asm/delay.h>
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#include <asm/irq.h>
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#include <asm/irc-regs.h>
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#include <asm/irq-routing.h>
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#include <asm/mb93493-irqs.h>
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#include <asm/mb93493-regs.h>
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static void frv_mb93493_doirq(struct irq_source *source);
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#define IRQ_ROUTE_ONE(X) (X##_ROUTE << (X - IRQ_BASE_MB93493))
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#define IRQ_ROUTING \
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(IRQ_ROUTE_ONE(IRQ_MB93493_VDC) | \
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IRQ_ROUTE_ONE(IRQ_MB93493_VCC) | \
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IRQ_ROUTE_ONE(IRQ_MB93493_AUDIO_OUT) | \
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IRQ_ROUTE_ONE(IRQ_MB93493_I2C_0) | \
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IRQ_ROUTE_ONE(IRQ_MB93493_I2C_1) | \
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IRQ_ROUTE_ONE(IRQ_MB93493_USB) | \
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IRQ_ROUTE_ONE(IRQ_MB93493_LOCAL_BUS) | \
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IRQ_ROUTE_ONE(IRQ_MB93493_PCMCIA) | \
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IRQ_ROUTE_ONE(IRQ_MB93493_GPIO) | \
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IRQ_ROUTE_ONE(IRQ_MB93493_AUDIO_IN))
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/*****************************************************************************/
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/*
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* MB93493 companion chip IRQ multiplexor
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* daughter board PIC operations
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*/
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static struct irq_source frv_mb93493[2] = {
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[0] = {
|
||||
.muxname = "mb93493.0",
|
||||
.muxdata = __region_CS3 + 0x3d0,
|
||||
.doirq = frv_mb93493_doirq,
|
||||
.irqmask = 0x0000,
|
||||
},
|
||||
[1] = {
|
||||
.muxname = "mb93493.1",
|
||||
.muxdata = __region_CS3 + 0x3d4,
|
||||
.doirq = frv_mb93493_doirq,
|
||||
.irqmask = 0x0000,
|
||||
},
|
||||
static void frv_mb93493_enable(unsigned int irq)
|
||||
{
|
||||
uint32_t iqsr;
|
||||
volatile void *piqsr;
|
||||
|
||||
if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493)))
|
||||
piqsr = __addr_MB93493_IQSR(1);
|
||||
else
|
||||
piqsr = __addr_MB93493_IQSR(0);
|
||||
|
||||
iqsr = readl(piqsr);
|
||||
iqsr |= 1 << (irq - IRQ_BASE_MB93493 + 16);
|
||||
writel(iqsr, piqsr);
|
||||
}
|
||||
|
||||
static void frv_mb93493_disable(unsigned int irq)
|
||||
{
|
||||
uint32_t iqsr;
|
||||
volatile void *piqsr;
|
||||
|
||||
if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493)))
|
||||
piqsr = __addr_MB93493_IQSR(1);
|
||||
else
|
||||
piqsr = __addr_MB93493_IQSR(0);
|
||||
|
||||
iqsr = readl(piqsr);
|
||||
iqsr &= ~(1 << (irq - IRQ_BASE_MB93493 + 16));
|
||||
writel(iqsr, piqsr);
|
||||
}
|
||||
|
||||
static void frv_mb93493_ack(unsigned int irq)
|
||||
{
|
||||
}
|
||||
|
||||
static void frv_mb93493_end(unsigned int irq)
|
||||
{
|
||||
}
|
||||
|
||||
static struct irq_chip frv_mb93493_pic = {
|
||||
.name = "mb93093",
|
||||
.enable = frv_mb93493_enable,
|
||||
.disable = frv_mb93493_disable,
|
||||
.ack = frv_mb93493_ack,
|
||||
.mask = frv_mb93493_disable,
|
||||
.unmask = frv_mb93493_enable,
|
||||
.end = frv_mb93493_end,
|
||||
};
|
||||
|
||||
static void frv_mb93493_control(struct irq_group *group, int index, int on)
|
||||
/*
|
||||
* MB93493 PIC interrupt handler
|
||||
*/
|
||||
static irqreturn_t mb93493_interrupt(int irq, void *_piqsr, struct pt_regs *regs)
|
||||
{
|
||||
struct irq_source *source;
|
||||
volatile void *piqsr = _piqsr;
|
||||
irqreturn_t iret = 0;
|
||||
uint32_t iqsr;
|
||||
|
||||
if ((frv_mb93493[0].irqmask & (1 << index)))
|
||||
source = &frv_mb93493[0];
|
||||
else
|
||||
source = &frv_mb93493[1];
|
||||
iqsr = readl(piqsr);
|
||||
iqsr = iqsr & (iqsr >> 16) & 0xffff;
|
||||
|
||||
iqsr = readl(source->muxdata);
|
||||
if (on)
|
||||
iqsr |= 1 << (index + 16);
|
||||
else
|
||||
iqsr &= ~(1 << (index + 16));
|
||||
/* poll all the triggered IRQs */
|
||||
while (iqsr) {
|
||||
int irq;
|
||||
|
||||
writel(iqsr, source->muxdata);
|
||||
asm("scan %1,gr0,%0" : "=r"(irq) : "r"(iqsr));
|
||||
irq = 31 - irq;
|
||||
iqsr &= ~(1 << irq);
|
||||
|
||||
if (__do_IRQ(IRQ_BASE_MB93493 + irq, regs))
|
||||
iret |= IRQ_HANDLED;
|
||||
}
|
||||
|
||||
return iret;
|
||||
}
|
||||
|
||||
static struct irq_group frv_mb93493_irqs = {
|
||||
.first_irq = IRQ_BASE_MB93493,
|
||||
.control = frv_mb93493_control,
|
||||
/*
|
||||
* define an interrupt action for each MB93493 PIC output
|
||||
* - use dev_id to indicate the MB93493 PIC input to output mappings
|
||||
*/
|
||||
static struct irqaction mb93493_irq[2] = {
|
||||
[0] = {
|
||||
.handler = mb93493_interrupt,
|
||||
.flags = IRQF_DISABLED | IRQF_SHARED,
|
||||
.mask = CPU_MASK_NONE,
|
||||
.name = "mb93493.0",
|
||||
.dev_id = (void *) __addr_MB93493_IQSR(0),
|
||||
},
|
||||
[1] = {
|
||||
.handler = mb93493_interrupt,
|
||||
.flags = IRQF_DISABLED | IRQF_SHARED,
|
||||
.mask = CPU_MASK_NONE,
|
||||
.name = "mb93493.1",
|
||||
.dev_id = (void *) __addr_MB93493_IQSR(1),
|
||||
}
|
||||
};
|
||||
|
||||
static void frv_mb93493_doirq(struct irq_source *source)
|
||||
/*
|
||||
* initialise the motherboard MB93493's PIC
|
||||
*/
|
||||
void __init mb93493_init(void)
|
||||
{
|
||||
uint32_t mask = readl(source->muxdata);
|
||||
mask = mask & (mask >> 16) & 0xffff;
|
||||
int irq;
|
||||
|
||||
if (mask)
|
||||
distribute_irqs(&frv_mb93493_irqs, mask);
|
||||
}
|
||||
for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++)
|
||||
set_irq_chip_and_handler(irq, &frv_mb93493_pic, handle_edge_irq);
|
||||
|
||||
static void __init mb93493_irq_route(int irq, int source)
|
||||
{
|
||||
frv_mb93493[source].irqmask |= 1 << (irq - IRQ_BASE_MB93493);
|
||||
frv_mb93493_irqs.sources[irq - IRQ_BASE_MB93493] = &frv_mb93493[source];
|
||||
}
|
||||
|
||||
void __init route_mb93493_irqs(void)
|
||||
{
|
||||
frv_irq_route_external(&frv_mb93493[0], IRQ_CPU_MB93493_0);
|
||||
frv_irq_route_external(&frv_mb93493[1], IRQ_CPU_MB93493_1);
|
||||
|
||||
frv_irq_set_group(&frv_mb93493_irqs);
|
||||
|
||||
mb93493_irq_route(IRQ_MB93493_VDC, IRQ_MB93493_VDC_ROUTE);
|
||||
mb93493_irq_route(IRQ_MB93493_VCC, IRQ_MB93493_VCC_ROUTE);
|
||||
mb93493_irq_route(IRQ_MB93493_AUDIO_IN, IRQ_MB93493_AUDIO_IN_ROUTE);
|
||||
mb93493_irq_route(IRQ_MB93493_I2C_0, IRQ_MB93493_I2C_0_ROUTE);
|
||||
mb93493_irq_route(IRQ_MB93493_I2C_1, IRQ_MB93493_I2C_1_ROUTE);
|
||||
mb93493_irq_route(IRQ_MB93493_USB, IRQ_MB93493_USB_ROUTE);
|
||||
mb93493_irq_route(IRQ_MB93493_LOCAL_BUS, IRQ_MB93493_LOCAL_BUS_ROUTE);
|
||||
mb93493_irq_route(IRQ_MB93493_PCMCIA, IRQ_MB93493_PCMCIA_ROUTE);
|
||||
mb93493_irq_route(IRQ_MB93493_GPIO, IRQ_MB93493_GPIO_ROUTE);
|
||||
mb93493_irq_route(IRQ_MB93493_AUDIO_OUT, IRQ_MB93493_AUDIO_OUT_ROUTE);
|
||||
/* the MB93493 drives external IRQ inputs on the CPU PIC */
|
||||
setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]);
|
||||
setup_irq(IRQ_CPU_MB93493_1, &mb93493_irq[1]);
|
||||
}
|
||||
|
||||
@@ -1,291 +0,0 @@
|
||||
/* irq-routing.c: IRQ routing
|
||||
*
|
||||
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
|
||||
* Written by David Howells (dhowells@redhat.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq-routing.h>
|
||||
#include <asm/irc-regs.h>
|
||||
#include <asm/serial-regs.h>
|
||||
#include <asm/dma.h>
|
||||
|
||||
struct irq_level frv_irq_levels[16] = {
|
||||
[0 ... 15] = {
|
||||
.lock = SPIN_LOCK_UNLOCKED,
|
||||
}
|
||||
};
|
||||
|
||||
struct irq_group *irq_groups[NR_IRQ_GROUPS];
|
||||
|
||||
extern struct irq_group frv_cpu_irqs;
|
||||
|
||||
void __init frv_irq_route(struct irq_source *source, int irqlevel)
|
||||
{
|
||||
source->level = &frv_irq_levels[irqlevel];
|
||||
source->next = frv_irq_levels[irqlevel].sources;
|
||||
frv_irq_levels[irqlevel].sources = source;
|
||||
}
|
||||
|
||||
void __init frv_irq_route_external(struct irq_source *source, int irq)
|
||||
{
|
||||
int irqlevel = 0;
|
||||
|
||||
switch (irq) {
|
||||
case IRQ_CPU_EXTERNAL0: irqlevel = IRQ_XIRQ0_LEVEL; break;
|
||||
case IRQ_CPU_EXTERNAL1: irqlevel = IRQ_XIRQ1_LEVEL; break;
|
||||
case IRQ_CPU_EXTERNAL2: irqlevel = IRQ_XIRQ2_LEVEL; break;
|
||||
case IRQ_CPU_EXTERNAL3: irqlevel = IRQ_XIRQ3_LEVEL; break;
|
||||
case IRQ_CPU_EXTERNAL4: irqlevel = IRQ_XIRQ4_LEVEL; break;
|
||||
case IRQ_CPU_EXTERNAL5: irqlevel = IRQ_XIRQ5_LEVEL; break;
|
||||
case IRQ_CPU_EXTERNAL6: irqlevel = IRQ_XIRQ6_LEVEL; break;
|
||||
case IRQ_CPU_EXTERNAL7: irqlevel = IRQ_XIRQ7_LEVEL; break;
|
||||
default: BUG();
|
||||
}
|
||||
|
||||
source->level = &frv_irq_levels[irqlevel];
|
||||
source->next = frv_irq_levels[irqlevel].sources;
|
||||
frv_irq_levels[irqlevel].sources = source;
|
||||
}
|
||||
|
||||
void __init frv_irq_set_group(struct irq_group *group)
|
||||
{
|
||||
irq_groups[group->first_irq >> NR_IRQ_LOG2_ACTIONS_PER_GROUP] = group;
|
||||
}
|
||||
|
||||
void distribute_irqs(struct irq_group *group, unsigned long irqmask)
|
||||
{
|
||||
struct irqaction *action;
|
||||
int irq;
|
||||
|
||||
while (irqmask) {
|
||||
asm("scan %1,gr0,%0" : "=r"(irq) : "r"(irqmask));
|
||||
if (irq < 0 || irq > 31)
|
||||
asm volatile("break");
|
||||
irq = 31 - irq;
|
||||
|
||||
irqmask &= ~(1 << irq);
|
||||
action = group->actions[irq];
|
||||
|
||||
irq += group->first_irq;
|
||||
|
||||
if (action) {
|
||||
int status = 0;
|
||||
|
||||
// if (!(action->flags & IRQF_DISABLED))
|
||||
// local_irq_enable();
|
||||
|
||||
do {
|
||||
status |= action->flags;
|
||||
action->handler(irq, action->dev_id, __frame);
|
||||
action = action->next;
|
||||
} while (action);
|
||||
|
||||
if (status & IRQF_SAMPLE_RANDOM)
|
||||
add_interrupt_randomness(irq);
|
||||
local_irq_disable();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
* CPU UART interrupts
|
||||
*/
|
||||
static void frv_cpuuart_doirq(struct irq_source *source)
|
||||
{
|
||||
// uint8_t iir = readb(source->muxdata + UART_IIR * 8);
|
||||
// if ((iir & 0x0f) != UART_IIR_NO_INT)
|
||||
distribute_irqs(&frv_cpu_irqs, source->irqmask);
|
||||
}
|
||||
|
||||
struct irq_source frv_cpuuart[2] = {
|
||||
#define __CPUUART(X, A) \
|
||||
[X] = { \
|
||||
.muxname = "uart", \
|
||||
.muxdata = (volatile void __iomem *)(unsigned long)A,\
|
||||
.irqmask = 1 << IRQ_CPU_UART##X, \
|
||||
.doirq = frv_cpuuart_doirq, \
|
||||
}
|
||||
|
||||
__CPUUART(0, UART0_BASE),
|
||||
__CPUUART(1, UART1_BASE),
|
||||
};
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
* CPU DMA interrupts
|
||||
*/
|
||||
static void frv_cpudma_doirq(struct irq_source *source)
|
||||
{
|
||||
uint32_t cstr = readl(source->muxdata + DMAC_CSTRx);
|
||||
if (cstr & DMAC_CSTRx_INT)
|
||||
distribute_irqs(&frv_cpu_irqs, source->irqmask);
|
||||
}
|
||||
|
||||
struct irq_source frv_cpudma[8] = {
|
||||
#define __CPUDMA(X, A) \
|
||||
[X] = { \
|
||||
.muxname = "dma", \
|
||||
.muxdata = (volatile void __iomem *)(unsigned long)A,\
|
||||
.irqmask = 1 << IRQ_CPU_DMA##X, \
|
||||
.doirq = frv_cpudma_doirq, \
|
||||
}
|
||||
|
||||
__CPUDMA(0, 0xfe000900),
|
||||
__CPUDMA(1, 0xfe000980),
|
||||
__CPUDMA(2, 0xfe000a00),
|
||||
__CPUDMA(3, 0xfe000a80),
|
||||
__CPUDMA(4, 0xfe001000),
|
||||
__CPUDMA(5, 0xfe001080),
|
||||
__CPUDMA(6, 0xfe001100),
|
||||
__CPUDMA(7, 0xfe001180),
|
||||
};
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
* CPU timer interrupts - can't tell whether they've generated an interrupt or not
|
||||
*/
|
||||
static void frv_cputimer_doirq(struct irq_source *source)
|
||||
{
|
||||
distribute_irqs(&frv_cpu_irqs, source->irqmask);
|
||||
}
|
||||
|
||||
struct irq_source frv_cputimer[3] = {
|
||||
#define __CPUTIMER(X) \
|
||||
[X] = { \
|
||||
.muxname = "timer", \
|
||||
.muxdata = NULL, \
|
||||
.irqmask = 1 << IRQ_CPU_TIMER##X, \
|
||||
.doirq = frv_cputimer_doirq, \
|
||||
}
|
||||
|
||||
__CPUTIMER(0),
|
||||
__CPUTIMER(1),
|
||||
__CPUTIMER(2),
|
||||
};
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
* external CPU interrupts - can't tell directly whether they've generated an interrupt or not
|
||||
*/
|
||||
static void frv_cpuexternal_doirq(struct irq_source *source)
|
||||
{
|
||||
distribute_irqs(&frv_cpu_irqs, source->irqmask);
|
||||
}
|
||||
|
||||
struct irq_source frv_cpuexternal[8] = {
|
||||
#define __CPUEXTERNAL(X) \
|
||||
[X] = { \
|
||||
.muxname = "ext", \
|
||||
.muxdata = NULL, \
|
||||
.irqmask = 1 << IRQ_CPU_EXTERNAL##X, \
|
||||
.doirq = frv_cpuexternal_doirq, \
|
||||
}
|
||||
|
||||
__CPUEXTERNAL(0),
|
||||
__CPUEXTERNAL(1),
|
||||
__CPUEXTERNAL(2),
|
||||
__CPUEXTERNAL(3),
|
||||
__CPUEXTERNAL(4),
|
||||
__CPUEXTERNAL(5),
|
||||
__CPUEXTERNAL(6),
|
||||
__CPUEXTERNAL(7),
|
||||
};
|
||||
|
||||
#define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16))
|
||||
|
||||
struct irq_group frv_cpu_irqs = {
|
||||
.sources = {
|
||||
[IRQ_CPU_UART0] = &frv_cpuuart[0],
|
||||
[IRQ_CPU_UART1] = &frv_cpuuart[1],
|
||||
[IRQ_CPU_TIMER0] = &frv_cputimer[0],
|
||||
[IRQ_CPU_TIMER1] = &frv_cputimer[1],
|
||||
[IRQ_CPU_TIMER2] = &frv_cputimer[2],
|
||||
[IRQ_CPU_DMA0] = &frv_cpudma[0],
|
||||
[IRQ_CPU_DMA1] = &frv_cpudma[1],
|
||||
[IRQ_CPU_DMA2] = &frv_cpudma[2],
|
||||
[IRQ_CPU_DMA3] = &frv_cpudma[3],
|
||||
[IRQ_CPU_DMA4] = &frv_cpudma[4],
|
||||
[IRQ_CPU_DMA5] = &frv_cpudma[5],
|
||||
[IRQ_CPU_DMA6] = &frv_cpudma[6],
|
||||
[IRQ_CPU_DMA7] = &frv_cpudma[7],
|
||||
[IRQ_CPU_EXTERNAL0] = &frv_cpuexternal[0],
|
||||
[IRQ_CPU_EXTERNAL1] = &frv_cpuexternal[1],
|
||||
[IRQ_CPU_EXTERNAL2] = &frv_cpuexternal[2],
|
||||
[IRQ_CPU_EXTERNAL3] = &frv_cpuexternal[3],
|
||||
[IRQ_CPU_EXTERNAL4] = &frv_cpuexternal[4],
|
||||
[IRQ_CPU_EXTERNAL5] = &frv_cpuexternal[5],
|
||||
[IRQ_CPU_EXTERNAL6] = &frv_cpuexternal[6],
|
||||
[IRQ_CPU_EXTERNAL7] = &frv_cpuexternal[7],
|
||||
},
|
||||
};
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
* route the CPU's interrupt sources
|
||||
*/
|
||||
void __init route_cpu_irqs(void)
|
||||
{
|
||||
frv_irq_set_group(&frv_cpu_irqs);
|
||||
|
||||
__set_IITMR(0, 0x003f0000); /* DMA0-3, TIMER0-2 IRQ detect levels */
|
||||
__set_IITMR(1, 0x20000000); /* ERR0-1, UART0-1, DMA4-7 IRQ detect levels */
|
||||
|
||||
/* route UART and error interrupts */
|
||||
frv_irq_route(&frv_cpuuart[0], IRQ_UART0_LEVEL);
|
||||
frv_irq_route(&frv_cpuuart[1], IRQ_UART1_LEVEL);
|
||||
|
||||
set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL, IRQ_UART1_LEVEL, IRQ_UART0_LEVEL);
|
||||
|
||||
/* route DMA channel interrupts */
|
||||
frv_irq_route(&frv_cpudma[0], IRQ_DMA0_LEVEL);
|
||||
frv_irq_route(&frv_cpudma[1], IRQ_DMA1_LEVEL);
|
||||
frv_irq_route(&frv_cpudma[2], IRQ_DMA2_LEVEL);
|
||||
frv_irq_route(&frv_cpudma[3], IRQ_DMA3_LEVEL);
|
||||
frv_irq_route(&frv_cpudma[4], IRQ_DMA4_LEVEL);
|
||||
frv_irq_route(&frv_cpudma[5], IRQ_DMA5_LEVEL);
|
||||
frv_irq_route(&frv_cpudma[6], IRQ_DMA6_LEVEL);
|
||||
frv_irq_route(&frv_cpudma[7], IRQ_DMA7_LEVEL);
|
||||
|
||||
set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL, IRQ_DMA0_LEVEL);
|
||||
set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL, IRQ_DMA4_LEVEL);
|
||||
|
||||
/* route timer interrupts */
|
||||
frv_irq_route(&frv_cputimer[0], IRQ_TIMER0_LEVEL);
|
||||
frv_irq_route(&frv_cputimer[1], IRQ_TIMER1_LEVEL);
|
||||
frv_irq_route(&frv_cputimer[2], IRQ_TIMER2_LEVEL);
|
||||
|
||||
set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL);
|
||||
|
||||
/* route external interrupts */
|
||||
frv_irq_route(&frv_cpuexternal[0], IRQ_XIRQ0_LEVEL);
|
||||
frv_irq_route(&frv_cpuexternal[1], IRQ_XIRQ1_LEVEL);
|
||||
frv_irq_route(&frv_cpuexternal[2], IRQ_XIRQ2_LEVEL);
|
||||
frv_irq_route(&frv_cpuexternal[3], IRQ_XIRQ3_LEVEL);
|
||||
frv_irq_route(&frv_cpuexternal[4], IRQ_XIRQ4_LEVEL);
|
||||
frv_irq_route(&frv_cpuexternal[5], IRQ_XIRQ5_LEVEL);
|
||||
frv_irq_route(&frv_cpuexternal[6], IRQ_XIRQ6_LEVEL);
|
||||
frv_irq_route(&frv_cpuexternal[7], IRQ_XIRQ7_LEVEL);
|
||||
|
||||
set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL, IRQ_XIRQ4_LEVEL);
|
||||
set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL, IRQ_XIRQ0_LEVEL);
|
||||
|
||||
#if defined(CONFIG_MB93091_VDK)
|
||||
__set_TM1(0x55550000); /* XIRQ7-0 all active low */
|
||||
#elif defined(CONFIG_MB93093_PDK)
|
||||
__set_TM1(0x15550000); /* XIRQ7 active high, 6-0 all active low */
|
||||
#else
|
||||
#error dont know external IRQ trigger levels for this setup
|
||||
#endif
|
||||
|
||||
} /* end route_cpu_irqs() */
|
||||
+119
-643
File diff suppressed because it is too large
Load Diff
@@ -43,7 +43,6 @@
|
||||
#include <asm/mb-regs.h>
|
||||
#include <asm/mb93493-regs.h>
|
||||
#include <asm/gdb-stub.h>
|
||||
#include <asm/irq-routing.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
|
||||
@@ -26,7 +26,6 @@
|
||||
#include <asm/timer-regs.h>
|
||||
#include <asm/mb-regs.h>
|
||||
#include <asm/mb86943a.h>
|
||||
#include <asm/irq-routing.h>
|
||||
|
||||
#include <linux/timex.h>
|
||||
|
||||
|
||||
@@ -15,7 +15,6 @@
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/smp.h>
|
||||
#include <asm/irq-routing.h>
|
||||
|
||||
#include "pci-frv.h"
|
||||
|
||||
|
||||
+24
-30
@@ -14,36 +14,6 @@
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/irq-routing.h>
|
||||
|
||||
#define IRQ_BASE_CPU (NR_IRQ_ACTIONS_PER_GROUP * 0)
|
||||
|
||||
/* IRQ IDs presented to drivers */
|
||||
enum {
|
||||
IRQ_CPU__UNUSED = IRQ_BASE_CPU,
|
||||
IRQ_CPU_UART0,
|
||||
IRQ_CPU_UART1,
|
||||
IRQ_CPU_TIMER0,
|
||||
IRQ_CPU_TIMER1,
|
||||
IRQ_CPU_TIMER2,
|
||||
IRQ_CPU_DMA0,
|
||||
IRQ_CPU_DMA1,
|
||||
IRQ_CPU_DMA2,
|
||||
IRQ_CPU_DMA3,
|
||||
IRQ_CPU_DMA4,
|
||||
IRQ_CPU_DMA5,
|
||||
IRQ_CPU_DMA6,
|
||||
IRQ_CPU_DMA7,
|
||||
IRQ_CPU_EXTERNAL0,
|
||||
IRQ_CPU_EXTERNAL1,
|
||||
IRQ_CPU_EXTERNAL2,
|
||||
IRQ_CPU_EXTERNAL3,
|
||||
IRQ_CPU_EXTERNAL4,
|
||||
IRQ_CPU_EXTERNAL5,
|
||||
IRQ_CPU_EXTERNAL6,
|
||||
IRQ_CPU_EXTERNAL7,
|
||||
};
|
||||
|
||||
/* IRQ to level mappings */
|
||||
#define IRQ_GDBSTUB_LEVEL 15
|
||||
#define IRQ_UART_LEVEL 13
|
||||
@@ -82,6 +52,30 @@ enum {
|
||||
#define IRQ_XIRQ6_LEVEL 7
|
||||
#define IRQ_XIRQ7_LEVEL 8
|
||||
|
||||
/* IRQ IDs presented to drivers */
|
||||
#define IRQ_CPU__UNUSED IRQ_BASE_CPU
|
||||
#define IRQ_CPU_UART0 (IRQ_BASE_CPU + IRQ_UART0_LEVEL)
|
||||
#define IRQ_CPU_UART1 (IRQ_BASE_CPU + IRQ_UART1_LEVEL)
|
||||
#define IRQ_CPU_TIMER0 (IRQ_BASE_CPU + IRQ_TIMER0_LEVEL)
|
||||
#define IRQ_CPU_TIMER1 (IRQ_BASE_CPU + IRQ_TIMER1_LEVEL)
|
||||
#define IRQ_CPU_TIMER2 (IRQ_BASE_CPU + IRQ_TIMER2_LEVEL)
|
||||
#define IRQ_CPU_DMA0 (IRQ_BASE_CPU + IRQ_DMA0_LEVEL)
|
||||
#define IRQ_CPU_DMA1 (IRQ_BASE_CPU + IRQ_DMA1_LEVEL)
|
||||
#define IRQ_CPU_DMA2 (IRQ_BASE_CPU + IRQ_DMA2_LEVEL)
|
||||
#define IRQ_CPU_DMA3 (IRQ_BASE_CPU + IRQ_DMA3_LEVEL)
|
||||
#define IRQ_CPU_DMA4 (IRQ_BASE_CPU + IRQ_DMA4_LEVEL)
|
||||
#define IRQ_CPU_DMA5 (IRQ_BASE_CPU + IRQ_DMA5_LEVEL)
|
||||
#define IRQ_CPU_DMA6 (IRQ_BASE_CPU + IRQ_DMA6_LEVEL)
|
||||
#define IRQ_CPU_DMA7 (IRQ_BASE_CPU + IRQ_DMA7_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL0 (IRQ_BASE_CPU + IRQ_XIRQ0_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL1 (IRQ_BASE_CPU + IRQ_XIRQ1_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL2 (IRQ_BASE_CPU + IRQ_XIRQ2_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL3 (IRQ_BASE_CPU + IRQ_XIRQ3_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL4 (IRQ_BASE_CPU + IRQ_XIRQ4_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL5 (IRQ_BASE_CPU + IRQ_XIRQ5_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL6 (IRQ_BASE_CPU + IRQ_XIRQ6_LEVEL)
|
||||
#define IRQ_CPU_EXTERNAL7 (IRQ_BASE_CPU + IRQ_XIRQ7_LEVEL)
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_CPU_IRQS_H */
|
||||
|
||||
@@ -26,5 +26,10 @@ typedef struct {
|
||||
#error SMP not available on FR-V
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
extern atomic_t irq_err_count;
|
||||
static inline void ack_bad_irq(int irq)
|
||||
{
|
||||
atomic_inc(&irq_err_count);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,70 +0,0 @@
|
||||
/* irq-routing.h: multiplexed IRQ routing
|
||||
*
|
||||
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
|
||||
* Written by David Howells (dhowells@redhat.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_IRQ_ROUTING_H
|
||||
#define _ASM_IRQ_ROUTING_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
struct irq_source;
|
||||
struct irq_level;
|
||||
|
||||
/*
|
||||
* IRQ action distribution sets
|
||||
*/
|
||||
struct irq_group {
|
||||
int first_irq; /* first IRQ distributed here */
|
||||
void (*control)(struct irq_group *group, int index, int on);
|
||||
|
||||
struct irqaction *actions[NR_IRQ_ACTIONS_PER_GROUP]; /* IRQ action chains */
|
||||
struct irq_source *sources[NR_IRQ_ACTIONS_PER_GROUP]; /* IRQ sources */
|
||||
int disable_cnt[NR_IRQ_ACTIONS_PER_GROUP]; /* disable counts */
|
||||
};
|
||||
|
||||
/*
|
||||
* IRQ source manager
|
||||
*/
|
||||
struct irq_source {
|
||||
struct irq_source *next;
|
||||
struct irq_level *level;
|
||||
const char *muxname;
|
||||
volatile void __iomem *muxdata;
|
||||
unsigned long irqmask;
|
||||
|
||||
void (*doirq)(struct irq_source *source);
|
||||
};
|
||||
|
||||
/*
|
||||
* IRQ level management (per CPU IRQ priority / entry vector)
|
||||
*/
|
||||
struct irq_level {
|
||||
int usage;
|
||||
int disable_count;
|
||||
unsigned long flags; /* current IRQF_DISABLED and IRQF_SHARED settings */
|
||||
spinlock_t lock;
|
||||
struct irq_source *sources;
|
||||
};
|
||||
|
||||
extern struct irq_level frv_irq_levels[16];
|
||||
extern struct irq_group *irq_groups[NR_IRQ_GROUPS];
|
||||
|
||||
extern void frv_irq_route(struct irq_source *source, int irqlevel);
|
||||
extern void frv_irq_route_external(struct irq_source *source, int irq);
|
||||
extern void frv_irq_set_group(struct irq_group *group);
|
||||
extern void distribute_irqs(struct irq_group *group, unsigned long irqmask);
|
||||
extern void route_cpu_irqs(void);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_IRQ_ROUTING_H */
|
||||
+8
-18
@@ -1,6 +1,6 @@
|
||||
/* irq.h: FRV IRQ definitions
|
||||
*
|
||||
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
|
||||
* Written by David Howells (dhowells@redhat.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
@@ -12,32 +12,22 @@
|
||||
#ifndef _ASM_IRQ_H_
|
||||
#define _ASM_IRQ_H_
|
||||
|
||||
|
||||
/*
|
||||
* the system has an on-CPU PIC and another PIC on the FPGA and other PICs on other peripherals,
|
||||
* so we do some routing in irq-routing.[ch] to reduce the number of false-positives seen by
|
||||
* drivers
|
||||
*/
|
||||
|
||||
/* this number is used when no interrupt has been assigned */
|
||||
#define NO_IRQ (-1)
|
||||
|
||||
#define NR_IRQ_LOG2_ACTIONS_PER_GROUP 5
|
||||
#define NR_IRQ_ACTIONS_PER_GROUP (1 << NR_IRQ_LOG2_ACTIONS_PER_GROUP)
|
||||
#define NR_IRQ_GROUPS 4
|
||||
#define NR_IRQS (NR_IRQ_ACTIONS_PER_GROUP * NR_IRQ_GROUPS)
|
||||
#define NR_IRQS 48
|
||||
#define IRQ_BASE_CPU (0 * 16)
|
||||
#define IRQ_BASE_FPGA (1 * 16)
|
||||
#define IRQ_BASE_MB93493 (2 * 16)
|
||||
|
||||
/* probe returns a 32-bit IRQ mask:-/ */
|
||||
#define MIN_PROBE_IRQ (NR_IRQS - 32)
|
||||
#define MIN_PROBE_IRQ (NR_IRQS - 32)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
static inline int irq_canonicalize(int irq)
|
||||
{
|
||||
return irq;
|
||||
}
|
||||
|
||||
extern void disable_irq_nosync(unsigned int irq);
|
||||
extern void disable_irq(unsigned int irq);
|
||||
extern void enable_irq(unsigned int irq);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_IRQ_H_ */
|
||||
|
||||
@@ -12,12 +12,10 @@
|
||||
#ifndef _ASM_MB93091_FPGA_IRQS_H
|
||||
#define _ASM_MB93091_FPGA_IRQS_H
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/irq-routing.h>
|
||||
|
||||
#define IRQ_BASE_FPGA (NR_IRQ_ACTIONS_PER_GROUP * 1)
|
||||
|
||||
/* IRQ IDs presented to drivers */
|
||||
enum {
|
||||
IRQ_FPGA__UNUSED = IRQ_BASE_FPGA,
|
||||
|
||||
@@ -12,12 +12,10 @@
|
||||
#ifndef _ASM_MB93093_FPGA_IRQS_H
|
||||
#define _ASM_MB93093_FPGA_IRQS_H
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/irq-routing.h>
|
||||
|
||||
#define IRQ_BASE_FPGA (NR_IRQ_ACTIONS_PER_GROUP * 1)
|
||||
|
||||
/* IRQ IDs presented to drivers */
|
||||
enum {
|
||||
IRQ_FPGA_PUSH_BUTTON_SW1_5 = IRQ_BASE_FPGA + 8,
|
||||
|
||||
@@ -12,12 +12,10 @@
|
||||
#ifndef _ASM_MB93493_IRQS_H
|
||||
#define _ASM_MB93493_IRQS_H
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/irq-routing.h>
|
||||
|
||||
#define IRQ_BASE_MB93493 (NR_IRQ_ACTIONS_PER_GROUP * 2)
|
||||
|
||||
/* IRQ IDs presented to drivers */
|
||||
enum {
|
||||
IRQ_MB93493_VDC = IRQ_BASE_MB93493 + 0,
|
||||
|
||||
@@ -15,6 +15,7 @@
|
||||
#include <asm/mb-regs.h>
|
||||
#include <asm/mb93493-irqs.h>
|
||||
|
||||
#define __addr_MB93493(X) ((volatile unsigned long *)(__region_CS3 + (X)))
|
||||
#define __get_MB93493(X) ({ *(volatile unsigned long *)(__region_CS3 + (X)); })
|
||||
|
||||
#define __set_MB93493(X,V) \
|
||||
@@ -26,6 +27,7 @@ do { \
|
||||
#define __set_MB93493_STSR(X,V) __set_MB93493(0x3c0 + (X) * 4, (V))
|
||||
#define MB93493_STSR_EN
|
||||
|
||||
#define __addr_MB93493_IQSR(X) __addr_MB93493(0x3d0 + (X) * 4)
|
||||
#define __get_MB93493_IQSR(X) __get_MB93493(0x3d0 + (X) * 4)
|
||||
#define __set_MB93493_IQSR(X,V) __set_MB93493(0x3d0 + (X) * 4, (V))
|
||||
|
||||
|
||||
Reference in New Issue
Block a user