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Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux into next
Pull clock framework updates from Mike Turquette:
"The clock framework changes for 3.16 are pretty typical: mostly clock
driver additions and fixes. There are additions to the clock core
code for some of the basic types (e.g. the common divider type has
some fixes and featured added to it).
One minor annoyance is a last-minute dependency that wasn't handled
quite right. Commit ba0fae3b06 ("clk: berlin: add core clock driver
for BG2/BG2CD") in this pull request depends on
include/dt-bindings/clock/berlin2.h, which is already in your tree via
the arm-soc pull request. Building for the berlin platform will break
when the clk tree is built on it's own, but merged into your master
branch everything should be fine"
* tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux: (75 commits)
mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
clk: export __clk_round_rate for providers
clk: versatile: free icst on error return
clk: qcom: Return error pointers for unimplemented clocks
clk: qcom: Support msm8974pro global clock control hardware
clk: qcom: Properly support display clocks on msm8974
clk: qcom: Support display RCG clocks
clk: qcom: Return highest rate when round_rate() exceeds plan
clk: qcom: Fix mmcc-8974's PLL configurations
clk: qcom: Fix clk_rcg2_is_enabled() check
clk: berlin: add core clock driver for BG2Q
clk: berlin: add core clock driver for BG2/BG2CD
clk: berlin: add driver for BG2x complex divider cells
clk: berlin: add driver for BG2x simple PLLs
clk: berlin: add driver for BG2x audio/video PLL
clk: st: Terminate of match table
clk/exynos4: Fix compilation warning
ARM: shmobile: r8a7779: Add clock index macros for DT sources
clk: divider: Fix overflow in clk_divider_bestdiv
clk: u300: Terminate of match table
...
This commit is contained in:
Linus Torvalds
+11
-5
@@ -68,21 +68,27 @@ the operations defined in clk.h:
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||||
int (*is_enabled)(struct clk_hw *hw);
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unsigned long (*recalc_rate)(struct clk_hw *hw,
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unsigned long parent_rate);
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long (*round_rate)(struct clk_hw *hw, unsigned long,
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unsigned long *);
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long (*round_rate)(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate);
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long (*determine_rate)(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *best_parent_rate,
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struct clk **best_parent_clk);
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int (*set_parent)(struct clk_hw *hw, u8 index);
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u8 (*get_parent)(struct clk_hw *hw);
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int (*set_rate)(struct clk_hw *hw, unsigned long);
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int (*set_rate)(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate);
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int (*set_rate_and_parent)(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate, u8 index);
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unsigned long parent_rate,
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u8 index);
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unsigned long (*recalc_accuracy)(struct clk_hw *hw,
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unsigned long parent_accuracy);
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unsigned long parent_accuracy);
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void (*init)(struct clk_hw *hw);
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int (*debug_init)(struct clk_hw *hw,
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struct dentry *dentry);
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};
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Part 3 - hardware clk implementations
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@@ -10,12 +10,12 @@ This binding uses the common clock binding:
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Required properties:
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- compatible
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Shall have one of the following values:
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- "brcm,bcm11351-root-ccu"
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- "brcm,bcm11351-aon-ccu"
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- "brcm,bcm11351-hub-ccu"
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- "brcm,bcm11351-master-ccu"
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- "brcm,bcm11351-slave-ccu"
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Shall have a value of the form "brcm,<model>-<which>-ccu",
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where <model> is a Broadcom SoC model number and <which> is
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the name of a defined CCU. For example:
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"brcm,bcm11351-root-ccu"
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The compatible strings used for each supported SoC family
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are defined below.
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- reg
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Shall define the base and range of the address space
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containing clock control registers
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@@ -26,12 +26,48 @@ Required properties:
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Shall be an ordered list of strings defining the names of
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the clocks provided by the CCU.
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Device tree example:
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BCM281XX family SoCs use Kona CCUs. The following table defines
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the set of CCUs and clock specifiers for BCM281XX clocks. When
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a clock consumer references a clocks, its symbolic specifier
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(rather than its numeric index value) should be used. These
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specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
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slave_ccu: slave_ccu {
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compatible = "brcm,bcm11351-slave-ccu";
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reg = <0x3e011000 0x0f00>;
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#clock-cells = <1>;
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clock-output-names = "uartb",
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"uartb2",
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"uartb3",
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"uartb4";
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};
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ref_crystal_clk: ref_crystal {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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};
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uart@3e002000 {
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compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e002000 0x1000>;
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clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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BCM281XX family
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---------------
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CCU compatible string values for SoCs in the BCM281XX family are:
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"brcm,bcm11351-root-ccu"
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"brcm,bcm11351-aon-ccu"
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"brcm,bcm11351-hub-ccu"
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"brcm,bcm11351-master-ccu"
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"brcm,bcm11351-slave-ccu"
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The following table defines the set of CCUs and clock specifiers for
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BCM281XX family clocks. When a clock consumer references a clocks,
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its symbolic specifier (rather than its numeric index value) should
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be used. These specifiers are defined in:
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"include/dt-bindings/clock/bcm281xx.h"
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CCU Clock Type Index Specifier
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--- ----- ---- ----- ---------
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@@ -64,30 +100,40 @@ specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
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slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
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Device tree example:
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BCM21664 family
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---------------
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CCU compatible string values for SoCs in the BCM21664 family are:
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"brcm,bcm21664-root-ccu"
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"brcm,bcm21664-aon-ccu"
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"brcm,bcm21664-master-ccu"
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"brcm,bcm21664-slave-ccu"
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slave_ccu: slave_ccu {
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compatible = "brcm,bcm11351-slave-ccu";
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reg = <0x3e011000 0x0f00>;
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#clock-cells = <1>;
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clock-output-names = "uartb",
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"uartb2",
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"uartb3",
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"uartb4";
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};
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The following table defines the set of CCUs and clock specifiers for
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BCM21664 family clocks. When a clock consumer references a clocks,
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its symbolic specifier (rather than its numeric index value) should
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be used. These specifiers are defined in:
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"include/dt-bindings/clock/bcm21664.h"
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ref_crystal_clk: ref_crystal {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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};
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CCU Clock Type Index Specifier
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--- ----- ---- ----- ---------
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root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M
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uart@3e002000 {
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compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e002000 0x1000>;
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clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
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master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1
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master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2
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master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3
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master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4
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master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP
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master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP
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master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP
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master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP
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slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB
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slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2
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slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3
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slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4
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slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1
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slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2
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slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3
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slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4
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@@ -44,10 +44,9 @@ For example:
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clocks by index. The names should reflect the clock output signal
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names for the device.
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clock-indices: If the identifyng number for the clocks in the node
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is not linear from zero, then the this mapping allows
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the mapping of identifiers into the clock-output-names
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array.
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clock-indices: If the identifying number for the clocks in the node
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is not linear from zero, then this allows the mapping of
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identifiers into the clock-output-names array.
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For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
|
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@@ -58,7 +57,7 @@ For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
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clock-output-names = "clka", "clkb";
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}
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This ensures we do not have any empty nodes in clock-output-names
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This ensures we do not have any empty strings in clock-output-names
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==Clock consumers==
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@@ -12,7 +12,6 @@ Required properties:
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Optional properties:
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- clock-accuracy : accuracy of clock in ppb (parts per billion).
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Should be a single cell.
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- gpios : From common gpio binding; gpio connection to clock enable pin.
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- clock-output-names : From common clock binding.
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Example:
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@@ -0,0 +1,31 @@
|
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* Hisilicon Hix5hd2 Clock Controller
|
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|
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The hix5hd2 clock controller generates and supplies clock to various
|
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controllers within the hix5hd2 SoC.
|
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|
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Required Properties:
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- compatible: should be "hisilicon,hix5hd2-clock"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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Each clock is assigned an identifier and client nodes use this identifier
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to specify the clock which they consume.
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All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
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|
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Examples:
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clock: clock@f8a22000 {
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compatible = "hisilicon,hix5hd2-clock";
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reg = <0xf8a22000 0x1000>;
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#clock-cells = <1>;
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};
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uart0: uart@f8b00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8b00000 0x1000>;
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interrupts = <0 49 4>;
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clocks = <&clock HIX5HD2_FIXED_83M>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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@@ -0,0 +1,29 @@
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AXM5516 clock driver bindings
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-----------------------------
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Required properties :
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- compatible : shall contain "lsi,axm5516-clks"
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- reg : shall contain base register location and length
|
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- #clock-cells : shall contain 1
|
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|
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The consumer specifies the desired clock by having the clock ID in its "clocks"
|
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phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
|
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supported clock IDs.
|
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|
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Example:
|
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|
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clks: clock-controller@2010020000 {
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compatible = "lsi,axm5516-clks";
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#clock-cells = <1>;
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reg = <0x20 0x10020000 0 0x20000>;
|
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};
|
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|
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serial0: uart@2010080000 {
|
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compatible = "arm,pl011", "arm,primecell";
|
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reg = <0x20 0x10080000 0 0x1000>;
|
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks AXXIA_CLK_PER>;
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clock-names = "apb_pclk";
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};
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};
|
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|
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@@ -29,6 +29,11 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
|
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2 = l2clk (L2 Cache clock derived from CPU0 clock)
|
||||
3 = ddrclk (DDR controller clock derived from CPU0 clock)
|
||||
|
||||
The following is a list of provided IDs and clock names on Orion5x:
|
||||
0 = tclk (Internal Bus clock)
|
||||
1 = cpuclk (CPU0 clock)
|
||||
2 = ddrclk (DDR controller clock derived from CPU0 clock)
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
|
||||
@@ -38,6 +43,9 @@ Required properties:
|
||||
"marvell,dove-core-clock" - for Dove SoC core clocks
|
||||
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
|
||||
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
|
||||
"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
|
||||
"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
|
||||
"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
|
||||
- reg : shall be the register address of the Sample-At-Reset (SAR) register
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
|
||||
@@ -4,9 +4,12 @@ Qualcomm Global Clock & Reset Controller Binding
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
|
||||
"qcom,gcc-apq8064"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,gcc-msm8960"
|
||||
"qcom,gcc-msm8974"
|
||||
"qcom,gcc-msm8974pro"
|
||||
"qcom,gcc-msm8974pro-ac"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
@@ -11,6 +11,7 @@ Required Properties:
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
|
||||
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
|
||||
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
|
||||
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
|
||||
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
|
||||
|
||||
@@ -0,0 +1,41 @@
|
||||
These bindings should be considered EXPERIMENTAL for now.
|
||||
|
||||
* Renesas R8A7740 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
|
||||
and several fixed ratio and variable ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7740-cpg-clocks"
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the three parent clocks
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are
|
||||
"system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
|
||||
"m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
|
||||
|
||||
- renesas,mode: board-specific settings of the MD_CK* bits
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7740-cpg-clocks";
|
||||
reg = <0xe6150000 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "system", "pllc0", "pllc1",
|
||||
"pllc2", "r",
|
||||
"usb24s",
|
||||
"i", "zg", "b", "m1", "hp",
|
||||
"hpp", "usbp", "s", "zb", "m3",
|
||||
"cp";
|
||||
};
|
||||
|
||||
&cpg_clocks {
|
||||
renesas,mode = <0x05>;
|
||||
};
|
||||
@@ -0,0 +1,27 @@
|
||||
* Renesas R8A7779 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7779. It includes one PLL and
|
||||
several fixed ratio dividers
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7779-cpg-clocks"
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clock
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "plla",
|
||||
"z", "zs", "s", "s1", "p", "b", "out".
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@ffc80000 {
|
||||
compatible = "renesas,r8a7779-cpg-clocks";
|
||||
reg = <0 0xffc80000 0 0x30>;
|
||||
clocks = <&extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
|
||||
"b", "out";
|
||||
};
|
||||
@@ -0,0 +1,43 @@
|
||||
* Allwinner sunxi MMC controller
|
||||
|
||||
The highspeed MMC host controller on Allwinner SoCs provides an interface
|
||||
for MMC, SD and SDIO types of memory cards.
|
||||
|
||||
Supported maximum speeds are the ones of the eMMC standard 4.5 as well
|
||||
as the speed of SD standard 3.0.
|
||||
Absolute maximum transfer rate is 200MB/s
|
||||
|
||||
Required properties:
|
||||
- compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc"
|
||||
- reg : mmc controller base registers
|
||||
- clocks : a list with 2 phandle + clock specifier pairs
|
||||
- clock-names : must contain "ahb" and "mmc"
|
||||
- interrupts : mmc controller interrupt
|
||||
|
||||
Optional properties:
|
||||
- resets : phandle + reset specifier pair
|
||||
- reset-names : must contain "ahb"
|
||||
- for cd, bus-width and additional generic mmc parameters
|
||||
please refer to mmc.txt within this directory
|
||||
|
||||
Examples:
|
||||
- Within .dtsi:
|
||||
mmc0: mmc@01c0f000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c0f000 0x1000>;
|
||||
clocks = <&ahb_gates 8>, <&mmc0_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
interrupts = <0 32 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- Within dts:
|
||||
mmc0: mmc@01c0f000 {
|
||||
pinctrl-names = "default", "default";
|
||||
pinctrl-0 = <&mmc0_pins_a>;
|
||||
pinctrl-1 = <&mmc0_cd_pin_reference_design>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pio 7 1 0>; /* PH1 */
|
||||
cd-inverted;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -815,6 +815,11 @@ F: arch/arm/boot/dts/at91*.dtsi
|
||||
F: arch/arm/boot/dts/sama*.dts
|
||||
F: arch/arm/boot/dts/sama*.dtsi
|
||||
|
||||
ARM/ATMEL AT91 Clock Support
|
||||
M: Boris Brezillon <boris.brezillon@free-electrons.com>
|
||||
S: Maintained
|
||||
F: drivers/clk/at91
|
||||
|
||||
ARM/CALXEDA HIGHBANK ARCHITECTURE
|
||||
M: Rob Herring <robh@kernel.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
||||
+130
-84
@@ -14,6 +14,8 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#include "dt-bindings/clock/bcm21664.h"
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
@@ -43,7 +45,7 @@
|
||||
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e000000 0x118>;
|
||||
clocks = <&uartb_clk>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
@@ -53,7 +55,7 @@
|
||||
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e001000 0x118>;
|
||||
clocks = <&uartb2_clk>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
@@ -63,7 +65,7 @@
|
||||
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e002000 0x118>;
|
||||
clocks = <&uartb3_clk>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
@@ -85,7 +87,7 @@
|
||||
compatible = "brcm,kona-timer";
|
||||
reg = <0x35006000 0x1c>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&hub_timer_clk>;
|
||||
clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
|
||||
};
|
||||
|
||||
gpio: gpio@35003000 {
|
||||
@@ -106,7 +108,7 @@
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f180000 0x801c>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sdio1_clk>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -114,7 +116,7 @@
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f190000 0x801c>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sdio2_clk>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -122,7 +124,7 @@
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f1a0000 0x801c>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sdio3_clk>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -130,7 +132,7 @@
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f1b0000 0x801c>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sdio4_clk>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -140,7 +142,7 @@
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&bsc1_clk>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -150,7 +152,7 @@
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&bsc2_clk>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -160,7 +162,7 @@
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&bsc3_clk>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -170,105 +172,149 @@
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&bsc4_clk>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clocks {
|
||||
bsc1_clk: bsc1 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
bsc2_clk: bsc2 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
/*
|
||||
* Fixed clocks are defined before CCUs whose
|
||||
* clocks may depend on them.
|
||||
*/
|
||||
|
||||
bsc3_clk: bsc3 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
ref_32k_clk: ref_32k {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
bsc4_clk: bsc4 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
pmu_bsc_clk: pmu_bsc {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
hub_timer_clk: hub_timer {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
pwm_clk: pwm {
|
||||
bbl_32k_clk: bbl_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ref_13m_clk: ref_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
var_13m_clk: var_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
dft_19_5m_clk: dft_19_5m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19500000>;
|
||||
};
|
||||
|
||||
ref_crystal_clk: ref_crystal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sdio1_clk: sdio1 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
ref_52m_clk: ref_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
sdio2_clk: sdio2 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
var_52m_clk: var_52m {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sdio3_clk: sdio3 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sdio4_clk: sdio4 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
tmon_1m_clk: tmon_1m {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
uartb_clk: uartb {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
uartb2_clk: uartb2 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
uartb3_clk: uartb3 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
usb_otg_ahb_clk: usb_otg_ahb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
ref_96m_clk: ref_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
var_96m_clk: var_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
ref_104m_clk: ref_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
var_104m_clk: var_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
ref_156m_clk: ref_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
var_156m_clk: var_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
root_ccu: root_ccu {
|
||||
compatible = BCM21664_DT_ROOT_CCU_COMPAT;
|
||||
reg = <0x35001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "frac_1m";
|
||||
};
|
||||
|
||||
aon_ccu: aon_ccu {
|
||||
compatible = BCM21664_DT_AON_CCU_COMPAT;
|
||||
reg = <0x35002000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "hub_timer";
|
||||
};
|
||||
|
||||
master_ccu: master_ccu {
|
||||
compatible = BCM21664_DT_MASTER_CCU_COMPAT;
|
||||
reg = <0x3f001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "sdio1",
|
||||
"sdio2",
|
||||
"sdio3",
|
||||
"sdio4",
|
||||
"sdio1_sleep",
|
||||
"sdio2_sleep",
|
||||
"sdio3_sleep",
|
||||
"sdio4_sleep";
|
||||
};
|
||||
|
||||
slave_ccu: slave_ccu {
|
||||
compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
|
||||
reg = <0x3e011000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "uartb",
|
||||
"uartb2",
|
||||
"uartb3",
|
||||
"bsc1",
|
||||
"bsc2",
|
||||
"bsc3",
|
||||
"bsc4";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
+4
-4
@@ -58,12 +58,12 @@ config COMMON_CLK_SI570
|
||||
clock generators.
|
||||
|
||||
config COMMON_CLK_S2MPS11
|
||||
tristate "Clock driver for S2MPS11/S5M8767 MFD"
|
||||
tristate "Clock driver for S2MPS1X/S5M8767 MFD"
|
||||
depends on MFD_SEC_CORE
|
||||
---help---
|
||||
This driver supports S2MPS11/S5M8767 crystal oscillator clock. These
|
||||
multi-function devices have 3 fixed-rate oscillators, clocked at
|
||||
32KHz each.
|
||||
This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
|
||||
clock. These multi-function devices have two (S2MPS14) or three
|
||||
(S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
|
||||
|
||||
config CLK_TWL6040
|
||||
tristate "External McPDM functional clock from twl6040"
|
||||
|
||||
@@ -13,6 +13,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
|
||||
# hardware specific clock types
|
||||
# please keep this section sorted lexicographically by file/directory path name
|
||||
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
|
||||
obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
|
||||
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
|
||||
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
|
||||
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
|
||||
@@ -32,8 +33,10 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
|
||||
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
|
||||
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
|
||||
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
|
||||
obj-$(CONFIG_ARCH_BERLIN) += berlin/
|
||||
obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
|
||||
obj-$(CONFIG_ARCH_HIP04) += hisilicon/
|
||||
obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
|
||||
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
|
||||
ifeq ($(CONFIG_COMMON_CLK), y)
|
||||
obj-$(CONFIG_ARCH_MMP) += mmp/
|
||||
|
||||
@@ -6,4 +6,4 @@ config CLK_BCM_KONA
|
||||
help
|
||||
Enable common clock framework support for Broadcom SoCs
|
||||
using "Kona" style clock control units, including those
|
||||
in the BCM281xx family.
|
||||
in the BCM281xx and BCM21664 families.
|
||||
|
||||
@@ -1,3 +1,4 @@
|
||||
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
|
||||
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
|
||||
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
|
||||
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
|
||||
|
||||
@@ -0,0 +1,290 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Broadcom Corporation
|
||||
* Copyright 2014 Linaro Limited
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "clk-kona.h"
|
||||
#include "dt-bindings/clock/bcm21664.h"
|
||||
|
||||
#define BCM21664_CCU_COMMON(_name, _capname) \
|
||||
KONA_CCU_COMMON(BCM21664, _name, _capname)
|
||||
|
||||
/* Root CCU */
|
||||
|
||||
static struct peri_clk_data frac_1m_data = {
|
||||
.gate = HW_SW_GATE(0x214, 16, 0, 1),
|
||||
.clocks = CLOCKS("ref_crystal"),
|
||||
};
|
||||
|
||||
static struct ccu_data root_ccu_data = {
|
||||
BCM21664_CCU_COMMON(root, ROOT),
|
||||
/* no policy control */
|
||||
.kona_clks = {
|
||||
[BCM21664_ROOT_CCU_FRAC_1M] =
|
||||
KONA_CLK(root, frac_1m, peri),
|
||||
[BCM21664_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
||||
},
|
||||
};
|
||||
|
||||
/* AON CCU */
|
||||
|
||||
static struct peri_clk_data hub_timer_data = {
|
||||
.gate = HW_SW_GATE(0x0414, 16, 0, 1),
|
||||
.hyst = HYST(0x0414, 8, 9),
|
||||
.clocks = CLOCKS("bbl_32k",
|
||||
"frac_1m",
|
||||
"dft_19_5m"),
|
||||
.sel = SELECTOR(0x0a10, 0, 2),
|
||||
.trig = TRIGGER(0x0a40, 4),
|
||||
};
|
||||
|
||||
static struct ccu_data aon_ccu_data = {
|
||||
BCM21664_CCU_COMMON(aon, AON),
|
||||
.policy = {
|
||||
.enable = CCU_LVM_EN(0x0034, 0),
|
||||
.control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
|
||||
},
|
||||
.kona_clks = {
|
||||
[BCM21664_AON_CCU_HUB_TIMER] =
|
||||
KONA_CLK(aon, hub_timer, peri),
|
||||
[BCM21664_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
||||
},
|
||||
};
|
||||
|
||||
/* Master CCU */
|
||||
|
||||
static struct peri_clk_data sdio1_data = {
|
||||
.gate = HW_SW_GATE(0x0358, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_52m",
|
||||
"ref_52m",
|
||||
"var_96m",
|
||||
"ref_96m"),
|
||||
.sel = SELECTOR(0x0a28, 0, 3),
|
||||
.div = DIVIDER(0x0a28, 4, 14),
|
||||
.trig = TRIGGER(0x0afc, 9),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio2_data = {
|
||||
.gate = HW_SW_GATE(0x035c, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_52m",
|
||||
"ref_52m",
|
||||
"var_96m",
|
||||
"ref_96m"),
|
||||
.sel = SELECTOR(0x0a2c, 0, 3),
|
||||
.div = DIVIDER(0x0a2c, 4, 14),
|
||||
.trig = TRIGGER(0x0afc, 10),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio3_data = {
|
||||
.gate = HW_SW_GATE(0x0364, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_52m",
|
||||
"ref_52m",
|
||||
"var_96m",
|
||||
"ref_96m"),
|
||||
.sel = SELECTOR(0x0a34, 0, 3),
|
||||
.div = DIVIDER(0x0a34, 4, 14),
|
||||
.trig = TRIGGER(0x0afc, 12),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio4_data = {
|
||||
.gate = HW_SW_GATE(0x0360, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_52m",
|
||||
"ref_52m",
|
||||
"var_96m",
|
||||
"ref_96m"),
|
||||
.sel = SELECTOR(0x0a30, 0, 3),
|
||||
.div = DIVIDER(0x0a30, 4, 14),
|
||||
.trig = TRIGGER(0x0afc, 11),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio1_sleep_data = {
|
||||
.clocks = CLOCKS("ref_32k"), /* Verify */
|
||||
.gate = HW_SW_GATE(0x0358, 18, 2, 3),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio2_sleep_data = {
|
||||
.clocks = CLOCKS("ref_32k"), /* Verify */
|
||||
.gate = HW_SW_GATE(0x035c, 18, 2, 3),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio3_sleep_data = {
|
||||
.clocks = CLOCKS("ref_32k"), /* Verify */
|
||||
.gate = HW_SW_GATE(0x0364, 18, 2, 3),
|
||||
};
|
||||
|
||||
static struct peri_clk_data sdio4_sleep_data = {
|
||||
.clocks = CLOCKS("ref_32k"), /* Verify */
|
||||
.gate = HW_SW_GATE(0x0360, 18, 2, 3),
|
||||
};
|
||||
|
||||
static struct ccu_data master_ccu_data = {
|
||||
BCM21664_CCU_COMMON(master, MASTER),
|
||||
.policy = {
|
||||
.enable = CCU_LVM_EN(0x0034, 0),
|
||||
.control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
|
||||
},
|
||||
.kona_clks = {
|
||||
[BCM21664_MASTER_CCU_SDIO1] =
|
||||
KONA_CLK(master, sdio1, peri),
|
||||
[BCM21664_MASTER_CCU_SDIO2] =
|
||||
KONA_CLK(master, sdio2, peri),
|
||||
[BCM21664_MASTER_CCU_SDIO3] =
|
||||
KONA_CLK(master, sdio3, peri),
|
||||
[BCM21664_MASTER_CCU_SDIO4] =
|
||||
KONA_CLK(master, sdio4, peri),
|
||||
[BCM21664_MASTER_CCU_SDIO1_SLEEP] =
|
||||
KONA_CLK(master, sdio1_sleep, peri),
|
||||
[BCM21664_MASTER_CCU_SDIO2_SLEEP] =
|
||||
KONA_CLK(master, sdio2_sleep, peri),
|
||||
[BCM21664_MASTER_CCU_SDIO3_SLEEP] =
|
||||
KONA_CLK(master, sdio3_sleep, peri),
|
||||
[BCM21664_MASTER_CCU_SDIO4_SLEEP] =
|
||||
KONA_CLK(master, sdio4_sleep, peri),
|
||||
[BCM21664_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
||||
},
|
||||
};
|
||||
|
||||
/* Slave CCU */
|
||||
|
||||
static struct peri_clk_data uartb_data = {
|
||||
.gate = HW_SW_GATE(0x0400, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_156m",
|
||||
"ref_156m"),
|
||||
.sel = SELECTOR(0x0a10, 0, 2),
|
||||
.div = FRAC_DIVIDER(0x0a10, 4, 12, 8),
|
||||
.trig = TRIGGER(0x0afc, 2),
|
||||
};
|
||||
|
||||
static struct peri_clk_data uartb2_data = {
|
||||
.gate = HW_SW_GATE(0x0404, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_156m",
|
||||
"ref_156m"),
|
||||
.sel = SELECTOR(0x0a14, 0, 2),
|
||||
.div = FRAC_DIVIDER(0x0a14, 4, 12, 8),
|
||||
.trig = TRIGGER(0x0afc, 3),
|
||||
};
|
||||
|
||||
static struct peri_clk_data uartb3_data = {
|
||||
.gate = HW_SW_GATE(0x0408, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_156m",
|
||||
"ref_156m"),
|
||||
.sel = SELECTOR(0x0a18, 0, 2),
|
||||
.div = FRAC_DIVIDER(0x0a18, 4, 12, 8),
|
||||
.trig = TRIGGER(0x0afc, 4),
|
||||
};
|
||||
|
||||
static struct peri_clk_data bsc1_data = {
|
||||
.gate = HW_SW_GATE(0x0458, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_104m",
|
||||
"ref_104m",
|
||||
"var_13m",
|
||||
"ref_13m"),
|
||||
.sel = SELECTOR(0x0a64, 0, 3),
|
||||
.trig = TRIGGER(0x0afc, 23),
|
||||
};
|
||||
|
||||
static struct peri_clk_data bsc2_data = {
|
||||
.gate = HW_SW_GATE(0x045c, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_104m",
|
||||
"ref_104m",
|
||||
"var_13m",
|
||||
"ref_13m"),
|
||||
.sel = SELECTOR(0x0a68, 0, 3),
|
||||
.trig = TRIGGER(0x0afc, 24),
|
||||
};
|
||||
|
||||
static struct peri_clk_data bsc3_data = {
|
||||
.gate = HW_SW_GATE(0x0470, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_104m",
|
||||
"ref_104m",
|
||||
"var_13m",
|
||||
"ref_13m"),
|
||||
.sel = SELECTOR(0x0a7c, 0, 3),
|
||||
.trig = TRIGGER(0x0afc, 18),
|
||||
};
|
||||
|
||||
static struct peri_clk_data bsc4_data = {
|
||||
.gate = HW_SW_GATE(0x0474, 18, 2, 3),
|
||||
.clocks = CLOCKS("ref_crystal",
|
||||
"var_104m",
|
||||
"ref_104m",
|
||||
"var_13m",
|
||||
"ref_13m"),
|
||||
.sel = SELECTOR(0x0a80, 0, 3),
|
||||
.trig = TRIGGER(0x0afc, 19),
|
||||
};
|
||||
|
||||
static struct ccu_data slave_ccu_data = {
|
||||
BCM21664_CCU_COMMON(slave, SLAVE),
|
||||
.policy = {
|
||||
.enable = CCU_LVM_EN(0x0034, 0),
|
||||
.control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
|
||||
},
|
||||
.kona_clks = {
|
||||
[BCM21664_SLAVE_CCU_UARTB] =
|
||||
KONA_CLK(slave, uartb, peri),
|
||||
[BCM21664_SLAVE_CCU_UARTB2] =
|
||||
KONA_CLK(slave, uartb2, peri),
|
||||
[BCM21664_SLAVE_CCU_UARTB3] =
|
||||
KONA_CLK(slave, uartb3, peri),
|
||||
[BCM21664_SLAVE_CCU_BSC1] =
|
||||
KONA_CLK(slave, bsc1, peri),
|
||||
[BCM21664_SLAVE_CCU_BSC2] =
|
||||
KONA_CLK(slave, bsc2, peri),
|
||||
[BCM21664_SLAVE_CCU_BSC3] =
|
||||
KONA_CLK(slave, bsc3, peri),
|
||||
[BCM21664_SLAVE_CCU_BSC4] =
|
||||
KONA_CLK(slave, bsc4, peri),
|
||||
[BCM21664_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
||||
},
|
||||
};
|
||||
|
||||
/* Device tree match table callback functions */
|
||||
|
||||
static void __init kona_dt_root_ccu_setup(struct device_node *node)
|
||||
{
|
||||
kona_dt_ccu_setup(&root_ccu_data, node);
|
||||
}
|
||||
|
||||
static void __init kona_dt_aon_ccu_setup(struct device_node *node)
|
||||
{
|
||||
kona_dt_ccu_setup(&aon_ccu_data, node);
|
||||
}
|
||||
|
||||
static void __init kona_dt_master_ccu_setup(struct device_node *node)
|
||||
{
|
||||
kona_dt_ccu_setup(&master_ccu_data, node);
|
||||
}
|
||||
|
||||
static void __init kona_dt_slave_ccu_setup(struct device_node *node)
|
||||
{
|
||||
kona_dt_ccu_setup(&slave_ccu_data, node);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(bcm21664_root_ccu, BCM21664_DT_ROOT_CCU_COMPAT,
|
||||
kona_dt_root_ccu_setup);
|
||||
CLK_OF_DECLARE(bcm21664_aon_ccu, BCM21664_DT_AON_CCU_COMPAT,
|
||||
kona_dt_aon_ccu_setup);
|
||||
CLK_OF_DECLARE(bcm21664_master_ccu, BCM21664_DT_MASTER_CCU_COMPAT,
|
||||
kona_dt_master_ccu_setup);
|
||||
CLK_OF_DECLARE(bcm21664_slave_ccu, BCM21664_DT_SLAVE_CCU_COMPAT,
|
||||
kona_dt_slave_ccu_setup);
|
||||
+95
-136
@@ -15,14 +15,10 @@
|
||||
#include "clk-kona.h"
|
||||
#include "dt-bindings/clock/bcm281xx.h"
|
||||
|
||||
/* bcm11351 CCU device tree "compatible" strings */
|
||||
#define BCM11351_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu"
|
||||
#define BCM11351_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
|
||||
#define BCM11351_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
|
||||
#define BCM11351_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
|
||||
#define BCM11351_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
|
||||
#define BCM281XX_CCU_COMMON(_name, _ucase_name) \
|
||||
KONA_CCU_COMMON(BCM281XX, _name, _ucase_name)
|
||||
|
||||
/* Root CCU clocks */
|
||||
/* Root CCU */
|
||||
|
||||
static struct peri_clk_data frac_1m_data = {
|
||||
.gate = HW_SW_GATE(0x214, 16, 0, 1),
|
||||
@@ -31,7 +27,16 @@ static struct peri_clk_data frac_1m_data = {
|
||||
.clocks = CLOCKS("ref_crystal"),
|
||||
};
|
||||
|
||||
/* AON CCU clocks */
|
||||
static struct ccu_data root_ccu_data = {
|
||||
BCM281XX_CCU_COMMON(root, ROOT),
|
||||
.kona_clks = {
|
||||
[BCM281XX_ROOT_CCU_FRAC_1M] =
|
||||
KONA_CLK(root, frac_1m, peri),
|
||||
[BCM281XX_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
||||
},
|
||||
};
|
||||
|
||||
/* AON CCU */
|
||||
|
||||
static struct peri_clk_data hub_timer_data = {
|
||||
.gate = HW_SW_GATE(0x0414, 16, 0, 1),
|
||||
@@ -60,7 +65,20 @@ static struct peri_clk_data pmu_bsc_var_data = {
|
||||
.trig = TRIGGER(0x0a40, 2),
|
||||
};
|
||||
|
||||
/* Hub CCU clocks */
|
||||
static struct ccu_data aon_ccu_data = {
|
||||
BCM281XX_CCU_COMMON(aon, AON),
|
||||
.kona_clks = {
|
||||
[BCM281XX_AON_CCU_HUB_TIMER] =
|
||||
KONA_CLK(aon, hub_timer, peri),
|
||||
[BCM281XX_AON_CCU_PMU_BSC] =
|
||||
KONA_CLK(aon, pmu_bsc, peri),
|
||||
[BCM281XX_AON_CCU_PMU_BSC_VAR] =
|
||||
KONA_CLK(aon, pmu_bsc_var, peri),
|
||||
[BCM281XX_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
||||
},
|
||||
};
|
||||
|
||||
/* Hub CCU */
|
||||
|
||||
static struct peri_clk_data tmon_1m_data = {
|
||||
.gate = HW_SW_GATE(0x04a4, 18, 2, 3),
|
||||
@@ -70,7 +88,16 @@ static struct peri_clk_data tmon_1m_data = {
|
||||
.trig = TRIGGER(0x0e84, 1),
|
||||
};
|
||||
|
||||
/* Master CCU clocks */
|
||||
static struct ccu_data hub_ccu_data = {
|
||||
BCM281XX_CCU_COMMON(hub, HUB),
|
||||
.kona_clks = {
|
||||
[BCM281XX_HUB_CCU_TMON_1M] =
|
||||
KONA_CLK(hub, tmon_1m, peri),
|
||||
[BCM281XX_HUB_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
||||
},
|
||||
};
|
||||
|
||||
/* Master CCU */
|
||||
|
||||
static struct peri_clk_data sdio1_data = {
|
||||
.gate = HW_SW_GATE(0x0358, 18, 2, 3),
|
||||
@@ -153,7 +180,28 @@ static struct peri_clk_data hsic2_12m_data = {
|
||||
.trig = TRIGGER(0x0afc, 5),
|
||||
};
|
||||
|
||||
/* Slave CCU clocks */
|
||||
static struct ccu_data master_ccu_data = {
|
||||
BCM281XX_CCU_COMMON(master, MASTER),
|
||||
.kona_clks = {
|
||||
[BCM281XX_MASTER_CCU_SDIO1] =
|
||||
KONA_CLK(master, sdio1, peri),
|
||||
[BCM281XX_MASTER_CCU_SDIO2] =
|
||||
KONA_CLK(master, sdio2, peri),
|
||||
[BCM281XX_MASTER_CCU_SDIO3] =
|
||||
KONA_CLK(master, sdio3, peri),
|
||||
[BCM281XX_MASTER_CCU_SDIO4] =
|
||||
KONA_CLK(master, sdio4, peri),
|
||||
[BCM281XX_MASTER_CCU_USB_IC] =
|
||||
KONA_CLK(master, usb_ic, peri),
|
||||
[BCM281XX_MASTER_CCU_HSIC2_48M] =
|
||||
KONA_CLK(master, hsic2_48m, peri),
|
||||
[BCM281XX_MASTER_CCU_HSIC2_12M] =
|
||||
KONA_CLK(master, hsic2_12m, peri),
|
||||
[BCM281XX_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
||||
},
|
||||
};
|
||||
|
||||
/* Slave CCU */
|
||||
|
||||
static struct peri_clk_data uartb_data = {
|
||||
.gate = HW_SW_GATE(0x0400, 18, 2, 3),
|
||||
@@ -261,156 +309,67 @@ static struct peri_clk_data pwm_data = {
|
||||
.trig = TRIGGER(0x0afc, 15),
|
||||
};
|
||||
|
||||
/*
|
||||
* CCU setup routines
|
||||
*
|
||||
* These are called from kona_dt_ccu_setup() to initialize the array
|
||||
* of clocks provided by the CCU. Once allocated, the entries in
|
||||
* the array are initialized by calling kona_clk_setup() with the
|
||||
* initialization data for each clock. They return 0 if successful
|
||||
* or an error code otherwise.
|
||||
*/
|
||||
static int __init bcm281xx_root_ccu_clks_setup(struct ccu_data *ccu)
|
||||
{
|
||||
struct clk **clks;
|
||||
size_t count = BCM281XX_ROOT_CCU_CLOCK_COUNT;
|
||||
|
||||
clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks) {
|
||||
pr_err("%s: failed to allocate root clocks\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
ccu->data.clks = clks;
|
||||
ccu->data.clk_num = count;
|
||||
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_ROOT_CCU_FRAC_1M, frac_1m);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init bcm281xx_aon_ccu_clks_setup(struct ccu_data *ccu)
|
||||
{
|
||||
struct clk **clks;
|
||||
size_t count = BCM281XX_AON_CCU_CLOCK_COUNT;
|
||||
|
||||
clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks) {
|
||||
pr_err("%s: failed to allocate aon clocks\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
ccu->data.clks = clks;
|
||||
ccu->data.clk_num = count;
|
||||
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_HUB_TIMER, hub_timer);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_PMU_BSC, pmu_bsc);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_PMU_BSC_VAR, pmu_bsc_var);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init bcm281xx_hub_ccu_clks_setup(struct ccu_data *ccu)
|
||||
{
|
||||
struct clk **clks;
|
||||
size_t count = BCM281XX_HUB_CCU_CLOCK_COUNT;
|
||||
|
||||
clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks) {
|
||||
pr_err("%s: failed to allocate hub clocks\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
ccu->data.clks = clks;
|
||||
ccu->data.clk_num = count;
|
||||
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_HUB_CCU_TMON_1M, tmon_1m);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init bcm281xx_master_ccu_clks_setup(struct ccu_data *ccu)
|
||||
{
|
||||
struct clk **clks;
|
||||
size_t count = BCM281XX_MASTER_CCU_CLOCK_COUNT;
|
||||
|
||||
clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks) {
|
||||
pr_err("%s: failed to allocate master clocks\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
ccu->data.clks = clks;
|
||||
ccu->data.clk_num = count;
|
||||
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO1, sdio1);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO2, sdio2);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO3, sdio3);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO4, sdio4);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_USB_IC, usb_ic);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_HSIC2_48M, hsic2_48m);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_HSIC2_12M, hsic2_12m);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init bcm281xx_slave_ccu_clks_setup(struct ccu_data *ccu)
|
||||
{
|
||||
struct clk **clks;
|
||||
size_t count = BCM281XX_SLAVE_CCU_CLOCK_COUNT;
|
||||
|
||||
clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks) {
|
||||
pr_err("%s: failed to allocate slave clocks\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
ccu->data.clks = clks;
|
||||
ccu->data.clk_num = count;
|
||||
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB, uartb);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB2, uartb2);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB3, uartb3);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB4, uartb4);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_SSP0, ssp0);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_SSP2, ssp2);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC1, bsc1);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC2, bsc2);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC3, bsc3);
|
||||
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_PWM, pwm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static struct ccu_data slave_ccu_data = {
|
||||
BCM281XX_CCU_COMMON(slave, SLAVE),
|
||||
.kona_clks = {
|
||||
[BCM281XX_SLAVE_CCU_UARTB] =
|
||||
KONA_CLK(slave, uartb, peri),
|
||||
[BCM281XX_SLAVE_CCU_UARTB2] =
|
||||
KONA_CLK(slave, uartb2, peri),
|
||||
[BCM281XX_SLAVE_CCU_UARTB3] =
|
||||
KONA_CLK(slave, uartb3, peri),
|
||||
[BCM281XX_SLAVE_CCU_UARTB4] =
|
||||
KONA_CLK(slave, uartb4, peri),
|
||||
[BCM281XX_SLAVE_CCU_SSP0] =
|
||||
KONA_CLK(slave, ssp0, peri),
|
||||
[BCM281XX_SLAVE_CCU_SSP2] =
|
||||
KONA_CLK(slave, ssp2, peri),
|
||||
[BCM281XX_SLAVE_CCU_BSC1] =
|
||||
KONA_CLK(slave, bsc1, peri),
|
||||
[BCM281XX_SLAVE_CCU_BSC2] =
|
||||
KONA_CLK(slave, bsc2, peri),
|
||||
[BCM281XX_SLAVE_CCU_BSC3] =
|
||||
KONA_CLK(slave, bsc3, peri),
|
||||
[BCM281XX_SLAVE_CCU_PWM] =
|
||||
KONA_CLK(slave, pwm, peri),
|
||||
[BCM281XX_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
||||
},
|
||||
};
|
||||
|
||||
/* Device tree match table callback functions */
|
||||
|
||||
static void __init kona_dt_root_ccu_setup(struct device_node *node)
|
||||
{
|
||||
kona_dt_ccu_setup(node, bcm281xx_root_ccu_clks_setup);
|
||||
kona_dt_ccu_setup(&root_ccu_data, node);
|
||||
}
|
||||
|
||||
static void __init kona_dt_aon_ccu_setup(struct device_node *node)
|
||||
{
|
||||
kona_dt_ccu_setup(node, bcm281xx_aon_ccu_clks_setup);
|
||||
kona_dt_ccu_setup(&aon_ccu_data, node);
|
||||
}
|
||||
|
||||
static void __init kona_dt_hub_ccu_setup(struct device_node *node)
|
||||
{
|
||||
kona_dt_ccu_setup(node, bcm281xx_hub_ccu_clks_setup);
|
||||
kona_dt_ccu_setup(&hub_ccu_data, node);
|
||||
}
|
||||
|
||||
static void __init kona_dt_master_ccu_setup(struct device_node *node)
|
||||
{
|
||||
kona_dt_ccu_setup(node, bcm281xx_master_ccu_clks_setup);
|
||||
kona_dt_ccu_setup(&master_ccu_data, node);
|
||||
}
|
||||
|
||||
static void __init kona_dt_slave_ccu_setup(struct device_node *node)
|
||||
{
|
||||
kona_dt_ccu_setup(node, bcm281xx_slave_ccu_clks_setup);
|
||||
kona_dt_ccu_setup(&slave_ccu_data, node);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(bcm11351_root_ccu, BCM11351_DT_ROOT_CCU_COMPAT,
|
||||
CLK_OF_DECLARE(bcm281xx_root_ccu, BCM281XX_DT_ROOT_CCU_COMPAT,
|
||||
kona_dt_root_ccu_setup);
|
||||
CLK_OF_DECLARE(bcm11351_aon_ccu, BCM11351_DT_AON_CCU_COMPAT,
|
||||
CLK_OF_DECLARE(bcm281xx_aon_ccu, BCM281XX_DT_AON_CCU_COMPAT,
|
||||
kona_dt_aon_ccu_setup);
|
||||
CLK_OF_DECLARE(bcm11351_hub_ccu, BCM11351_DT_HUB_CCU_COMPAT,
|
||||
CLK_OF_DECLARE(bcm281xx_hub_ccu, BCM281XX_DT_HUB_CCU_COMPAT,
|
||||
kona_dt_hub_ccu_setup);
|
||||
CLK_OF_DECLARE(bcm11351_master_ccu, BCM11351_DT_MASTER_CCU_COMPAT,
|
||||
CLK_OF_DECLARE(bcm281xx_master_ccu, BCM281XX_DT_MASTER_CCU_COMPAT,
|
||||
kona_dt_master_ccu_setup);
|
||||
CLK_OF_DECLARE(bcm11351_slave_ccu, BCM11351_DT_SLAVE_CCU_COMPAT,
|
||||
CLK_OF_DECLARE(bcm281xx_slave_ccu, BCM281XX_DT_SLAVE_CCU_COMPAT,
|
||||
kona_dt_slave_ccu_setup);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user