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Merge tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework changes from Mike Turquette: "The clock framework changes for 3.15 look similar to past pull requests. Mostly clock driver updates, more Device Tree support in the form of common functions useful across platforms and a handful of features and fixes to the framework core" * tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: shmobile: fix setting paretn clock rate clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1 clk: Fix minor errors in of_clk_init() function comments clk: reverse default clk provider initialization order in of_clk_init() clk: sirf: update copyright years to 2014 clk: mmp: try to use closer one when do round rate clk: mmp: fix the wrong calculation formula clk: mmp: fix wrong mask when calculate denominator clk: st: Adds quadfs clock binding clk: st: Adds clockgen-vcc and clockgen-mux clock binding clk: st: Adds clockgen clock binding clk: st: Adds divmux and prediv clock binding clk: st: Support for A9 MUX clocks clk: st: Support for ClockGenA9/DDR/GPU clk: st: Support for QUADFS inside ClockGenB/C/D/E/F clk: st: Support for VCC-mux and MUX clocks clk: st: Support for PLLs inside ClockGenA(s) clk: st: Support for DIVMUX and PreDiv Clocks clk: support hardware-specific debugfs entries clk: s2mps11: Use of_get_child_by_name ...
This commit is contained in:
Linus Torvalds
@@ -255,3 +255,37 @@ are sorted out.
|
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|
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To bypass this disabling, include "clk_ignore_unused" in the bootargs to the
|
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kernel.
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|
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Part 7 - Locking
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The common clock framework uses two global locks, the prepare lock and the
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enable lock.
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|
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The enable lock is a spinlock and is held across calls to the .enable,
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.disable and .is_enabled operations. Those operations are thus not allowed to
|
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sleep, and calls to the clk_enable(), clk_disable() and clk_is_enabled() API
|
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functions are allowed in atomic context.
|
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|
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The prepare lock is a mutex and is held across calls to all other operations.
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All those operations are allowed to sleep, and calls to the corresponding API
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functions are not allowed in atomic context.
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|
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This effectively divides operations in two groups from a locking perspective.
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|
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Drivers don't need to manually protect resources shared between the operations
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of one group, regardless of whether those resources are shared by multiple
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clocks or not. However, access to resources that are shared between operations
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of the two groups needs to be protected by the drivers. An example of such a
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resource would be a register that controls both the clock rate and the clock
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enable/disable state.
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The clock framework is reentrant, in that a driver is allowed to call clock
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framework functions from within its implementation of clock operations. This
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can for instance cause a .set_rate operation of one clock being called from
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within the .set_rate operation of another clock. This case must be considered
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in the driver implementations, but the code flow is usually controlled by the
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driver in that case.
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Note that locking must also be considered when code outside of the common
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clock framework needs to access resources used by the clock operations. This
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is considered out of scope of this document.
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@@ -30,3 +30,17 @@ Example:
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resume-offset = <0x308>;
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reboot-offset = <0x4>;
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};
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PCTRL: Peripheral misc control register
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|
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Required Properties:
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- compatible: "hisilicon,pctrl"
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- reg: Address and size of pctrl.
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|
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Example:
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/* for Hi3620 */
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pctrl: pctrl@fca09000 {
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compatible = "hisilicon,pctrl";
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reg = <0xfca09000 0x1000>;
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};
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@@ -23,3 +23,8 @@ Optional properties:
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and the bit index.
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- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
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and width.
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- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
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the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
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value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
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hold/delay times that is needed for the SD/MMC CIU clock. The values of both
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can be 0-315 degrees, in 45 degree increments.
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@@ -5,7 +5,7 @@ This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be "adi,axi-clkgen".
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- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
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- #clock-cells : from common clock binding; Should always be set to 0.
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- reg : Address and length of the axi-clkgen register set.
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- clocks : Phandle and clock specifier for the parent clock.
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@@ -44,6 +44,23 @@ For example:
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clocks by index. The names should reflect the clock output signal
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names for the device.
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clock-indices: If the identifyng number for the clocks in the node
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is not linear from zero, then the this mapping allows
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the mapping of identifiers into the clock-output-names
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array.
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For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
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oscillator {
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compatible = "myclocktype";
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#clock-cells = <1>;
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clock-indices = <1>, <3>;
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clock-output-names = "clka", "clkb";
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}
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This ensures we do not have any empty nodes in clock-output-names
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==Clock consumers==
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Required properties:
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@@ -7,6 +7,7 @@ Required Properties:
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- compatible: should be one of the following.
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- "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
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- "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
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|
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- reg: physical base address of the controller and length of memory mapped
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region.
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@@ -0,0 +1,48 @@
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Device Tree Clock bindings for arch-moxart
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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|
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MOXA ART SoCs allow to determine PLL output and APB frequencies
|
||||
by reading registers holding multiplier and divisor information.
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|
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PLL:
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Required properties:
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||||
- compatible : Must be "moxa,moxart-pll-clock"
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- #clock-cells : Should be 0
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- reg : Should contain registers location and length
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- clocks : Should contain phandle + clock-specifier for the parent clock
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Optional properties:
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- clock-output-names : Should contain clock name
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||||
|
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|
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APB:
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|
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Required properties:
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- compatible : Must be "moxa,moxart-apb-clock"
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- #clock-cells : Should be 0
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- reg : Should contain registers location and length
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- clocks : Should contain phandle + clock-specifier for the parent clock
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|
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Optional properties:
|
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- clock-output-names : Should contain clock name
|
||||
|
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|
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For example:
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|
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clk_pll: clk_pll@98100000 {
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compatible = "moxa,moxart-pll-clock";
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#clock-cells = <0>;
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reg = <0x98100000 0x34>;
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};
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clk_apb: clk_apb@98100000 {
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compatible = "moxa,moxart-apb-clock";
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#clock-cells = <0>;
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reg = <0x98100000 0x34>;
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clocks = <&clk_pll>;
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};
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@@ -11,6 +11,18 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
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3 = hclk (DRAM control clock)
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4 = dramclk (DDR clock)
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The following is a list of provided IDs and clock names on Armada 375:
|
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = l2clk (L2 Cache clock)
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3 = ddrclk (DDR clock)
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The following is a list of provided IDs and clock names on Armada 380/385:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = l2clk (L2 Cache clock)
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3 = ddrclk (DDR clock)
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The following is a list of provided IDs and clock names on Kirkwood and Dove:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU0 clock)
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@@ -20,6 +32,8 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
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||||
Required properties:
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||||
- compatible : shall be one of the following:
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"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
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"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
|
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"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
|
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"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
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"marvell,dove-core-clock" - for Dove SoC core clocks
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"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
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@@ -4,7 +4,10 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
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0 = nand (NAND clock)
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||||
|
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Required properties:
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||||
- compatible : must be "marvell,armada-370-corediv-clock"
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||||
- compatible : must be "marvell,armada-370-corediv-clock",
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"marvell,armada-375-corediv-clock",
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"marvell,armada-380-corediv-clock",
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- reg : must be the register address of Core Divider control register
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- #clock-cells : from common clock binding; shall be set to 1
|
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- clocks : must be set to the parent's phandle
|
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|
||||
@@ -1,9 +1,10 @@
|
||||
* Gated Clock bindings for Marvell EBU SoCs
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||||
|
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Marvell Armada 370/XP, Dove and Kirkwood allow some peripheral clocks to be
|
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gated to save some power. The clock consumer should specify the desired clock
|
||||
by having the clock ID in its "clocks" phandle cell. The clock ID is directly
|
||||
mapped to the corresponding clock gating control bit in HW to ease manual clock
|
||||
Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
|
||||
peripheral clocks to be gated to save some power. The clock consumer
|
||||
should specify the desired clock by having the clock ID in its
|
||||
"clocks" phandle cell. The clock ID is directly mapped to the
|
||||
corresponding clock gating control bit in HW to ease manual clock
|
||||
lookup in datasheet.
|
||||
|
||||
The following is a list of provided IDs for Armada 370:
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||||
@@ -22,6 +23,60 @@ ID Clock Peripheral
|
||||
28 ddr DDR Cntrl
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30 sata1 SATA Host 0
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|
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The following is a list of provided IDs for Armada 375:
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||||
ID Clock Peripheral
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||||
-----------------------------------
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||||
2 mu Management Unit
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3 pp Packet Processor
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||||
4 ptp PTP
|
||||
5 pex0 PCIe 0 Clock out
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6 pex1 PCIe 1 Clock out
|
||||
8 audio Audio Cntrl
|
||||
11 nd_clk Nand Flash Cntrl
|
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14 sata0_link SATA 0 Link
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15 sata0_core SATA 0 Core
|
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16 usb3 USB3 Host
|
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17 sdio SDHCI Host
|
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18 usb USB Host
|
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19 gop Gigabit Ethernet MAC
|
||||
20 sata1_link SATA 1 Link
|
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21 sata1_core SATA 1 Core
|
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22 xor0 XOR DMA 0
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23 xor1 XOR DMA 0
|
||||
24 copro Coprocessor
|
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25 tdm Time Division Mplx
|
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28 crypto0_enc Cryptographic Unit Port 0 Encryption
|
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29 crypto0_core Cryptographic Unit Port 0 Core
|
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30 crypto1_enc Cryptographic Unit Port 1 Encryption
|
||||
31 crypto1_core Cryptographic Unit Port 1 Core
|
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|
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The following is a list of provided IDs for Armada 380/385:
|
||||
ID Clock Peripheral
|
||||
-----------------------------------
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||||
0 audio Audio
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||||
2 ge2 Gigabit Ethernet 2
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3 ge1 Gigabit Ethernet 1
|
||||
4 ge0 Gigabit Ethernet 0
|
||||
5 pex1 PCIe 1
|
||||
6 pex2 PCIe 2
|
||||
7 pex3 PCIe 3
|
||||
8 pex0 PCIe 0
|
||||
9 usb3h0 USB3 Host 0
|
||||
10 usb3h1 USB3 Host 1
|
||||
11 usb3d USB3 Device
|
||||
13 bm Buffer Management
|
||||
14 crypto0z Cryptographic 0 Z
|
||||
15 sata0 SATA 0
|
||||
16 crypto1z Cryptographic 1 Z
|
||||
17 sdio SDIO
|
||||
18 usb2 USB 2
|
||||
21 crypto1 Cryptographic 1
|
||||
22 xor0 XOR 0
|
||||
23 crypto0 Cryptographic 0
|
||||
25 tdm Time Division Multiplexing
|
||||
28 xor1 XOR 1
|
||||
30 sata1 SATA 1
|
||||
|
||||
The following is a list of provided IDs for Armada XP:
|
||||
ID Clock Peripheral
|
||||
-----------------------------------
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||||
@@ -95,6 +150,8 @@ ID Clock Peripheral
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
|
||||
"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
|
||||
"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
|
||||
"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
|
||||
"marvell,dove-gating-clock" - for Dove SoC clock gating
|
||||
"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
|
||||
|
||||
@@ -0,0 +1,29 @@
|
||||
* Renesas RZ Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
|
||||
CPU and GPU clocks, and several fixed ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of
|
||||
- "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
|
||||
- "renesas,rz-cpg-clocks" for the generic RZ CPG
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
- clocks: References to possible parent clocks. Order must match clock modes
|
||||
in the datasheet. For the r7s72100, this is extal, usb_x1.
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "pll",
|
||||
"i", and "g"
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@fcfe0000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "renesas,r7s72100-cpg-clocks",
|
||||
"renesas,rz-cpg-clocks";
|
||||
reg = <0xfcfe0000 0x18>;
|
||||
clocks = <&extal_clk>, <&usb_x1_clk>;
|
||||
clock-output-names = "pll", "i", "g";
|
||||
};
|
||||
@@ -0,0 +1,49 @@
|
||||
Binding for a ST divider and multiplexer clock driver.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Base address is located to the parent node. See clock binding[2]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
|
||||
"st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
|
||||
"st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
|
||||
"st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
|
||||
"st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
|
||||
"st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"
|
||||
|
||||
- #clock-cells : From common clock binding; shall be set to 1.
|
||||
|
||||
- clocks : From common clock binding
|
||||
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
|
||||
clockgenA@fd345000 {
|
||||
reg = <0xfd345000 0xb50>;
|
||||
|
||||
CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-divmux-c32-odf1",
|
||||
"st,clkgena-divmux";
|
||||
|
||||
clocks = <&CLK_M_A1_OSC_PREDIV>,
|
||||
<&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
|
||||
<&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
|
||||
|
||||
clock-output-names = "CLK_M_RX_ICN_TS",
|
||||
"CLK_M_RX_ICN_VDP_0",
|
||||
"", /* Unused */
|
||||
"CLK_M_PRV_T1_BUS",
|
||||
"CLK_M_ICN_REG_12",
|
||||
"CLK_M_ICN_REG_10",
|
||||
"", /* Unused */
|
||||
"CLK_M_ICN_ST231";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
Binding for a ST multiplexed clock driver.
|
||||
|
||||
This binding supports only simple indexed multiplexers, it does not
|
||||
support table based parent index to hardware value translations.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
|
||||
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
|
||||
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
|
||||
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
- reg : A Base address and length of the register set.
|
||||
|
||||
- clocks : from common clock binding
|
||||
|
||||
Example:
|
||||
|
||||
CLK_M_HVA: CLK_M_HVA {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
|
||||
reg = <0xfd690868 4>;
|
||||
|
||||
clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
|
||||
};
|
||||
@@ -0,0 +1,48 @@
|
||||
Binding for a ST pll clock driver.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Base address is located to the parent node. See clock binding[2]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,clkgena-prediv-c65", "st,clkgena-prediv"
|
||||
"st,clkgena-prediv-c32", "st,clkgena-prediv"
|
||||
|
||||
"st,clkgena-plls-c65"
|
||||
"st,plls-c32-a1x-0", "st,clkgen-plls-c32"
|
||||
"st,plls-c32-a1x-1", "st,clkgen-plls-c32"
|
||||
"st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
|
||||
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
|
||||
|
||||
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
|
||||
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
|
||||
|
||||
|
||||
- #clock-cells : From common clock binding; shall be set to 1.
|
||||
|
||||
- clocks : From common clock binding
|
||||
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
|
||||
clockgenA@fee62000 {
|
||||
reg = <0xfee62000 0xb48>;
|
||||
|
||||
CLK_S_A0_PLL: CLK_S_A0_PLL {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-plls-c65";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
|
||||
clock-output-names = "CLK_S_A0_PLL0_HS",
|
||||
"CLK_S_A0_PLL0_LS",
|
||||
"CLK_S_A0_PLL1";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,36 @@
|
||||
Binding for a ST pre-divider clock driver.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Base address is located to the parent node. See clock binding[2]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,clkgena-prediv-c65", "st,clkgena-prediv"
|
||||
"st,clkgena-prediv-c32", "st,clkgena-prediv"
|
||||
|
||||
- #clock-cells : From common clock binding; shall be set to 0.
|
||||
|
||||
- clocks : From common clock binding
|
||||
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
|
||||
clockgenA@fd345000 {
|
||||
reg = <0xfd345000 0xb50>;
|
||||
|
||||
CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,clkgena-prediv-c32",
|
||||
"st,clkgena-prediv";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
|
||||
clock-output-names = "CLK_M_A2_OSC_PREDIV";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
Binding for a type of STMicroelectronics clock crossbar (VCC).
|
||||
|
||||
The crossbar can take up to 4 input clocks and control up to 16
|
||||
output clocks. Not all inputs or outputs have to be in use in a
|
||||
particular instantiation. Each output can be individually enabled,
|
||||
select any of the input clocks and apply a divide (by 1,2,4 or 8) to
|
||||
that selected clock.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,stih416-clkgenc", "st,vcc"
|
||||
"st,stih416-clkgenf", "st,vcc"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1.
|
||||
|
||||
- reg : A Base address and length of the register set.
|
||||
|
||||
- clocks : from common clock binding
|
||||
|
||||
- clock-output-names : From common clock binding. The block has 16
|
||||
clock outputs but not all of them in a specific instance
|
||||
have to be used in the SoC. If a clock name is left as
|
||||
an empty string then no clock will be created for the
|
||||
output associated with that string index. If fewer than
|
||||
16 strings are provided then no clocks will be created
|
||||
for the remaining outputs.
|
||||
|
||||
Example:
|
||||
|
||||
CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
|
||||
reg = <0xfe8308ac 12>;
|
||||
|
||||
clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
|
||||
<&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
|
||||
|
||||
clock-output-names =
|
||||
"CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
|
||||
"CLK_S_OUT_DVO", "CLK_S_PIX_HD",
|
||||
"CLK_S_HDDAC", "CLK_S_DENC",
|
||||
"CLK_S_SDDAC", "CLK_S_PIX_MAIN",
|
||||
"CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
|
||||
"CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
|
||||
"CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
|
||||
"CLK_S_THSENS";
|
||||
};
|
||||
|
||||
@@ -0,0 +1,83 @@
|
||||
Binding for a Clockgen hardware block found on
|
||||
certain STMicroelectronics consumer electronics SoC devices.
|
||||
|
||||
A Clockgen node can contain pll, diviser or multiplexer nodes.
|
||||
|
||||
We will find only the base address of the Clockgen, this base
|
||||
address is common of all subnode.
|
||||
|
||||
clockgen_node {
|
||||
reg = <>;
|
||||
|
||||
pll_node {
|
||||
...
|
||||
};
|
||||
|
||||
prediv_node {
|
||||
...
|
||||
};
|
||||
|
||||
divmux_node {
|
||||
...
|
||||
};
|
||||
|
||||
quadfs_node {
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Each subnode should use the binding discribe in [2]..[4]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
|
||||
Required properties:
|
||||
- reg : A Base address and length of the register set.
|
||||
|
||||
Example:
|
||||
|
||||
clockgenA@fee62000 {
|
||||
|
||||
reg = <0xfee62000 0xb48>;
|
||||
|
||||
CLK_S_A0_PLL: CLK_S_A0_PLL {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-plls-c65";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
|
||||
clock-output-names = "CLK_S_A0_PLL0_HS",
|
||||
"CLK_S_A0_PLL0_LS",
|
||||
"CLK_S_A0_PLL1";
|
||||
};
|
||||
|
||||
CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,clkgena-prediv-c65",
|
||||
"st,clkgena-prediv";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
|
||||
clock-output-names = "CLK_S_A0_OSC_PREDIV";
|
||||
};
|
||||
|
||||
CLK_S_A0_HS: CLK_S_A0_HS {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-divmux-c65-hs",
|
||||
"st,clkgena-divmux";
|
||||
|
||||
clocks = <&CLK_S_A0_OSC_PREDIV>,
|
||||
<&CLK_S_A0_PLL 0>, /* PLL0 HS */
|
||||
<&CLK_S_A0_PLL 2>; /* PLL1 */
|
||||
|
||||
clock-output-names = "CLK_S_FDMA_0",
|
||||
"CLK_S_FDMA_1",
|
||||
""; /* CLK_S_JIT_SENSE */
|
||||
/* Fourth output unused */
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
Binding for a type of quad channel digital frequency synthesizer found on
|
||||
certain STMicroelectronics consumer electronics SoC devices.
|
||||
|
||||
This version contains a programmable PLL which can generate up to 216, 432
|
||||
or 660MHz (from a 30MHz oscillator input) as the input to the digital
|
||||
synthesizers.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be:
|
||||
"st,stih416-quadfs216", "st,quadfs"
|
||||
"st,stih416-quadfs432", "st,quadfs"
|
||||
"st,stih416-quadfs660-E", "st,quadfs"
|
||||
"st,stih416-quadfs660-F", "st,quadfs"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1.
|
||||
|
||||
- reg : A Base address and length of the register set.
|
||||
|
||||
- clocks : from common clock binding
|
||||
|
||||
- clock-output-names : From common clock binding. The block has 4
|
||||
clock outputs but not all of them in a specific instance
|
||||
have to be used in the SoC. If a clock name is left as
|
||||
an empty string then no clock will be created for the
|
||||
output associated with that string index. If fewer than
|
||||
4 strings are provided then no clocks will be created
|
||||
for the remaining outputs.
|
||||
|
||||
Example:
|
||||
|
||||
CLOCKGEN_E: CLOCKGEN_E {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,stih416-quadfs660-E", "st,quadfs";
|
||||
reg = <0xfd3208bc 0xB0>;
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clock-output-names = "CLK_M_PIX_MDTP_0",
|
||||
"CLK_M_PIX_MDTP_1",
|
||||
"CLK_M_PIX_MDTP_2",
|
||||
"CLK_M_MPELPC";
|
||||
};
|
||||
@@ -6,37 +6,41 @@ This binding uses the common clock binding[1].
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"allwinner,sun4i-osc-clk" - for a gatable oscillator
|
||||
"allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
|
||||
"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
|
||||
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
|
||||
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
|
||||
"allwinner,sun4i-pll5-clk" - for the PLL5 clock
|
||||
"allwinner,sun4i-pll6-clk" - for the PLL6 clock
|
||||
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-axi-clk" - for the AXI clock
|
||||
"allwinner,sun4i-axi-gates-clk" - for the AXI gates
|
||||
"allwinner,sun4i-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
|
||||
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
|
||||
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
|
||||
"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
|
||||
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
|
||||
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
|
||||
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
|
||||
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
|
||||
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
|
||||
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
|
||||
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
|
||||
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
|
||||
"allwinner,sun4i-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
|
||||
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
|
||||
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
|
||||
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
|
||||
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
|
||||
"allwinner,sun4i-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
|
||||
"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
|
||||
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
|
||||
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
|
||||
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
|
||||
"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
|
||||
"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
|
||||
"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
|
||||
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
|
||||
"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
|
||||
"allwinner,sun7i-a20-out-clk" - for the external output clocks
|
||||
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
|
||||
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
|
||||
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
|
||||
|
||||
Required properties for all clocks:
|
||||
- reg : shall be the control register address for the clock.
|
||||
@@ -44,10 +48,17 @@ Required properties for all clocks:
|
||||
multiplexed clocks, the list order must match the hardware
|
||||
programming order.
|
||||
- #clock-cells : from common clock binding; shall be set to 0 except for
|
||||
"allwinner,*-gates-clk" where it shall be set to 1
|
||||
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
|
||||
"allwinner,sun4i-pll6-clk" where it shall be set to 1
|
||||
- clock-output-names : shall be the corresponding names of the outputs.
|
||||
If the clock module only has one output, the name shall be the
|
||||
module name.
|
||||
|
||||
Additionally, "allwinner,*-gates-clk" clocks require:
|
||||
- clock-output-names : the corresponding gate names that the clock controls
|
||||
And "allwinner,*-usb-clk" clocks also require:
|
||||
- reset-cells : shall be set to 1
|
||||
|
||||
For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
|
||||
dummy clocks at 25 MHz and 125 MHz, respectively. See example.
|
||||
|
||||
Clock consumers should specify the desired clocks they use with a
|
||||
"clocks" phandle cell. Consumers that are using a gated clock should
|
||||
@@ -56,23 +67,68 @@ offset of the bit controlling this particular gate in the register.
|
||||
|
||||
For example:
|
||||
|
||||
osc24M: osc24M@01c20050 {
|
||||
osc24M: clk@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-osc-clk";
|
||||
compatible = "allwinner,sun4i-a10-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clocks = <&osc24M_fixed>;
|
||||
clock-output-names = "osc24M";
|
||||
};
|
||||
|
||||
pll1: pll1@01c20000 {
|
||||
pll1: clk@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll1";
|
||||
};
|
||||
|
||||
pll5: clk@01c20020 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll5-clk";
|
||||
reg = <0x01c20020 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll5_ddr", "pll5_other";
|
||||
};
|
||||
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
compatible = "allwinner,sun4i-a10-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>;
|
||||
clock-output-names = "cpu";
|
||||
};
|
||||
|
||||
mmc0_clk: clk@01c20088 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc0";
|
||||
};
|
||||
|
||||
mii_phy_tx_clk: clk@2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "mii_phy_tx";
|
||||
};
|
||||
|
||||
gmac_int_tx_clk: clk@3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "gmac_int_tx";
|
||||
};
|
||||
|
||||
gmac_clk: clk@01c20164 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun7i-a20-gmac-clk";
|
||||
reg = <0x01c20164 0x4>;
|
||||
/*
|
||||
* The first clock must be fixed at 25MHz;
|
||||
* the second clock must be fixed at 125MHz
|
||||
*/
|
||||
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
|
||||
clock-output-names = "gmac";
|
||||
};
|
||||
|
||||
+1
-1
@@ -2318,7 +2318,7 @@ F: include/uapi/linux/coda*.h
|
||||
|
||||
COMMON CLK FRAMEWORK
|
||||
M: Mike Turquette <mturquette@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (same as CLK API & CLKDEV)
|
||||
L: linux-kernel@vger.kernel.org
|
||||
T: git git://git.linaro.org/people/mturquette/linux.git
|
||||
S: Maintained
|
||||
F: drivers/clk/
|
||||
|
||||
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Reference in New Issue
Block a user