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Documentation: DT bindings: add more Tegra chip compatible strings
Align compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers: http://marc.info/?l=devicetree&m=142255654213019&w=2 The primary objective here is to avoid checkpatch warnings, per: http://marc.info/?l=linux-tegra&m=142201349727836&w=2 DT binding text files have been updated for the following IP blocks: - PCIe - SOR - SoC timers - AHB "gizmo" - APB_MISC - pinmux control - UART - PWM - I2C - SPI - RTC - PMC - eFuse - AHCI - HDA - XUSB_PADCTRL - SDHCI - SOC_THERM - AHUB - I2S - EHCI - USB PHY N.B. The nvidia,tegra20-timer compatible string is removed from the nvidia,tegra30-timer.txt documentation file because it's already mentioned in the nvidia,tegra20-timer.txt documentation file. This second version takes into account the following requests from Rob Herring <robherring2@gmail.com>: - Per-IP block patches have been combined into a single patch - Explicit documentation about which compatible strings are actually matched by the driver has been removed. In its place is implicit documentation that loosely follows Rob's prescribed format: "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ..." [...] "You should attempt to document known values of <chip> if you use it" Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Dylan Reid <dgreid@chromium.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Jingchang Lu <jingchang.lu@freescale.com> Cc: John Crispin <blogic@openwrt.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mikko Perttunen <mperttunen@nvidia.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Takashi Iwai <tiwai@suse.de> Cc: Tejun Heo <tj@kernel.org> Cc: "Terje Bergström" <tbergstrom@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Zhang Rui <rui.zhang@intel.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-i2c@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-pwm@vger.kernel.org Cc: linux-tegra@vger.kernel.org Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Paul Walmsley
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Rob Herring
Rob Herring
parent
2d4c0aef0f
commit
193c9d23a0
@@ -1,7 +1,10 @@
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NVIDIA Tegra AHB
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Required properties:
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- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb"
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- compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
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Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
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'"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
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tegra132, or tegra210.
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- reg : Should contain 1 register ranges(address and length)
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Example:
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@@ -6,7 +6,11 @@ modes. It provides power-gating controllers for SoC and CPU power-islands.
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Required properties:
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- name : Should be pmc
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- compatible : Should contain "nvidia,tegra<chip>-pmc".
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- compatible : For Tegra20, must contain "nvidia,tegra20-pmc". For Tegra30,
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must contain "nvidia,tegra30-pmc". For Tegra114, must contain
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"nvidia,tegra114-pmc". For Tegra124, must contain "nvidia,tegra124-pmc".
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Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the
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above, where <chip> is tegra132.
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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@@ -1,7 +1,9 @@
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Tegra124 SoC SATA AHCI controller
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Required properties :
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- compatible : "nvidia,tegra124-ahci".
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- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
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must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
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is tegra132.
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- reg : Should contain 2 entries:
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- AHCI register set (SATA BAR5)
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- SATA register set
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@@ -1,11 +1,11 @@
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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
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Required properties:
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- compatible : should be:
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"nvidia,tegra20-efuse"
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"nvidia,tegra30-efuse"
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"nvidia,tegra114-efuse"
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"nvidia,tegra124-efuse"
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- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
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must contain "nvidia,tegra30-efuse". For Tegra114, must contain
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"nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
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Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
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<chip> is tegra132.
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Details:
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nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
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due to a hardware bug. Tegra20 also lacks certain information which is
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@@ -197,7 +197,9 @@ of the following host1x client modules:
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- sor: serial output resource
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Required properties:
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- compatible: "nvidia,tegra124-sor"
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- compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise,
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must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>
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is tegra132.
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.
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@@ -222,7 +224,9 @@ of the following host1x client modules:
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- nvidia,dpaux: phandle to a DispayPort AUX interface
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- dpaux: DisplayPort AUX interface
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- compatible: "nvidia,tegra124-dpaux"
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- compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
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must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
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<chip> is tegra132.
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.
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@@ -1,11 +1,11 @@
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NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
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Required properties:
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- compatible : should be:
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"nvidia,tegra114-i2c"
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"nvidia,tegra30-i2c"
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"nvidia,tegra20-i2c"
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"nvidia,tegra20-i2c-dvc"
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- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
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"nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
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For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
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"nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
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tegra124, tegra132, or tegra210.
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Details of compatible are as follows:
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nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
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controller. This only support master mode of I2C communication. Register
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@@ -1,11 +1,10 @@
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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block
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Required properties:
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- compatible : should be:
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"nvidia,tegra20-apbmisc"
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"nvidia,tegra30-apbmisc"
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"nvidia,tegra114-apbmisc"
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"nvidia,tegra124-apbmisc"
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- compatible : For Tegra20, must be "nvidia,tegra20-apbmisc". For Tegra30,
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must be "nvidia,tegra30-apbmisc". Otherwise, must contain
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"nvidia,<chip>-apbmisc", plus one of the above, where <chip> is tegra114,
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tegra124, tegra132.
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- reg: Should contain 2 entries: the first entry gives the physical address
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and length of the registers which contain revision and debug features.
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The second entry gives the physical address and length of the
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@@ -7,7 +7,11 @@ This file documents differences between the core properties described
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by mmc.txt and the properties used by the sdhci-tegra driver.
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Required properties:
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- compatible : Should be "nvidia,<chip>-sdhci"
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- compatible : For Tegra20, must contain "nvidia,tegra20-sdhci".
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For Tegra30, must contain "nvidia,tegra30-sdhci". For Tegra114,
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must contain "nvidia,tegra114-sdhci". For Tegra124, must contain
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"nvidia,tegra124-sdhci". Otherwise, must contain "nvidia,<chip>-sdhci",
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plus one of the above, where <chip> is tegra132 or tegra210.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets : Must contain an entry for each entry in reset-names.
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@@ -1,10 +1,10 @@
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NVIDIA Tegra PCIe controller
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Required properties:
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- compatible: Must be one of:
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- "nvidia,tegra20-pcie"
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- "nvidia,tegra30-pcie"
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- "nvidia,tegra124-pcie"
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- compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30,
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"nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie".
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Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
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<chip> is tegra132 or tegra210.
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- device_type: Must be "pci"
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- reg: A list of physical base address and length for each set of controller
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registers. Must contain an entry for each entry in the reg-names property.
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@@ -6,7 +6,8 @@ nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
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a baseline, and only documents the differences between the two bindings.
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Required properties:
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- compatible: "nvidia,tegra124-pinmux"
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- compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
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Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
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- reg: Should contain a list of base address and size pairs for:
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-- first entry - the drive strength and pad control registers.
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-- second entry - the pinmux registers
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@@ -13,7 +13,9 @@ how to describe and reference PHYs in device trees.
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Required properties:
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--------------------
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- compatible: should be "nvidia,tegra124-xusb-padctl"
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- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
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Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
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"nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
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- reg: Physical base address and length of the controller's registers.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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@@ -1,9 +1,10 @@
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Tegra SoC PWFM controller
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Required properties:
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- compatible: should be one of:
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- "nvidia,tegra20-pwm"
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- "nvidia,tegra30-pwm"
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- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". For Tegra30,
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must contain "nvidia,tegra30-pwm". Otherwise, must contain
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"nvidia,<chip>-pwm", plus one of the above, where <chip> is tegra114,
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tegra124, tegra132, or tegra210.
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- reg: physical base address and length of the controller's registers
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- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
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the cells format.
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@@ -6,7 +6,9 @@ state.
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Required properties:
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- compatible : should be "nvidia,tegra20-rtc".
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- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise,
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must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip>
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can be tegra30, tegra114, tegra124, or tegra132.
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A single interrupt specifier.
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- clocks : Must contain one entry, for the module clock.
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@@ -8,7 +8,10 @@ Required properties:
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- "ns16550"
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- "ns16750"
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- "ns16850"
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- "nvidia,tegra20-uart"
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- For Tegra20, must contain "nvidia,tegra20-uart"
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- For other Tegra, must contain '"nvidia,<chip>-uart",
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"nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
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tegra132, or tegra210.
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- "nxp,lpc3220-uart"
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- "ralink,rt2880-uart"
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- "ibm,qpace-nwp-serial"
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@@ -1,7 +1,10 @@
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NVIDIA Tegra30 AHUB (Audio Hub)
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Required properties:
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- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc.
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- compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
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must contain "nvidia,tegra114-ahub". For Tegra124, must contain
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"nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
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plus at least one of the above, where <chip> is tegra132.
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- reg : Should contain the register physical address and length for each of
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the AHUB's register blocks.
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- Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
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@@ -1,7 +1,9 @@
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NVIDIA Tegra30 HDA controller
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Required properties:
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- compatible : "nvidia,tegra30-hda"
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- compatible : For Tegra30, must contain "nvidia,tegra30-hda". Otherwise,
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must contain '"nvidia,<chip>-hda", "nvidia,tegra30-hda"', where <chip> is
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tegra114, tegra124, or tegra132.
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- reg : Should contain the HDA registers location and length.
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- interrupts : The interrupt from the HDA controller.
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- clocks : Must contain an entry for each required entry in clock-names.
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@@ -1,7 +1,10 @@
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NVIDIA Tegra30 I2S controller
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Required properties:
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- compatible : "nvidia,tegra30-i2s"
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- compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124,
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must contain "nvidia,tegra124-i2s". Otherwise, must contain
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"nvidia,<chip>-i2s" plus at least one of the above, where <chip> is
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tegra114 or tegra132.
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- reg : Should contain I2S registers location and length
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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@@ -1,7 +1,9 @@
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NVIDIA Tegra114 SPI controller.
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Required properties:
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- compatible : should be "nvidia,tegra114-spi".
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- compatible : For Tegra114, must contain "nvidia,tegra114-spi".
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Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
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<chip> is tegra124, tegra132, or tegra210.
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- reg: Should contain SPI registers location and length.
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- interrupts: Should contain SPI interrupts.
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- clock-names : Must include the following entries:
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@@ -7,7 +7,9 @@ notifications. It is also used to manage emergency shutdown in an
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overheating situation.
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Required properties :
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- compatible : "nvidia,tegra124-soctherm".
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- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
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For Tegra132, must contain "nvidia,tegra132-soctherm".
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For Tegra210, must contain "nvidia,tegra210-soctherm".
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- reg : Should contain 1 entry:
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- SOCTHERM register set
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- interrupts : Defines the interrupt used by SOCTHERM
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@@ -6,7 +6,9 @@ trigger a legacy watchdog reset.
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Required properties:
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- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
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- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise,
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must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where
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<chip> is tegra124 or tegra132.
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 6 interrupts; one per each of timer channels 1
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through 5, and one for the shared interrupt for the remaining channels.
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