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[ALSA] Add ASoC drivers for the Freescale MPC8610 SoC
Add the ASoC drivers for the Freescale MPC8610 SoC and the MPC8610 HPCD reference board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
This commit is contained in:
Timur Tabi
committed by
Jaroslav Kysela
Jaroslav Kysela
parent
ce22e03e62
commit
17467f2339
@@ -28,6 +28,7 @@ source "sound/soc/at91/Kconfig"
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source "sound/soc/pxa/Kconfig"
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source "sound/soc/s3c24xx/Kconfig"
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source "sound/soc/sh/Kconfig"
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source "sound/soc/fsl/Kconfig"
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# Supported codecs
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source "sound/soc/codecs/Kconfig"
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+1
-1
@@ -1,4 +1,4 @@
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snd-soc-core-objs := soc-core.o soc-dapm.o
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obj-$(CONFIG_SND_SOC) += snd-soc-core.o
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obj-$(CONFIG_SND_SOC) += codecs/ at91/ pxa/ s3c24xx/ sh/
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obj-$(CONFIG_SND_SOC) += codecs/ at91/ pxa/ s3c24xx/ sh/ fsl/
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@@ -0,0 +1,20 @@
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menu "ALSA SoC audio for Freescale SOCs"
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config SND_SOC_MPC8610
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bool "ALSA SoC support for the MPC8610 SOC"
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depends on SND_SOC && MPC8610_HPCD
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default y if MPC8610
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help
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Say Y if you want to add support for codecs attached to the SSI
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device on an MPC8610.
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config SND_SOC_MPC8610_HPCD
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bool "ALSA SoC support for the Freescale MPC8610 HPCD board"
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depends on SND_SOC_MPC8610
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select SND_SOC_CS4270
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select SND_SOC_CS4270_VD33_ERRATA
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default y if MPC8610_HPCD
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help
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Say Y if you want to enable audio on the Freescale MPC8610 HPCD.
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endmenu
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@@ -0,0 +1,6 @@
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# MPC8610 HPCD Machine Support
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obj-$(CONFIG_SND_SOC_MPC8610_HPCD) += mpc8610_hpcd.o
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# MPC8610 Platform Support
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obj-$(CONFIG_SND_SOC_MPC8610) += fsl_ssi.o fsl_dma.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,149 @@
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/*
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* mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _MPC8610_PCM_H
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#define _MPC8610_PCM_H
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struct ccsr_dma {
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u8 res0[0x100];
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struct ccsr_dma_channel {
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__be32 mr; /* Mode register */
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__be32 sr; /* Status register */
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__be32 eclndar; /* Current link descriptor extended addr reg */
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__be32 clndar; /* Current link descriptor address register */
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__be32 satr; /* Source attributes register */
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__be32 sar; /* Source address register */
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__be32 datr; /* Destination attributes register */
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__be32 dar; /* Destination address register */
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__be32 bcr; /* Byte count register */
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__be32 enlndar; /* Next link descriptor extended address reg */
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__be32 nlndar; /* Next link descriptor address register */
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u8 res1[4];
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__be32 eclsdar; /* Current list descriptor extended addr reg */
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__be32 clsdar; /* Current list descriptor address register */
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__be32 enlsdar; /* Next list descriptor extended address reg */
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__be32 nlsdar; /* Next list descriptor address register */
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__be32 ssr; /* Source stride register */
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__be32 dsr; /* Destination stride register */
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u8 res2[0x38];
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} channel[4];
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__be32 dgsr;
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};
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#define CCSR_DMA_MR_BWC_DISABLED 0x0F000000
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#define CCSR_DMA_MR_BWC_SHIFT 24
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#define CCSR_DMA_MR_BWC_MASK 0x0F000000
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#define CCSR_DMA_MR_BWC(x) \
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((ilog2(x) << CCSR_DMA_MR_BWC_SHIFT) & CCSR_DMA_MR_BWC_MASK)
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#define CCSR_DMA_MR_EMP_EN 0x00200000
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#define CCSR_DMA_MR_EMS_EN 0x00040000
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#define CCSR_DMA_MR_DAHTS_MASK 0x00030000
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#define CCSR_DMA_MR_DAHTS_1 0x00000000
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#define CCSR_DMA_MR_DAHTS_2 0x00010000
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#define CCSR_DMA_MR_DAHTS_4 0x00020000
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#define CCSR_DMA_MR_DAHTS_8 0x00030000
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#define CCSR_DMA_MR_SAHTS_MASK 0x0000C000
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#define CCSR_DMA_MR_SAHTS_1 0x00000000
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#define CCSR_DMA_MR_SAHTS_2 0x00004000
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#define CCSR_DMA_MR_SAHTS_4 0x00008000
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#define CCSR_DMA_MR_SAHTS_8 0x0000C000
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#define CCSR_DMA_MR_DAHE 0x00002000
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#define CCSR_DMA_MR_SAHE 0x00001000
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#define CCSR_DMA_MR_SRW 0x00000400
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#define CCSR_DMA_MR_EOSIE 0x00000200
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#define CCSR_DMA_MR_EOLNIE 0x00000100
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#define CCSR_DMA_MR_EOLSIE 0x00000080
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#define CCSR_DMA_MR_EIE 0x00000040
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#define CCSR_DMA_MR_XFE 0x00000020
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#define CCSR_DMA_MR_CDSM_SWSM 0x00000010
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#define CCSR_DMA_MR_CA 0x00000008
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#define CCSR_DMA_MR_CTM 0x00000004
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#define CCSR_DMA_MR_CC 0x00000002
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#define CCSR_DMA_MR_CS 0x00000001
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#define CCSR_DMA_SR_TE 0x00000080
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#define CCSR_DMA_SR_CH 0x00000020
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#define CCSR_DMA_SR_PE 0x00000010
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#define CCSR_DMA_SR_EOLNI 0x00000008
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#define CCSR_DMA_SR_CB 0x00000004
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#define CCSR_DMA_SR_EOSI 0x00000002
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#define CCSR_DMA_SR_EOLSI 0x00000001
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/* ECLNDAR takes bits 32-36 of the CLNDAR register */
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static inline u32 CCSR_DMA_ECLNDAR_ADDR(u64 x)
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{
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return (x >> 32) & 0xf;
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}
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#define CCSR_DMA_CLNDAR_ADDR(x) ((x) & 0xFFFFFFFE)
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#define CCSR_DMA_CLNDAR_EOSIE 0x00000008
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/* SATR and DATR, combined */
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#define CCSR_DMA_ATR_PBATMU 0x20000000
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#define CCSR_DMA_ATR_TFLOWLVL_0 0x00000000
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#define CCSR_DMA_ATR_TFLOWLVL_1 0x06000000
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#define CCSR_DMA_ATR_TFLOWLVL_2 0x08000000
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#define CCSR_DMA_ATR_TFLOWLVL_3 0x0C000000
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#define CCSR_DMA_ATR_PCIORDER 0x02000000
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#define CCSR_DMA_ATR_SME 0x01000000
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#define CCSR_DMA_ATR_NOSNOOP 0x00040000
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#define CCSR_DMA_ATR_SNOOP 0x00050000
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#define CCSR_DMA_ATR_ESAD_MASK 0x0000000F
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/**
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* List Descriptor for extended chaining mode DMA operations.
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*
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* The CLSDAR register points to the first (in a linked-list) List
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* Descriptor. Each object must be aligned on a 32-byte boundary. Each
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* list descriptor points to a linked-list of link Descriptors.
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*/
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struct fsl_dma_list_descriptor {
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__be64 next; /* Address of next list descriptor */
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__be64 first_link; /* Address of first link descriptor */
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__be32 source; /* Source stride */
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__be32 dest; /* Destination stride */
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u8 res[8]; /* Reserved */
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} __attribute__ ((aligned(32), packed));
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/**
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* Link Descriptor for basic and extended chaining mode DMA operations.
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*
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* A Link Descriptor points to a single DMA buffer. Each link descriptor
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* must be aligned on a 32-byte boundary.
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*/
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struct fsl_dma_link_descriptor {
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__be32 source_attr; /* Programmed into SATR register */
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__be32 source_addr; /* Programmed into SAR register */
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__be32 dest_attr; /* Programmed into DATR register */
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__be32 dest_addr; /* Programmed into DAR register */
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__be64 next; /* Address of next link descriptor */
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__be32 count; /* Byte count */
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u8 res[4]; /* Reserved */
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} __attribute__ ((aligned(32), packed));
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/* DMA information needed to create a snd_soc_cpu_dai object
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*
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* ssi_stx_phys: bus address of SSI STX register to use
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* ssi_srx_phys: bus address of SSI SRX register to use
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* dma[0]: points to the DMA channel to use for playback
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* dma[1]: points to the DMA channel to use for capture
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* dma_irq[0]: IRQ of the DMA channel to use for playback
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* dma_irq[1]: IRQ of the DMA channel to use for capture
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*/
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struct fsl_dma_info {
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dma_addr_t ssi_stx_phys;
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dma_addr_t ssi_srx_phys;
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struct ccsr_dma_channel __iomem *dma_channel[2];
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unsigned int dma_irq[2];
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};
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extern struct snd_soc_platform fsl_soc_platform;
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int fsl_dma_configure(struct fsl_dma_info *dma_info);
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#endif
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,224 @@
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/*
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* fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 SoC
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed
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* under the terms of the GNU General Public License version 2. This
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* program is licensed "as is" without any warranty of any kind, whether
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* express or implied.
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*/
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#ifndef _MPC8610_I2S_H
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#define _MPC8610_I2S_H
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/* SSI Register Map */
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struct ccsr_ssi {
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__be32 stx0; /* 0x.0000 - SSI Transmit Data Register 0 */
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__be32 stx1; /* 0x.0004 - SSI Transmit Data Register 1 */
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__be32 srx0; /* 0x.0008 - SSI Receive Data Register 0 */
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__be32 srx1; /* 0x.000C - SSI Receive Data Register 1 */
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__be32 scr; /* 0x.0010 - SSI Control Register */
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__be32 sisr; /* 0x.0014 - SSI Interrupt Status Register Mixed */
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__be32 sier; /* 0x.0018 - SSI Interrupt Enable Register */
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__be32 stcr; /* 0x.001C - SSI Transmit Configuration Register */
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__be32 srcr; /* 0x.0020 - SSI Receive Configuration Register */
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__be32 stccr; /* 0x.0024 - SSI Transmit Clock Control Register */
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__be32 srccr; /* 0x.0028 - SSI Receive Clock Control Register */
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__be32 sfcsr; /* 0x.002C - SSI FIFO Control/Status Register */
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__be32 str; /* 0x.0030 - SSI Test Register */
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__be32 sor; /* 0x.0034 - SSI Option Register */
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__be32 sacnt; /* 0x.0038 - SSI AC97 Control Register */
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__be32 sacadd; /* 0x.003C - SSI AC97 Command Address Register */
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__be32 sacdat; /* 0x.0040 - SSI AC97 Command Data Register */
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__be32 satag; /* 0x.0044 - SSI AC97 Tag Register */
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__be32 stmsk; /* 0x.0048 - SSI Transmit Time Slot Mask Register */
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__be32 srmsk; /* 0x.004C - SSI Receive Time Slot Mask Register */
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__be32 saccst; /* 0x.0050 - SSI AC97 Channel Status Register */
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__be32 saccen; /* 0x.0054 - SSI AC97 Channel Enable Register */
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__be32 saccdis; /* 0x.0058 - SSI AC97 Channel Disable Register */
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};
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#define CCSR_SSI_SCR_RFR_CLK_DIS 0x00000800
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#define CCSR_SSI_SCR_TFR_CLK_DIS 0x00000400
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#define CCSR_SSI_SCR_TCH_EN 0x00000100
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#define CCSR_SSI_SCR_SYS_CLK_EN 0x00000080
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#define CCSR_SSI_SCR_I2S_MODE_MASK 0x00000060
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#define CCSR_SSI_SCR_I2S_MODE_NORMAL 0x00000000
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#define CCSR_SSI_SCR_I2S_MODE_MASTER 0x00000020
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#define CCSR_SSI_SCR_I2S_MODE_SLAVE 0x00000040
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#define CCSR_SSI_SCR_SYN 0x00000010
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#define CCSR_SSI_SCR_NET 0x00000008
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#define CCSR_SSI_SCR_RE 0x00000004
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#define CCSR_SSI_SCR_TE 0x00000002
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#define CCSR_SSI_SCR_SSIEN 0x00000001
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#define CCSR_SSI_SISR_RFRC 0x01000000
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#define CCSR_SSI_SISR_TFRC 0x00800000
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#define CCSR_SSI_SISR_CMDAU 0x00040000
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#define CCSR_SSI_SISR_CMDDU 0x00020000
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#define CCSR_SSI_SISR_RXT 0x00010000
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#define CCSR_SSI_SISR_RDR1 0x00008000
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#define CCSR_SSI_SISR_RDR0 0x00004000
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#define CCSR_SSI_SISR_TDE1 0x00002000
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#define CCSR_SSI_SISR_TDE0 0x00001000
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#define CCSR_SSI_SISR_ROE1 0x00000800
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#define CCSR_SSI_SISR_ROE0 0x00000400
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#define CCSR_SSI_SISR_TUE1 0x00000200
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#define CCSR_SSI_SISR_TUE0 0x00000100
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#define CCSR_SSI_SISR_TFS 0x00000080
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#define CCSR_SSI_SISR_RFS 0x00000040
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#define CCSR_SSI_SISR_TLS 0x00000020
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#define CCSR_SSI_SISR_RLS 0x00000010
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#define CCSR_SSI_SISR_RFF1 0x00000008
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#define CCSR_SSI_SISR_RFF0 0x00000004
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#define CCSR_SSI_SISR_TFE1 0x00000002
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#define CCSR_SSI_SISR_TFE0 0x00000001
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#define CCSR_SSI_SIER_RFRC_EN 0x01000000
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#define CCSR_SSI_SIER_TFRC_EN 0x00800000
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#define CCSR_SSI_SIER_RDMAE 0x00400000
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#define CCSR_SSI_SIER_RIE 0x00200000
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#define CCSR_SSI_SIER_TDMAE 0x00100000
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#define CCSR_SSI_SIER_TIE 0x00080000
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#define CCSR_SSI_SIER_CMDAU_EN 0x00040000
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#define CCSR_SSI_SIER_CMDDU_EN 0x00020000
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#define CCSR_SSI_SIER_RXT_EN 0x00010000
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#define CCSR_SSI_SIER_RDR1_EN 0x00008000
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#define CCSR_SSI_SIER_RDR0_EN 0x00004000
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#define CCSR_SSI_SIER_TDE1_EN 0x00002000
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#define CCSR_SSI_SIER_TDE0_EN 0x00001000
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#define CCSR_SSI_SIER_ROE1_EN 0x00000800
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#define CCSR_SSI_SIER_ROE0_EN 0x00000400
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#define CCSR_SSI_SIER_TUE1_EN 0x00000200
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#define CCSR_SSI_SIER_TUE0_EN 0x00000100
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#define CCSR_SSI_SIER_TFS_EN 0x00000080
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#define CCSR_SSI_SIER_RFS_EN 0x00000040
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#define CCSR_SSI_SIER_TLS_EN 0x00000020
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#define CCSR_SSI_SIER_RLS_EN 0x00000010
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#define CCSR_SSI_SIER_RFF1_EN 0x00000008
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#define CCSR_SSI_SIER_RFF0_EN 0x00000004
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#define CCSR_SSI_SIER_TFE1_EN 0x00000002
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#define CCSR_SSI_SIER_TFE0_EN 0x00000001
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#define CCSR_SSI_STCR_TXBIT0 0x00000200
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#define CCSR_SSI_STCR_TFEN1 0x00000100
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#define CCSR_SSI_STCR_TFEN0 0x00000080
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#define CCSR_SSI_STCR_TFDIR 0x00000040
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#define CCSR_SSI_STCR_TXDIR 0x00000020
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#define CCSR_SSI_STCR_TSHFD 0x00000010
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#define CCSR_SSI_STCR_TSCKP 0x00000008
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#define CCSR_SSI_STCR_TFSI 0x00000004
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#define CCSR_SSI_STCR_TFSL 0x00000002
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#define CCSR_SSI_STCR_TEFS 0x00000001
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#define CCSR_SSI_SRCR_RXEXT 0x00000400
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#define CCSR_SSI_SRCR_RXBIT0 0x00000200
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#define CCSR_SSI_SRCR_RFEN1 0x00000100
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#define CCSR_SSI_SRCR_RFEN0 0x00000080
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#define CCSR_SSI_SRCR_RFDIR 0x00000040
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#define CCSR_SSI_SRCR_RXDIR 0x00000020
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#define CCSR_SSI_SRCR_RSHFD 0x00000010
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#define CCSR_SSI_SRCR_RSCKP 0x00000008
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#define CCSR_SSI_SRCR_RFSI 0x00000004
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#define CCSR_SSI_SRCR_RFSL 0x00000002
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#define CCSR_SSI_SRCR_REFS 0x00000001
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/* STCCR and SRCCR */
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#define CCSR_SSI_SxCCR_DIV2 0x00040000
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#define CCSR_SSI_SxCCR_PSR 0x00020000
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#define CCSR_SSI_SxCCR_WL_SHIFT 13
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#define CCSR_SSI_SxCCR_WL_MASK 0x0001E000
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#define CCSR_SSI_SxCCR_WL(x) \
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(((((x) / 2) - 1) << CCSR_SSI_SxCCR_WL_SHIFT) & CCSR_SSI_SxCCR_WL_MASK)
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#define CCSR_SSI_SxCCR_DC_SHIFT 8
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#define CCSR_SSI_SxCCR_DC_MASK 0x00001F00
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#define CCSR_SSI_SxCCR_DC(x) \
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((((x) - 1) << CCSR_SSI_SxCCR_DC_SHIFT) & CCSR_SSI_SxCCR_DC_MASK)
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#define CCSR_SSI_SxCCR_PM_SHIFT 0
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#define CCSR_SSI_SxCCR_PM_MASK 0x000000FF
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#define CCSR_SSI_SxCCR_PM(x) \
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((((x) - 1) << CCSR_SSI_SxCCR_PM_SHIFT) & CCSR_SSI_SxCCR_PM_MASK)
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/*
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* The xFCNT bits are read-only, and the xFWM bits are read/write. Use the
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* CCSR_SSI_SFCSR_xFCNTy() macros to read the FIFO counters, and use the
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* CCSR_SSI_SFCSR_xFWMy() macros to set the watermarks.
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*/
|
||||
#define CCSR_SSI_SFCSR_RFCNT1_SHIFT 28
|
||||
#define CCSR_SSI_SFCSR_RFCNT1_MASK 0xF0000000
|
||||
#define CCSR_SSI_SFCSR_RFCNT1(x) \
|
||||
(((x) & CCSR_SSI_SFCSR_RFCNT1_MASK) >> CCSR_SSI_SFCSR_RFCNT1_SHIFT)
|
||||
#define CCSR_SSI_SFCSR_TFCNT1_SHIFT 24
|
||||
#define CCSR_SSI_SFCSR_TFCNT1_MASK 0x0F000000
|
||||
#define CCSR_SSI_SFCSR_TFCNT1(x) \
|
||||
(((x) & CCSR_SSI_SFCSR_TFCNT1_MASK) >> CCSR_SSI_SFCSR_TFCNT1_SHIFT)
|
||||
#define CCSR_SSI_SFCSR_RFWM1_SHIFT 20
|
||||
#define CCSR_SSI_SFCSR_RFWM1_MASK 0x00F00000
|
||||
#define CCSR_SSI_SFCSR_RFWM1(x) \
|
||||
(((x) << CCSR_SSI_SFCSR_RFWM1_SHIFT) & CCSR_SSI_SFCSR_RFWM1_MASK)
|
||||
#define CCSR_SSI_SFCSR_TFWM1_SHIFT 16
|
||||
#define CCSR_SSI_SFCSR_TFWM1_MASK 0x000F0000
|
||||
#define CCSR_SSI_SFCSR_TFWM1(x) \
|
||||
(((x) << CCSR_SSI_SFCSR_TFWM1_SHIFT) & CCSR_SSI_SFCSR_TFWM1_MASK)
|
||||
#define CCSR_SSI_SFCSR_RFCNT0_SHIFT 12
|
||||
#define CCSR_SSI_SFCSR_RFCNT0_MASK 0x0000F000
|
||||
#define CCSR_SSI_SFCSR_RFCNT0(x) \
|
||||
(((x) & CCSR_SSI_SFCSR_RFCNT0_MASK) >> CCSR_SSI_SFCSR_RFCNT0_SHIFT)
|
||||
#define CCSR_SSI_SFCSR_TFCNT0_SHIFT 8
|
||||
#define CCSR_SSI_SFCSR_TFCNT0_MASK 0x00000F00
|
||||
#define CCSR_SSI_SFCSR_TFCNT0(x) \
|
||||
(((x) & CCSR_SSI_SFCSR_TFCNT0_MASK) >> CCSR_SSI_SFCSR_TFCNT0_SHIFT)
|
||||
#define CCSR_SSI_SFCSR_RFWM0_SHIFT 4
|
||||
#define CCSR_SSI_SFCSR_RFWM0_MASK 0x000000F0
|
||||
#define CCSR_SSI_SFCSR_RFWM0(x) \
|
||||
(((x) << CCSR_SSI_SFCSR_RFWM0_SHIFT) & CCSR_SSI_SFCSR_RFWM0_MASK)
|
||||
#define CCSR_SSI_SFCSR_TFWM0_SHIFT 0
|
||||
#define CCSR_SSI_SFCSR_TFWM0_MASK 0x0000000F
|
||||
#define CCSR_SSI_SFCSR_TFWM0(x) \
|
||||
(((x) << CCSR_SSI_SFCSR_TFWM0_SHIFT) & CCSR_SSI_SFCSR_TFWM0_MASK)
|
||||
|
||||
#define CCSR_SSI_STR_TEST 0x00008000
|
||||
#define CCSR_SSI_STR_RCK2TCK 0x00004000
|
||||
#define CCSR_SSI_STR_RFS2TFS 0x00002000
|
||||
#define CCSR_SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F)
|
||||
#define CCSR_SSI_STR_TXD2RXD 0x00000080
|
||||
#define CCSR_SSI_STR_TCK2RCK 0x00000040
|
||||
#define CCSR_SSI_STR_TFS2RFS 0x00000020
|
||||
#define CCSR_SSI_STR_TXSTATE(x) ((x) & 0x1F)
|
||||
|
||||
#define CCSR_SSI_SOR_CLKOFF 0x00000040
|
||||
#define CCSR_SSI_SOR_RX_CLR 0x00000020
|
||||
#define CCSR_SSI_SOR_TX_CLR 0x00000010
|
||||
#define CCSR_SSI_SOR_INIT 0x00000008
|
||||
#define CCSR_SSI_SOR_WAIT_SHIFT 1
|
||||
#define CCSR_SSI_SOR_WAIT_MASK 0x00000006
|
||||
#define CCSR_SSI_SOR_WAIT(x) (((x) & 3) << CCSR_SSI_SOR_WAIT_SHIFT)
|
||||
#define CCSR_SSI_SOR_SYNRST 0x00000001
|
||||
|
||||
/* Instantiation data for an SSI interface
|
||||
*
|
||||
* This structure contains all the information that the the SSI driver needs
|
||||
* to instantiate an SSI interface with ALSA. The machine driver should
|
||||
* create this structure, fill it in, call fsl_ssi_create_dai(), and then
|
||||
* delete the structure.
|
||||
*
|
||||
* id: which SSI this is (0, 1, etc. )
|
||||
* ssi: pointer to the SSI's registers
|
||||
* ssi_phys: physical address of the SSI registers
|
||||
* irq: IRQ of this SSI
|
||||
* dev: struct device, used to create the sysfs statistics file
|
||||
*/
|
||||
struct fsl_ssi_info {
|
||||
unsigned int id;
|
||||
struct ccsr_ssi __iomem *ssi;
|
||||
dma_addr_t ssi_phys;
|
||||
unsigned int irq;
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
struct snd_soc_cpu_dai *fsl_ssi_create_dai(struct fsl_ssi_info *ssi_info);
|
||||
void fsl_ssi_destroy_dai(struct snd_soc_cpu_dai *fsl_ssi_dai);
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user