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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (44 commits) qlge: Fix sparse warnings for tx ring indexes. qlge: Fix sparse warning regarding rx buffer queues. qlge: Fix sparse endian warning in ql_hw_csum_setup(). qlge: Fix sparse endian warning for inbound packet control block flags. qlge: Fix sparse warnings for byte swapping in qlge_ethool.c myri10ge: print MAC and serial number on probe failure pkt_sched: cls_u32: Fix locking in u32_change() iucv: fix cpu hotplug af_iucv: Free iucv path/socket in path_pending callback af_iucv: avoid left over IUCV connections from failing connects af_iucv: New error return codes for connect() net/ehea: bitops work on unsigned longs Revert "net: Fix for initial link state in 2.6.28" tcp: Kill extraneous SPLICE_F_NONBLOCK checks. tcp: don't mask EOF and socket errors on nonblocking splice receive dccp: Integrate the TFRC library with DCCP dccp: Clean up ccid.c after integration of CCID plugins dccp: Lockless integration of CCID congestion-control plugins qeth: get rid of extra argument after printk to dev_* conversion qeth: No large send using EDDP for HiperSockets. ...
This commit is contained in:
@@ -1519,7 +1519,7 @@ static int decodeFVteln(char *teln, unsigned long *bmaskp, int *activep)
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int digit2 = 0;
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if (!isdigit(*s)) return -3;
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while (isdigit(*s)) { digit1 = digit1*10 + (*s - '0'); s++; }
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if (digit1 <= 0 && digit1 > 30) return -4;
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if (digit1 <= 0 || digit1 > 30) return -4;
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if (*s == 0 || *s == ',' || *s == ' ') {
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bmask |= (1 << digit1);
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digit1 = 0;
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@@ -1530,7 +1530,7 @@ static int decodeFVteln(char *teln, unsigned long *bmaskp, int *activep)
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s++;
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if (!isdigit(*s)) return -3;
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while (isdigit(*s)) { digit2 = digit2*10 + (*s - '0'); s++; }
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if (digit2 <= 0 && digit2 > 30) return -4;
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if (digit2 <= 0 || digit2 > 30) return -4;
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if (*s == 0 || *s == ',' || *s == ' ') {
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if (digit1 > digit2)
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for (i = digit2; i <= digit1 ; i++)
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+72
-47
@@ -66,6 +66,7 @@
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#include <linux/mm.h>
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#include <linux/highmem.h>
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#include <linux/sockios.h>
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#include <linux/firmware.h>
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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
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#include <linux/if_vlan.h>
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@@ -186,8 +187,6 @@ MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
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#define MAX_RODATA_LEN 8*1024
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#define MAX_DATA_LEN 2*1024
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#include "acenic_firmware.h"
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#ifndef tigon2FwReleaseLocal
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#define tigon2FwReleaseLocal 0
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#endif
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@@ -417,6 +416,10 @@ static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
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MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
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#ifndef CONFIG_ACENIC_OMIT_TIGON_I
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MODULE_FIRMWARE("acenic/tg1.bin");
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#endif
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MODULE_FIRMWARE("acenic/tg2.bin");
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module_param_array_named(link, link_state, int, NULL, 0);
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module_param_array(trace, int, NULL, 0);
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@@ -943,8 +946,8 @@ static int __devinit ace_init(struct net_device *dev)
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case 4:
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case 5:
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printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
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tig_ver, tigonFwReleaseMajor, tigonFwReleaseMinor,
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tigonFwReleaseFix);
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tig_ver, ap->firmware_major, ap->firmware_minor,
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ap->firmware_fix);
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writel(0, ®s->LocalCtrl);
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ap->version = 1;
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ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
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@@ -952,8 +955,8 @@ static int __devinit ace_init(struct net_device *dev)
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#endif
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case 6:
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printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
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tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
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tigon2FwReleaseFix);
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tig_ver, ap->firmware_major, ap->firmware_minor,
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ap->firmware_fix);
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writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl);
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readl(®s->CpuBCtrl); /* PCI write posting */
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/*
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@@ -1205,7 +1208,9 @@ static int __devinit ace_init(struct net_device *dev)
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memset(ap->info, 0, sizeof(struct ace_info));
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memset(ap->skb, 0, sizeof(struct ace_skb));
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ace_load_firmware(dev);
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if (ace_load_firmware(dev))
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goto init_error;
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ap->fw_running = 0;
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tmp_ptr = ap->info_dma;
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@@ -1441,10 +1446,7 @@ static int __devinit ace_init(struct net_device *dev)
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if (ap->version >= 2)
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writel(tmp, ®s->TuneFastLink);
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if (ACE_IS_TIGON_I(ap))
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writel(tigonFwStartAddr, ®s->Pc);
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if (ap->version == 2)
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writel(tigon2FwStartAddr, ®s->Pc);
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writel(ap->firmware_start, ®s->Pc);
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writel(0, ®s->Mb0Lo);
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@@ -2761,8 +2763,8 @@ static void ace_get_drvinfo(struct net_device *dev,
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strlcpy(info->driver, "acenic", sizeof(info->driver));
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snprintf(info->version, sizeof(info->version), "%i.%i.%i",
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tigonFwReleaseMajor, tigonFwReleaseMinor,
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tigonFwReleaseFix);
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ap->firmware_major, ap->firmware_minor,
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ap->firmware_fix);
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if (ap->pdev)
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strlcpy(info->bus_info, pci_name(ap->pdev),
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@@ -2869,11 +2871,10 @@ static struct net_device_stats *ace_get_stats(struct net_device *dev)
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}
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static void __devinit ace_copy(struct ace_regs __iomem *regs, void *src,
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u32 dest, int size)
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static void __devinit ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
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u32 dest, int size)
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{
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void __iomem *tdest;
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u32 *wsrc;
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short tsize, i;
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if (size <= 0)
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@@ -2885,20 +2886,15 @@ static void __devinit ace_copy(struct ace_regs __iomem *regs, void *src,
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tdest = (void __iomem *) ®s->Window +
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(dest & (ACE_WINDOW_SIZE - 1));
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writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
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/*
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* This requires byte swapping on big endian, however
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* writel does that for us
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*/
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wsrc = src;
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for (i = 0; i < (tsize / 4); i++) {
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writel(wsrc[i], tdest + i*4);
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/* Firmware is big-endian */
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writel(be32_to_cpup(src), tdest);
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src++;
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tdest += 4;
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dest += 4;
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size -= 4;
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}
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dest += tsize;
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src += tsize;
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size -= tsize;
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}
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return;
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}
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@@ -2937,8 +2933,13 @@ static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int siz
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*/
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static int __devinit ace_load_firmware(struct net_device *dev)
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{
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const struct firmware *fw;
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const char *fw_name = "acenic/tg2.bin";
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struct ace_private *ap = netdev_priv(dev);
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struct ace_regs __iomem *regs = ap->regs;
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const __be32 *fw_data;
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u32 load_addr;
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int ret;
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if (!(readl(®s->CpuCtrl) & CPU_HALTED)) {
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printk(KERN_ERR "%s: trying to download firmware while the "
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@@ -2946,28 +2947,52 @@ static int __devinit ace_load_firmware(struct net_device *dev)
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return -EFAULT;
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}
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/*
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* Do not try to clear more than 512KB or we end up seeing
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* funny things on NICs with only 512KB SRAM
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*/
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ace_clear(regs, 0x2000, 0x80000-0x2000);
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if (ACE_IS_TIGON_I(ap)) {
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ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
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ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
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ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
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tigonFwRodataLen);
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ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
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ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
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}else if (ap->version == 2) {
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ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
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ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
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ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
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ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
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tigon2FwRodataLen);
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ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
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if (ACE_IS_TIGON_I(ap))
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fw_name = "acenic/tg1.bin";
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ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
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if (ret) {
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printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
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ap->name, fw_name);
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return ret;
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}
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return 0;
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fw_data = (void *)fw->data;
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/* Firmware blob starts with version numbers, followed by
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load and start address. Remainder is the blob to be loaded
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contiguously from load address. We don't bother to represent
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the BSS/SBSS sections any more, since we were clearing the
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whole thing anyway. */
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ap->firmware_major = fw->data[0];
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ap->firmware_minor = fw->data[1];
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ap->firmware_fix = fw->data[2];
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ap->firmware_start = be32_to_cpu(fw_data[1]);
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if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
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printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
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ap->name, ap->firmware_start, fw_name);
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ret = -EINVAL;
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goto out;
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}
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load_addr = be32_to_cpu(fw_data[2]);
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if (load_addr < 0x4000 || load_addr >= 0x80000) {
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printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
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ap->name, load_addr, fw_name);
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ret = -EINVAL;
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goto out;
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}
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/*
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* Do not try to clear more than 512KiB or we end up seeing
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* funny things on NICs with only 512KiB SRAM
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*/
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ace_clear(regs, 0x2000, 0x80000-0x2000);
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ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
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out:
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release_firmware(fw);
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return ret;
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}
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@@ -694,6 +694,10 @@ struct ace_private
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u32 last_tx, last_std_rx, last_mini_rx;
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#endif
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int pci_using_dac;
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u8 firmware_major;
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u8 firmware_minor;
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u8 firmware_fix;
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u32 firmware_start;
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};
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+134
-134
File diff suppressed because it is too large
Load Diff
@@ -478,7 +478,7 @@ struct ehea_port {
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int num_add_tx_qps;
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int num_mcs;
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int resets;
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u64 flags;
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unsigned long flags;
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u64 mac_addr;
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u32 logical_port_id;
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u32 port_speed;
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@@ -510,7 +510,6 @@ void ehea_set_ethtool_ops(struct net_device *netdev);
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int ehea_sense_port_attr(struct ehea_port *port);
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int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);
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|
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extern u64 ehea_driver_flags;
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extern struct work_struct ehea_rereg_mr_task;
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#endif /* __EHEA_H__ */
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@@ -99,7 +99,7 @@ MODULE_PARM_DESC(use_lro, " Large Receive Offload, 1: enable, 0: disable, "
|
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|
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static int port_name_cnt;
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static LIST_HEAD(adapter_list);
|
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u64 ehea_driver_flags;
|
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static unsigned long ehea_driver_flags;
|
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struct work_struct ehea_rereg_mr_task;
|
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static DEFINE_MUTEX(dlpar_mem_lock);
|
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struct ehea_fw_handle_array ehea_fw_handles;
|
||||
|
||||
@@ -944,7 +944,7 @@ static void enc28j60_hw_rx(struct net_device *ndev)
|
||||
if (netif_msg_rx_status(priv))
|
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enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
|
||||
|
||||
if (!RSV_GETBIT(rxstat, RSV_RXOK)) {
|
||||
if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
|
||||
if (netif_msg_rx_err(priv))
|
||||
dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
|
||||
ndev->stats.rx_errors++;
|
||||
@@ -952,6 +952,8 @@ static void enc28j60_hw_rx(struct net_device *ndev)
|
||||
ndev->stats.rx_crc_errors++;
|
||||
if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
|
||||
ndev->stats.rx_frame_errors++;
|
||||
if (len > MAX_FRAMELEN)
|
||||
ndev->stats.rx_over_errors++;
|
||||
} else {
|
||||
skb = dev_alloc_skb(len + NET_IP_ALIGN);
|
||||
if (!skb) {
|
||||
|
||||
@@ -75,7 +75,7 @@
|
||||
#include "myri10ge_mcp.h"
|
||||
#include "myri10ge_mcp_gen_header.h"
|
||||
|
||||
#define MYRI10GE_VERSION_STR "1.4.4-1.395"
|
||||
#define MYRI10GE_VERSION_STR "1.4.4-1.398"
|
||||
|
||||
MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
|
||||
MODULE_AUTHOR("Maintainer: help@myri.com");
|
||||
@@ -3929,6 +3929,10 @@ abort_with_firmware:
|
||||
myri10ge_dummy_rdma(mgp, 0);
|
||||
|
||||
abort_with_ioremap:
|
||||
if (mgp->mac_addr_string != NULL)
|
||||
dev_err(&pdev->dev,
|
||||
"myri10ge_probe() failed: MAC=%s, SN=%ld\n",
|
||||
mgp->mac_addr_string, mgp->serial_number);
|
||||
iounmap(mgp->sram);
|
||||
|
||||
abort_with_mtrr:
|
||||
|
||||
+17
-40
@@ -818,15 +818,6 @@ struct tx_doorbell_context {
|
||||
};
|
||||
|
||||
/* DATA STRUCTURES SHARED WITH HARDWARE. */
|
||||
|
||||
struct bq_element {
|
||||
u32 addr_lo;
|
||||
#define BQ_END 0x00000001
|
||||
#define BQ_CONT 0x00000002
|
||||
#define BQ_MASK 0x00000003
|
||||
u32 addr_hi;
|
||||
} __attribute((packed));
|
||||
|
||||
struct tx_buf_desc {
|
||||
__le64 addr;
|
||||
__le32 len;
|
||||
@@ -860,8 +851,8 @@ struct ob_mac_iocb_req {
|
||||
__le16 frame_len;
|
||||
#define OB_MAC_IOCB_LEN_MASK 0x3ffff
|
||||
__le16 reserved2;
|
||||
__le32 tid;
|
||||
__le32 txq_idx;
|
||||
u32 tid;
|
||||
u32 txq_idx;
|
||||
__le32 reserved3;
|
||||
__le16 vlan_tci;
|
||||
__le16 reserved4;
|
||||
@@ -880,8 +871,8 @@ struct ob_mac_iocb_rsp {
|
||||
u8 flags2; /* */
|
||||
u8 flags3; /* */
|
||||
#define OB_MAC_IOCB_RSP_B 0x80 /* */
|
||||
__le32 tid;
|
||||
__le32 txq_idx;
|
||||
u32 tid;
|
||||
u32 txq_idx;
|
||||
__le32 reserved[13];
|
||||
} __attribute((packed));
|
||||
|
||||
@@ -903,8 +894,8 @@ struct ob_mac_tso_iocb_req {
|
||||
#define OB_MAC_TSO_IOCB_V 0x04
|
||||
__le32 reserved1[2];
|
||||
__le32 frame_len;
|
||||
__le32 tid;
|
||||
__le32 txq_idx;
|
||||
u32 tid;
|
||||
u32 txq_idx;
|
||||
__le16 total_hdrs_len;
|
||||
__le16 net_trans_offset;
|
||||
#define OB_MAC_TRANSPORT_HDR_SHIFT 6
|
||||
@@ -925,8 +916,8 @@ struct ob_mac_tso_iocb_rsp {
|
||||
u8 flags2; /* */
|
||||
u8 flags3; /* */
|
||||
#define OB_MAC_TSO_IOCB_RSP_B 0x8000
|
||||
__le32 tid;
|
||||
__le32 txq_idx;
|
||||
u32 tid;
|
||||
u32 txq_idx;
|
||||
__le32 reserved2[13];
|
||||
} __attribute((packed));
|
||||
|
||||
@@ -979,10 +970,11 @@ struct ib_mac_iocb_rsp {
|
||||
|
||||
__le16 reserved1;
|
||||
__le32 reserved2[6];
|
||||
__le32 flags4;
|
||||
#define IB_MAC_IOCB_RSP_HV 0x20000000 /* */
|
||||
#define IB_MAC_IOCB_RSP_HS 0x40000000 /* */
|
||||
#define IB_MAC_IOCB_RSP_HL 0x80000000 /* */
|
||||
u8 reserved3[3];
|
||||
u8 flags4;
|
||||
#define IB_MAC_IOCB_RSP_HV 0x20
|
||||
#define IB_MAC_IOCB_RSP_HS 0x40
|
||||
#define IB_MAC_IOCB_RSP_HL 0x80
|
||||
__le32 hdr_len; /* */
|
||||
__le32 hdr_addr_lo; /* */
|
||||
__le32 hdr_addr_hi; /* */
|
||||
@@ -1126,7 +1118,7 @@ struct map_list {
|
||||
struct tx_ring_desc {
|
||||
struct sk_buff *skb;
|
||||
struct ob_mac_iocb_req *queue_entry;
|
||||
int index;
|
||||
u32 index;
|
||||
struct oal oal;
|
||||
struct map_list map[MAX_SKB_FRAGS + 1];
|
||||
int map_cnt;
|
||||
@@ -1138,8 +1130,8 @@ struct bq_desc {
|
||||
struct page *lbq_page;
|
||||
struct sk_buff *skb;
|
||||
} p;
|
||||
struct bq_element *bq;
|
||||
int index;
|
||||
__le64 *addr;
|
||||
u32 index;
|
||||
DECLARE_PCI_UNMAP_ADDR(mapaddr);
|
||||
DECLARE_PCI_UNMAP_LEN(maplen);
|
||||
};
|
||||
@@ -1189,7 +1181,7 @@ struct rx_ring {
|
||||
u32 cq_size;
|
||||
u32 cq_len;
|
||||
u16 cq_id;
|
||||
u32 *prod_idx_sh_reg; /* Shadowed producer register. */
|
||||
volatile __le32 *prod_idx_sh_reg; /* Shadowed producer register. */
|
||||
dma_addr_t prod_idx_sh_reg_dma;
|
||||
void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */
|
||||
u32 cnsmr_idx; /* current sw idx */
|
||||
@@ -1467,21 +1459,6 @@ static inline void ql_write_db_reg(u32 val, void __iomem *addr)
|
||||
mmiowb();
|
||||
}
|
||||
|
||||
/*
|
||||
* Shadow Registers:
|
||||
* Outbound queues have a consumer index that is maintained by the chip.
|
||||
* Inbound queues have a producer index that is maintained by the chip.
|
||||
* For lower overhead, these registers are "shadowed" to host memory
|
||||
* which allows the device driver to track the queue progress without
|
||||
* PCI reads. When an entry is placed on an inbound queue, the chip will
|
||||
* update the relevant index register and then copy the value to the
|
||||
* shadow register in host memory.
|
||||
*/
|
||||
static inline unsigned int ql_read_sh_reg(const volatile void *addr)
|
||||
{
|
||||
return *(volatile unsigned int __force *)addr;
|
||||
}
|
||||
|
||||
extern char qlge_driver_name[];
|
||||
extern const char qlge_driver_version[];
|
||||
extern const struct ethtool_ops qlge_ethtool_ops;
|
||||
|
||||
@@ -821,14 +821,11 @@ void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp)
|
||||
le16_to_cpu(ib_mac_rsp->vlan_id));
|
||||
|
||||
printk(KERN_ERR PFX "flags4 = %s%s%s.\n",
|
||||
le32_to_cpu(ib_mac_rsp->
|
||||
flags4) & IB_MAC_IOCB_RSP_HV ? "HV " : "",
|
||||
le32_to_cpu(ib_mac_rsp->
|
||||
flags4) & IB_MAC_IOCB_RSP_HS ? "HS " : "",
|
||||
le32_to_cpu(ib_mac_rsp->
|
||||
flags4) & IB_MAC_IOCB_RSP_HL ? "HL " : "");
|
||||
ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV ? "HV " : "",
|
||||
ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS ? "HS " : "",
|
||||
ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HL ? "HL " : "");
|
||||
|
||||
if (le32_to_cpu(ib_mac_rsp->flags4) & IB_MAC_IOCB_RSP_HV) {
|
||||
if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) {
|
||||
printk(KERN_ERR PFX "hdr length = %d.\n",
|
||||
le32_to_cpu(ib_mac_rsp->hdr_len));
|
||||
printk(KERN_ERR PFX "hdr addr_hi = 0x%x.\n",
|
||||
|
||||
@@ -56,9 +56,9 @@ static int ql_update_ring_coalescing(struct ql_adapter *qdev)
|
||||
for (i = 1; i < qdev->rss_ring_first_cq_id; i++, rx_ring++) {
|
||||
rx_ring = &qdev->rx_ring[i];
|
||||
cqicb = (struct cqicb *)rx_ring;
|
||||
cqicb->irq_delay = le16_to_cpu(qdev->tx_coalesce_usecs);
|
||||
cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
|
||||
cqicb->pkt_delay =
|
||||
le16_to_cpu(qdev->tx_max_coalesced_frames);
|
||||
cpu_to_le16(qdev->tx_max_coalesced_frames);
|
||||
cqicb->flags = FLAGS_LI;
|
||||
status = ql_write_cfg(qdev, cqicb, sizeof(cqicb),
|
||||
CFG_LCQ, rx_ring->cq_id);
|
||||
@@ -79,9 +79,9 @@ static int ql_update_ring_coalescing(struct ql_adapter *qdev)
|
||||
i++) {
|
||||
rx_ring = &qdev->rx_ring[i];
|
||||
cqicb = (struct cqicb *)rx_ring;
|
||||
cqicb->irq_delay = le16_to_cpu(qdev->rx_coalesce_usecs);
|
||||
cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
|
||||
cqicb->pkt_delay =
|
||||
le16_to_cpu(qdev->rx_max_coalesced_frames);
|
||||
cpu_to_le16(qdev->rx_max_coalesced_frames);
|
||||
cqicb->flags = FLAGS_LI;
|
||||
status = ql_write_cfg(qdev, cqicb, sizeof(cqicb),
|
||||
CFG_LCQ, rx_ring->cq_id);
|
||||
|
||||
@@ -257,7 +257,7 @@ int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
|
||||
{
|
||||
status =
|
||||
ql_wait_reg_rdy(qdev,
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
|
||||
@@ -265,13 +265,13 @@ int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
|
||||
MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
|
||||
status =
|
||||
ql_wait_reg_rdy(qdev,
|
||||
MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
|
||||
MAC_ADDR_IDX, MAC_ADDR_MR, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
*value++ = ql_read32(qdev, MAC_ADDR_DATA);
|
||||
status =
|
||||
ql_wait_reg_rdy(qdev,
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
|
||||
@@ -279,14 +279,14 @@ int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
|
||||
MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
|
||||
status =
|
||||
ql_wait_reg_rdy(qdev,
|
||||
MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
|
||||
MAC_ADDR_IDX, MAC_ADDR_MR, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
*value++ = ql_read32(qdev, MAC_ADDR_DATA);
|
||||
if (type == MAC_ADDR_TYPE_CAM_MAC) {
|
||||
status =
|
||||
ql_wait_reg_rdy(qdev,
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
|
||||
@@ -294,7 +294,7 @@ int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
|
||||
MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
|
||||
status =
|
||||
ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
|
||||
MAC_ADDR_MR, MAC_ADDR_E);
|
||||
MAC_ADDR_MR, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
*value++ = ql_read32(qdev, MAC_ADDR_DATA);
|
||||
@@ -344,7 +344,7 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
|
||||
|
||||
status =
|
||||
ql_wait_reg_rdy(qdev,
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
|
||||
@@ -353,7 +353,7 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
|
||||
ql_write32(qdev, MAC_ADDR_DATA, lower);
|
||||
status =
|
||||
ql_wait_reg_rdy(qdev,
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
|
||||
@@ -362,7 +362,7 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
|
||||
ql_write32(qdev, MAC_ADDR_DATA, upper);
|
||||
status =
|
||||
ql_wait_reg_rdy(qdev,
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
|
||||
@@ -400,7 +400,7 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
|
||||
|
||||
status =
|
||||
ql_wait_reg_rdy(qdev,
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
|
||||
MAC_ADDR_IDX, MAC_ADDR_MW, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
|
||||
@@ -431,13 +431,13 @@ int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
|
||||
if (status)
|
||||
goto exit;
|
||||
|
||||
status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, RT_IDX_E);
|
||||
status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
|
||||
ql_write32(qdev, RT_IDX,
|
||||
RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
|
||||
status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, RT_IDX_E);
|
||||
status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
|
||||
if (status)
|
||||
goto exit;
|
||||
*value = ql_read32(qdev, RT_DATA);
|
||||
@@ -874,7 +874,6 @@ static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
|
||||
{
|
||||
int clean_idx = rx_ring->lbq_clean_idx;
|
||||
struct bq_desc *lbq_desc;
|
||||
struct bq_element *bq;
|
||||
u64 map;
|
||||
int i;
|
||||
|
||||
@@ -884,7 +883,6 @@ static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
|
||||
"lbq: try cleaning clean_idx = %d.\n",
|
||||
clean_idx);
|
||||
lbq_desc = &rx_ring->lbq[clean_idx];
|
||||
bq = lbq_desc->bq;
|
||||
if (lbq_desc->p.lbq_page == NULL) {
|
||||
QPRINTK(qdev, RX_STATUS, DEBUG,
|
||||
"lbq: getting new page for index %d.\n",
|
||||
@@ -906,10 +904,7 @@ static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
|
||||
}
|
||||
pci_unmap_addr_set(lbq_desc, mapaddr, map);
|
||||
pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
|
||||
bq->addr_lo = /*lbq_desc->addr_lo = */
|
||||
cpu_to_le32(map);
|
||||
bq->addr_hi = /*lbq_desc->addr_hi = */
|
||||
cpu_to_le32(map >> 32);
|
||||
*lbq_desc->addr = cpu_to_le64(map);
|
||||
}
|
||||
clean_idx++;
|
||||
if (clean_idx == rx_ring->lbq_len)
|
||||
@@ -934,7 +929,6 @@ static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
|
||||
{
|
||||
int clean_idx = rx_ring->sbq_clean_idx;
|
||||
struct bq_desc *sbq_desc;
|
||||
struct bq_element *bq;
|
||||
u64 map;
|
||||
int i;
|
||||
|
||||
@@ -944,7 +938,6 @@ static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
|
||||
QPRINTK(qdev, RX_STATUS, DEBUG,
|
||||
"sbq: try cleaning clean_idx = %d.\n",
|
||||
clean_idx);
|
||||
bq = sbq_desc->bq;
|
||||
if (sbq_desc->p.skb == NULL) {
|
||||
QPRINTK(qdev, RX_STATUS, DEBUG,
|
||||
"sbq: getting new skb for index %d.\n",
|
||||
@@ -963,11 +956,15 @@ static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
|
||||
sbq_desc->p.skb->data,
|
||||
rx_ring->sbq_buf_size /
|
||||
2, PCI_DMA_FROMDEVICE);
|
||||
if (pci_dma_mapping_error(qdev->pdev, map)) {
|
||||
QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
|
||||
rx_ring->sbq_clean_idx = clean_idx;
|
||||
return;
|
||||
}
|
||||
pci_unmap_addr_set(sbq_desc, mapaddr, map);
|
||||
pci_unmap_len_set(sbq_desc, maplen,
|
||||
rx_ring->sbq_buf_size / 2);
|
||||
bq->addr_lo = cpu_to_le32(map);
|
||||
bq->addr_hi = cpu_to_le32(map >> 32);
|
||||
*sbq_desc->addr = cpu_to_le64(map);
|
||||
}
|
||||
|
||||
clean_idx++;
|
||||
@@ -1303,6 +1300,11 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
|
||||
"No skb available, drop the packet.\n");
|
||||
return NULL;
|
||||
}
|
||||
pci_unmap_page(qdev->pdev,
|
||||
pci_unmap_addr(lbq_desc,
|
||||
mapaddr),
|
||||
pci_unmap_len(lbq_desc, maplen),
|
||||
PCI_DMA_FROMDEVICE);
|
||||
skb_reserve(skb, NET_IP_ALIGN);
|
||||
QPRINTK(qdev, RX_STATUS, DEBUG,
|
||||
"%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
|
||||
@@ -1330,7 +1332,7 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
|
||||
* eventually be in trouble.
|
||||
*/
|
||||
int size, offset, i = 0;
|
||||
struct bq_element *bq, bq_array[8];
|
||||
__le64 *bq, bq_array[8];
|
||||
sbq_desc = ql_get_curr_sbuf(rx_ring);
|
||||
pci_unmap_single(qdev->pdev,
|
||||
pci_unmap_addr(sbq_desc, mapaddr),
|
||||
@@ -1356,16 +1358,10 @@ static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
|
||||
} else {
|
||||
QPRINTK(qdev, RX_STATUS, DEBUG,
|
||||
"Headers in small, %d bytes of data in chain of large.\n", length);
|
||||
bq = (struct bq_element *)sbq_desc->p.skb->data;
|
||||
bq = (__le64 *)sbq_desc->p.skb->data;
|
||||
}
|
||||
while (length > 0) {
|
||||
lbq_desc = ql_get_curr_lbuf(rx_ring);
|
||||
if ((bq->addr_lo & ~BQ_MASK) != lbq_desc->bq->addr_lo) {
|
||||
QPRINTK(qdev, RX_STATUS, ERR,
|
||||
"Panic!!! bad large buffer address, expected 0x%.08x, got 0x%.08x.\n",
|
||||
lbq_desc->bq->addr_lo, bq->addr_lo);
|
||||
return NULL;
|
||||
}
|
||||
pci_unmap_page(qdev->pdev,
|
||||
pci_unmap_addr(lbq_desc,
|
||||
mapaddr),
|
||||
@@ -1549,7 +1545,7 @@ static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
|
||||
static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
|
||||
{
|
||||
struct ql_adapter *qdev = rx_ring->qdev;
|
||||
u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
|
||||
u32 prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg);
|
||||
struct ob_mac_iocb_rsp *net_rsp = NULL;
|
||||
int count = 0;
|
||||
|
||||
@@ -1575,7 +1571,7 @@ static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
|
||||
}
|
||||
count++;
|
||||
ql_update_cq(rx_ring);
|
||||
prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
|
||||
prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg);
|
||||
}
|
||||
ql_write_cq_idx(rx_ring);
|
||||
if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
|
||||
@@ -1595,7 +1591,7 @@ static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
|
||||
static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
|
||||
{
|
||||
struct ql_adapter *qdev = rx_ring->qdev;
|
||||
u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
|
||||
u32 prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg);
|
||||
struct ql_net_rsp_iocb *net_rsp;
|
||||
int count = 0;
|
||||
|
||||
@@ -1628,7 +1624,7 @@ static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
|
||||
}
|
||||
count++;
|
||||
ql_update_cq(rx_ring);
|
||||
prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
|
||||
prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg);
|
||||
if (count == budget)
|
||||
break;
|
||||
}
|
||||
@@ -1791,7 +1787,7 @@ static irqreturn_t qlge_isr(int irq, void *dev_id)
|
||||
* Check the default queue and wake handler if active.
|
||||
*/
|
||||
rx_ring = &qdev->rx_ring[0];
|
||||
if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
|
||||
if (le32_to_cpu(*rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
|
||||
QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
|
||||
ql_disable_completion_interrupt(qdev, intr_context->intr);
|
||||
queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
|
||||
@@ -1805,7 +1801,7 @@ static irqreturn_t qlge_isr(int irq, void *dev_id)
|
||||
*/
|
||||
for (i = 1; i < qdev->rx_ring_count; i++) {
|
||||
rx_ring = &qdev->rx_ring[i];
|
||||
if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
|
||||
if (le32_to_cpu(*rx_ring->prod_idx_sh_reg) !=
|
||||
rx_ring->cnsmr_idx) {
|
||||
QPRINTK(qdev, INTR, INFO,
|
||||
"Waking handler for rx_ring[%d].\n", i);
|
||||
@@ -1874,7 +1870,7 @@ static void ql_hw_csum_setup(struct sk_buff *skb,
|
||||
{
|
||||
int len;
|
||||
struct iphdr *iph = ip_hdr(skb);
|
||||
u16 *check;
|
||||
__sum16 *check;
|
||||
mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
|
||||
mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
|
||||
mac_iocb_ptr->net_trans_offset =
|
||||
@@ -2083,8 +2079,6 @@ static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring
|
||||
put_page(lbq_desc->p.lbq_page);
|
||||
lbq_desc->p.lbq_page = NULL;
|
||||
}
|
||||
lbq_desc->bq->addr_lo = 0;
|
||||
lbq_desc->bq->addr_hi = 0;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -2097,12 +2091,12 @@ static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
|
||||
int i;
|
||||
struct bq_desc *lbq_desc;
|
||||
u64 map;
|
||||
struct bq_element *bq = rx_ring->lbq_base;
|
||||
__le64 *bq = rx_ring->lbq_base;
|
||||
|
||||
for (i = 0; i < rx_ring->lbq_len; i++) {
|
||||
lbq_desc = &rx_ring->lbq[i];
|
||||
memset(lbq_desc, 0, sizeof(lbq_desc));
|
||||
lbq_desc->bq = bq;
|
||||
lbq_desc->addr = bq;
|
||||
lbq_desc->index = i;
|
||||
lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
|
||||
if (unlikely(!lbq_desc->p.lbq_page)) {
|
||||
@@ -2119,8 +2113,7 @@ static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
|
||||
}
|
||||
pci_unmap_addr_set(lbq_desc, mapaddr, map);
|
||||
pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
|
||||
bq->addr_lo = cpu_to_le32(map);
|
||||
bq->addr_hi = cpu_to_le32(map >> 32);
|
||||
*lbq_desc->addr = cpu_to_le64(map);
|
||||
}
|
||||
bq++;
|
||||
}
|
||||
@@ -2149,13 +2142,6 @@ static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring
|
||||
dev_kfree_skb(sbq_desc->p.skb);
|
||||
sbq_desc->p.skb = NULL;
|
||||
}
|
||||
if (sbq_desc->bq == NULL) {
|
||||
QPRINTK(qdev, IFUP, ERR, "sbq_desc->bq %d is NULL.\n",
|
||||
i);
|
||||
return;
|
||||
}
|
||||
sbq_desc->bq->addr_lo = 0;
|
||||
sbq_desc->bq->addr_hi = 0;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -2167,13 +2153,13 @@ static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
|
||||
struct bq_desc *sbq_desc;
|
||||
struct sk_buff *skb;
|
||||
u64 map;
|
||||
struct bq_element *bq = rx_ring->sbq_base;
|
||||
__le64 *bq = rx_ring->sbq_base;
|
||||
|
||||
for (i = 0; i < rx_ring->sbq_len; i++) {
|
||||
sbq_desc = &rx_ring->sbq[i];
|
||||
memset(sbq_desc, 0, sizeof(sbq_desc));
|
||||
sbq_desc->index = i;
|
||||
sbq_desc->bq = bq;
|
||||
sbq_desc->addr = bq;
|
||||
skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
|
||||
if (unlikely(!skb)) {
|
||||
/* Better luck next round */
|
||||
@@ -2199,10 +2185,7 @@ static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
|
||||
}
|
||||
pci_unmap_addr_set(sbq_desc, mapaddr, map);
|
||||
pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
|
||||
bq->addr_lo = /*sbq_desc->addr_lo = */
|
||||
cpu_to_le32(map);
|
||||
bq->addr_hi = /*sbq_desc->addr_hi = */
|
||||
cpu_to_le32(map >> 32);
|
||||
*sbq_desc->addr = cpu_to_le64(map);
|
||||
bq++;
|
||||
}
|
||||
return 0;
|
||||
@@ -2481,7 +2464,8 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
|
||||
memset((void *)cqicb, 0, sizeof(struct cqicb));
|
||||
cqicb->msix_vect = rx_ring->irq;
|
||||
|
||||
cqicb->len = cpu_to_le16(rx_ring->cq_len | LEN_V | LEN_CPP_CONT);
|
||||
bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
|
||||
cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
|
||||
|
||||
cqicb->addr_lo = cpu_to_le32(rx_ring->cq_base_dma);
|
||||
cqicb->addr_hi = cpu_to_le32((u64) rx_ring->cq_base_dma >> 32);
|
||||
@@ -2503,8 +2487,11 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
|
||||
cpu_to_le32(rx_ring->lbq_base_indirect_dma);
|
||||
cqicb->lbq_addr_hi =
|
||||
cpu_to_le32((u64) rx_ring->lbq_base_indirect_dma >> 32);
|
||||
cqicb->lbq_buf_size = cpu_to_le32(rx_ring->lbq_buf_size);
|
||||
bq_len = (u16) rx_ring->lbq_len;
|
||||
bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
|
||||
(u16) rx_ring->lbq_buf_size;
|
||||
cqicb->lbq_buf_size = cpu_to_le16(bq_len);
|
||||
bq_len = (rx_ring->lbq_len == 65536) ? 0 :
|
||||
(u16) rx_ring->lbq_len;
|
||||
cqicb->lbq_len = cpu_to_le16(bq_len);
|
||||
rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
|
||||
rx_ring->lbq_curr_idx = 0;
|
||||
@@ -2520,7 +2507,8 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
|
||||
cpu_to_le32((u64) rx_ring->sbq_base_indirect_dma >> 32);
|
||||
cqicb->sbq_buf_size =
|
||||
cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
|
||||
bq_len = (u16) rx_ring->sbq_len;
|
||||
bq_len = (rx_ring->sbq_len == 65536) ? 0 :
|
||||
(u16) rx_ring->sbq_len;
|
||||
cqicb->sbq_len = cpu_to_le16(bq_len);
|
||||
rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
|
||||
rx_ring->sbq_curr_idx = 0;
|
||||
@@ -3341,11 +3329,11 @@ static int ql_configure_rings(struct ql_adapter *qdev)
|
||||
rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
|
||||
rx_ring->lbq_len = NUM_LARGE_BUFFERS;
|
||||
rx_ring->lbq_size =
|
||||
rx_ring->lbq_len * sizeof(struct bq_element);
|
||||
rx_ring->lbq_len * sizeof(__le64);
|
||||
rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
|
||||
rx_ring->sbq_len = NUM_SMALL_BUFFERS;
|
||||
rx_ring->sbq_size =
|
||||
rx_ring->sbq_len * sizeof(struct bq_element);
|
||||
rx_ring->sbq_len * sizeof(__le64);
|
||||
rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
|
||||
rx_ring->type = DEFAULT_Q;
|
||||
} else if (i < qdev->rss_ring_first_cq_id) {
|
||||
@@ -3372,11 +3360,11 @@ static int ql_configure_rings(struct ql_adapter *qdev)
|
||||
rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
|
||||
rx_ring->lbq_len = NUM_LARGE_BUFFERS;
|
||||
rx_ring->lbq_size =
|
||||
rx_ring->lbq_len * sizeof(struct bq_element);
|
||||
rx_ring->lbq_len * sizeof(__le64);
|
||||
rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
|
||||
rx_ring->sbq_len = NUM_SMALL_BUFFERS;
|
||||
rx_ring->sbq_size =
|
||||
rx_ring->sbq_len * sizeof(struct bq_element);
|
||||
rx_ring->sbq_len * sizeof(__le64);
|
||||
rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
|
||||
rx_ring->type = RX_Q;
|
||||
}
|
||||
|
||||
+48
-6
@@ -42,11 +42,11 @@
|
||||
#include <linux/mii.h>
|
||||
#include <linux/if_vlan.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/firmware.h>
|
||||
#include <asm/processor.h> /* Processor type for cache alignment. */
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include "starfire_firmware.h"
|
||||
/*
|
||||
* The current frame processor firmware fails to checksum a fragment
|
||||
* of length 1. If and when this is fixed, the #define below can be removed.
|
||||
@@ -173,6 +173,10 @@ static int full_duplex[MAX_UNITS] = {0, };
|
||||
#define skb_first_frag_len(skb) skb_headlen(skb)
|
||||
#define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
|
||||
|
||||
/* Firmware names */
|
||||
#define FIRMWARE_RX "adaptec/starfire_rx.bin"
|
||||
#define FIRMWARE_TX "adaptec/starfire_tx.bin"
|
||||
|
||||
/* These identify the driver base version and may not be removed. */
|
||||
static char version[] =
|
||||
KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
|
||||
@@ -182,6 +186,8 @@ MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
|
||||
MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
MODULE_FIRMWARE(FIRMWARE_RX);
|
||||
MODULE_FIRMWARE(FIRMWARE_TX);
|
||||
|
||||
module_param(max_interrupt_work, int, 0);
|
||||
module_param(mtu, int, 0);
|
||||
@@ -902,9 +908,12 @@ static void mdio_write(struct net_device *dev, int phy_id, int location, int val
|
||||
|
||||
static int netdev_open(struct net_device *dev)
|
||||
{
|
||||
const struct firmware *fw_rx, *fw_tx;
|
||||
const __be32 *fw_rx_data, *fw_tx_data;
|
||||
struct netdev_private *np = netdev_priv(dev);
|
||||
void __iomem *ioaddr = np->base;
|
||||
int i, retval;
|
||||
size_t tx_size, rx_size;
|
||||
size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
|
||||
|
||||
/* Do we ever need to reset the chip??? */
|
||||
@@ -1040,11 +1049,40 @@ static int netdev_open(struct net_device *dev)
|
||||
writel(ETH_P_8021Q, ioaddr + VlanType);
|
||||
#endif /* VLAN_SUPPORT */
|
||||
|
||||
retval = request_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev);
|
||||
if (retval) {
|
||||
printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
|
||||
FIRMWARE_RX);
|
||||
return retval;
|
||||
}
|
||||
if (fw_rx->size % 4) {
|
||||
printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
|
||||
fw_rx->size, FIRMWARE_RX);
|
||||
retval = -EINVAL;
|
||||
goto out_rx;
|
||||
}
|
||||
retval = request_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev);
|
||||
if (retval) {
|
||||
printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
|
||||
FIRMWARE_TX);
|
||||
goto out_rx;
|
||||
}
|
||||
if (fw_tx->size % 4) {
|
||||
printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
|
||||
fw_tx->size, FIRMWARE_TX);
|
||||
retval = -EINVAL;
|
||||
goto out_tx;
|
||||
}
|
||||
fw_rx_data = (const __be32 *)&fw_rx->data[0];
|
||||
fw_tx_data = (const __be32 *)&fw_tx->data[0];
|
||||
rx_size = fw_rx->size / 4;
|
||||
tx_size = fw_tx->size / 4;
|
||||
|
||||
/* Load Rx/Tx firmware into the frame processors */
|
||||
for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++)
|
||||
writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4);
|
||||
for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++)
|
||||
writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4);
|
||||
for (i = 0; i < rx_size; i++)
|
||||
writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4);
|
||||
for (i = 0; i < tx_size; i++)
|
||||
writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4);
|
||||
if (enable_hw_cksum)
|
||||
/* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
|
||||
writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
|
||||
@@ -1056,7 +1094,11 @@ static int netdev_open(struct net_device *dev)
|
||||
printk(KERN_DEBUG "%s: Done netdev_open().\n",
|
||||
dev->name);
|
||||
|
||||
return 0;
|
||||
out_tx:
|
||||
release_firmware(fw_tx);
|
||||
out_rx:
|
||||
release_firmware(fw_rx);
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1,346 +0,0 @@
|
||||
/*
|
||||
* Copyright 2003 Adaptec, Inc.
|
||||
*
|
||||
* Please read the following license before using the Adaptec Software
|
||||
* ("Program"). If you do not agree to the license terms, do not use the
|
||||
* Program:
|
||||
*
|
||||
* You agree to be bound by version 2 of the General Public License ("GPL")
|
||||
* dated June 1991, which can be found at http://www.fsf.org/licenses/gpl.html.
|
||||
* If the link is broken, write to Free Software Foundation, 59 Temple Place,
|
||||
* Boston, Massachusetts 02111-1307.
|
||||
*
|
||||
* BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE IT IS LICENSED "AS IS" AND
|
||||
* THERE IS NO WARRANTY FOR THE PROGRAM, INCLUDING BUT NOT LIMITED TO THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTIBILITY OR FITNESS FOR A PARTICULAR PURPOSE
|
||||
* (TO THE EXTENT PERMITTED BY APPLICABLE LAW). USE OF THE PROGRAM IS AT YOUR
|
||||
* OWN RISK. IN NO EVENT WILL ADAPTEC OR ITS LICENSORS BE LIABLE TO YOU FOR
|
||||
* DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
|
||||
* ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM.
|
||||
*
|
||||
*/
|
||||
|
||||
static const u32 firmware_rx[] = {
|
||||
0x010003dc, 0x00000000,
|
||||
0x04000421, 0x00000086,
|
||||
0x80000015, 0x0000180e,
|
||||
0x81000015, 0x00006664,
|
||||
0x1a0040ab, 0x00000b06,
|
||||
0x14200011, 0x00000000,
|
||||
0x14204022, 0x0000aaaa,
|
||||
0x14204022, 0x00000300,
|
||||
0x14204022, 0x00000000,
|
||||
0x1a0040ab, 0x00000b14,
|
||||
0x14200011, 0x00000000,
|
||||
0x83000015, 0x00000002,
|
||||
0x04000021, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x04000421, 0x00000087,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00008015, 0x00000000,
|
||||
0x0000003e, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x82000015, 0x00004000,
|
||||
0x009e8050, 0x00000000,
|
||||
0x03008015, 0x00000000,
|
||||
0x86008015, 0x00000000,
|
||||
0x82000015, 0x00008000,
|
||||
0x0100001c, 0x00000000,
|
||||
0x000050a0, 0x0000010c,
|
||||
0x4e20d011, 0x00006008,
|
||||
0x1420d012, 0x00004008,
|
||||
0x0000f090, 0x00007000,
|
||||
0x0000c8b0, 0x00003000,
|
||||
0x00004040, 0x00000000,
|
||||
0x00108015, 0x00000000,
|
||||
0x00a2c150, 0x00004000,
|
||||
0x00a400b0, 0x00000014,
|
||||
0x00000020, 0x00000000,
|
||||
0x2500400d, 0x00002525,
|
||||
0x00047220, 0x00003100,
|
||||
0x00934070, 0x00000000,
|
||||
0x00000020, 0x00000000,
|
||||
0x00924460, 0x00000184,
|
||||
0x2b20c011, 0x00000000,
|
||||
0x0000c420, 0x00000540,
|
||||
0x36014018, 0x0000422d,
|
||||
0x14200011, 0x00000000,
|
||||
0x00924460, 0x00000183,
|
||||
0x3200001f, 0x00000034,
|
||||
0x02ac0015, 0x00000002,
|
||||
0x00a60110, 0x00000008,
|
||||
0x42200011, 0x00000000,
|
||||
0x00924060, 0x00000103,
|
||||
0x0000001e, 0x00000000,
|
||||
0x00000020, 0x00000100,
|
||||
0x0000001e, 0x00000000,
|
||||
0x00924460, 0x00000086,
|
||||
0x00004080, 0x00000000,
|
||||
0x0092c070, 0x00000000,
|
||||
0x00924060, 0x00000100,
|
||||
0x0000c890, 0x00005000,
|
||||
0x00a6c110, 0x00000000,
|
||||
0x00b0c090, 0x00000012,
|
||||
0x021c0015, 0x00000000,
|
||||
0x3200001f, 0x00000034,
|
||||
0x00924460, 0x00000510,
|
||||
0x44210011, 0x00000000,
|
||||
0x42000011, 0x00000000,
|
||||
0x83000015, 0x00000040,
|
||||
0x00924460, 0x00000508,
|
||||
0x45014018, 0x00004545,
|
||||
0x00808050, 0x00000000,
|
||||
0x62208012, 0x00000000,
|
||||
0x82000015, 0x00000800,
|
||||
0x15200011, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x80000015, 0x0000eea4,
|
||||
0x81000015, 0x0000005f,
|
||||
0x00000060, 0x00000000,
|
||||
0x00004120, 0x00000000,
|
||||
0x00004a00, 0x00004000,
|
||||
0x00924460, 0x00000190,
|
||||
0x5601401a, 0x00005956,
|
||||
0x14000011, 0x00000000,
|
||||
0x00934050, 0x00000018,
|
||||
0x00930050, 0x00000018,
|
||||
0x3601403a, 0x0000002d,
|
||||
0x000643a9, 0x00000000,
|
||||
0x0000c420, 0x00000140,
|
||||
0x5601401a, 0x00005956,
|
||||
0x14000011, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x000642a9, 0x00000000,
|
||||
0x00024420, 0x00000183,
|
||||
0x5601401a, 0x00005956,
|
||||
0x82000015, 0x00002000,
|
||||
0x15200011, 0x00000000,
|
||||
0x82000015, 0x00000010,
|
||||
0x15200011, 0x00000000,
|
||||
0x82000015, 0x00000010,
|
||||
0x15200011, 0x00000000,
|
||||
}; /* 104 Rx instructions */
|
||||
#define FIRMWARE_RX_SIZE 104
|
||||
|
||||
static const u32 firmware_tx[] = {
|
||||
0x010003dc, 0x00000000,
|
||||
0x04000421, 0x00000086,
|
||||
0x80000015, 0x0000180e,
|
||||
0x81000015, 0x00006664,
|
||||
0x1a0040ab, 0x00000b06,
|
||||
0x14200011, 0x00000000,
|
||||
0x14204022, 0x0000aaaa,
|
||||
0x14204022, 0x00000300,
|
||||
0x14204022, 0x00000000,
|
||||
0x1a0040ab, 0x00000b14,
|
||||
0x14200011, 0x00000000,
|
||||
0x83000015, 0x00000002,
|
||||
0x04000021, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x04000421, 0x00000087,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00008015, 0x00000000,
|
||||
0x0000003e, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x82000015, 0x00004000,
|
||||
0x009e8050, 0x00000000,
|
||||
0x03008015, 0x00000000,
|
||||
0x86008015, 0x00000000,
|
||||
0x82000015, 0x00008000,
|
||||
0x0100001c, 0x00000000,
|
||||
0x000050a0, 0x0000010c,
|
||||
0x4e20d011, 0x00006008,
|
||||
0x1420d012, 0x00004008,
|
||||
0x0000f090, 0x00007000,
|
||||
0x0000c8b0, 0x00003000,
|
||||
0x00004040, 0x00000000,
|
||||
0x00108015, 0x00000000,
|
||||
0x00a2c150, 0x00004000,
|
||||
0x00a400b0, 0x00000014,
|
||||
0x00000020, 0x00000000,
|
||||
0x2500400d, 0x00002525,
|
||||
0x00047220, 0x00003100,
|
||||
0x00934070, 0x00000000,
|
||||
0x00000020, 0x00000000,
|
||||
0x00924460, 0x00000184,
|
||||
0x2b20c011, 0x00000000,
|
||||
0x0000c420, 0x00000540,
|
||||
0x36014018, 0x0000422d,
|
||||
0x14200011, 0x00000000,
|
||||
0x00924460, 0x00000183,
|
||||
0x3200001f, 0x00000034,
|
||||
0x02ac0015, 0x00000002,
|
||||
0x00a60110, 0x00000008,
|
||||
0x42200011, 0x00000000,
|
||||
0x00924060, 0x00000103,
|
||||
0x0000001e, 0x00000000,
|
||||
0x00000020, 0x00000100,
|
||||
0x0000001e, 0x00000000,
|
||||
0x00924460, 0x00000086,
|
||||
0x00004080, 0x00000000,
|
||||
0x0092c070, 0x00000000,
|
||||
0x00924060, 0x00000100,
|
||||
0x0000c890, 0x00005000,
|
||||
0x00a6c110, 0x00000000,
|
||||
0x00b0c090, 0x00000012,
|
||||
0x021c0015, 0x00000000,
|
||||
0x3200001f, 0x00000034,
|
||||
0x00924460, 0x00000510,
|
||||
0x44210011, 0x00000000,
|
||||
0x42000011, 0x00000000,
|
||||
0x83000015, 0x00000040,
|
||||
0x00924460, 0x00000508,
|
||||
0x45014018, 0x00004545,
|
||||
0x00808050, 0x00000000,
|
||||
0x62208012, 0x00000000,
|
||||
0x82000015, 0x00000800,
|
||||
0x15200011, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x80000015, 0x0000eea4,
|
||||
0x81000015, 0x0000005f,
|
||||
0x00000060, 0x00000000,
|
||||
0x00004120, 0x00000000,
|
||||
0x00004a00, 0x00004000,
|
||||
0x00924460, 0x00000190,
|
||||
0x5601401a, 0x00005956,
|
||||
0x14000011, 0x00000000,
|
||||
0x00934050, 0x00000018,
|
||||
0x00930050, 0x00000018,
|
||||
0x3601403a, 0x0000002d,
|
||||
0x000643a9, 0x00000000,
|
||||
0x0000c420, 0x00000140,
|
||||
0x5601401a, 0x00005956,
|
||||
0x14000011, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x000642a9, 0x00000000,
|
||||
0x00024420, 0x00000183,
|
||||
0x5601401a, 0x00005956,
|
||||
0x82000015, 0x00002000,
|
||||
0x15200011, 0x00000000,
|
||||
0x82000015, 0x00000010,
|
||||
0x15200011, 0x00000000,
|
||||
0x82000015, 0x00000010,
|
||||
0x15200011, 0x00000000,
|
||||
}; /* 104 Tx instructions */
|
||||
#define FIRMWARE_TX_SIZE 104
|
||||
#if 0
|
||||
static const u32 firmware_wol[] = {
|
||||
0x010003dc, 0x00000000,
|
||||
0x19000421, 0x00000087,
|
||||
0x80000015, 0x00001a1a,
|
||||
0x81000015, 0x00001a1a,
|
||||
0x1a0040ab, 0x00000b06,
|
||||
0x15200011, 0x00000000,
|
||||
0x15204022, 0x0000aaaa,
|
||||
0x15204022, 0x00000300,
|
||||
0x15204022, 0x00000000,
|
||||
0x1a0040ab, 0x00000b15,
|
||||
0x15200011, 0x00000000,
|
||||
0x83000015, 0x00000002,
|
||||
0x04000021, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x04000421, 0x00000087,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00008015, 0x00000000,
|
||||
0x0000003e, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x82000015, 0x00004000,
|
||||
0x82000015, 0x00008000,
|
||||
0x0000000c, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00004080, 0x00000100,
|
||||
0x1f20c011, 0x00001122,
|
||||
0x2720f011, 0x00003011,
|
||||
0x19200071, 0x00000000,
|
||||
0x1a200051, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x1d2040a4, 0x00003344,
|
||||
0x1d2040a2, 0x00005566,
|
||||
0x000040a0, 0x00000100,
|
||||
0x00108050, 0x00000001,
|
||||
0x1a208012, 0x00000006,
|
||||
0x82000015, 0x00008080,
|
||||
0x010003dc, 0x00000000,
|
||||
0x1d2040a4, 0x00002233,
|
||||
0x1d2040a4, 0x00004455,
|
||||
0x2d208011, 0x00000005,
|
||||
0x1d2040a4, 0x00006611,
|
||||
0x00108050, 0x00000001,
|
||||
0x27200011, 0x00000000,
|
||||
0x1d2050a4, 0x00006600,
|
||||
0x82000015, 0x00008080,
|
||||
0x010003dc, 0x00000000,
|
||||
0x00000050, 0x00000000,
|
||||
0x1b200031, 0x00000000,
|
||||
0x0000001e, 0x00000000,
|
||||
0x0000001e, 0x00000000,
|
||||
0x0000001e, 0x00000000,
|
||||
0x0000001e, 0x00000000,
|
||||
0x00924460, 0x00000086,
|
||||
0x00004080, 0x00000000,
|
||||
0x0092c070, 0x00000000,
|
||||
0x00924060, 0x00000100,
|
||||
0x0000c890, 0x00005000,
|
||||
0x00a6c110, 0x00000000,
|
||||
0x00b0c090, 0x00000012,
|
||||
0x021c0015, 0x00000000,
|
||||
0x3200001f, 0x00000034,
|
||||
0x00924460, 0x00000510,
|
||||
0x44210011, 0x00000000,
|
||||
0x42000011, 0x00000000,
|
||||
0x83000015, 0x00000040,
|
||||
0x00924460, 0x00000508,
|
||||
0x476a0012, 0x00000100,
|
||||
0x83000015, 0x00000008,
|
||||
0x16200011, 0x00000000,
|
||||
0x001e8050, 0x00000000,
|
||||
0x001e8050, 0x00000000,
|
||||
0x00808050, 0x00000000,
|
||||
0x03008015, 0x00000000,
|
||||
0x62208012, 0x00000000,
|
||||
0x82000015, 0x00000800,
|
||||
0x16200011, 0x00000000,
|
||||
0x80000015, 0x0000eea4,
|
||||
0x81000015, 0x0000005f,
|
||||
0x00000020, 0x00000000,
|
||||
0x00004120, 0x00000000,
|
||||
0x00004a00, 0x00004000,
|
||||
0x00924460, 0x00000190,
|
||||
0x5c01401a, 0x0000595c,
|
||||
0x15000011, 0x00000000,
|
||||
0x00934050, 0x00000018,
|
||||
0x00930050, 0x00000018,
|
||||
0x3601403a, 0x0000002d,
|
||||
0x00064029, 0x00000000,
|
||||
0x0000c420, 0x00000140,
|
||||
0x5c01401a, 0x0000595c,
|
||||
0x15000011, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00064029, 0x00000000,
|
||||
0x00024420, 0x00000183,
|
||||
0x5c01401a, 0x0000595c,
|
||||
0x82000015, 0x00002000,
|
||||
0x16200011, 0x00000000,
|
||||
0x82000015, 0x00000010,
|
||||
0x16200011, 0x00000000,
|
||||
0x82000015, 0x00000010,
|
||||
0x16200011, 0x00000000,
|
||||
}; /* 104 WoL instructions */
|
||||
#define FIRMWARE_WOL_SIZE 104
|
||||
#endif
|
||||
@@ -1,31 +0,0 @@
|
||||
#!/usr/bin/perl
|
||||
|
||||
# This script can be used to generate a new starfire_firmware.h
|
||||
# from GFP_RX.DAT and GFP_TX.DAT, files included with the DDK
|
||||
# and also with the Novell drivers.
|
||||
|
||||
open FW, "GFP_RX.DAT" || die;
|
||||
open FWH, ">starfire_firmware.h" || die;
|
||||
|
||||
printf(FWH "static u32 firmware_rx[] = {\n");
|
||||
$counter = 0;
|
||||
while ($foo = <FW>) {
|
||||
chomp;
|
||||
printf(FWH " 0x%s, 0x0000%s,\n", substr($foo, 4, 8), substr($foo, 0, 4));
|
||||
$counter++;
|
||||
}
|
||||
|
||||
close FW;
|
||||
open FW, "GFP_TX.DAT" || die;
|
||||
|
||||
printf(FWH "};\t/* %d Rx instructions */\n#define FIRMWARE_RX_SIZE %d\n\nstatic u32 firmware_tx[] = {\n", $counter, $counter);
|
||||
$counter = 0;
|
||||
while ($foo = <FW>) {
|
||||
chomp;
|
||||
printf(FWH " 0x%s, 0x0000%s,\n", substr($foo, 4, 8), substr($foo, 0, 4));
|
||||
$counter++;
|
||||
}
|
||||
|
||||
close FW;
|
||||
printf(FWH "};\t/* %d Tx instructions */\n#define FIRMWARE_TX_SIZE %d\n", $counter, $counter);
|
||||
close(FWH);
|
||||
+94
-698
File diff suppressed because it is too large
Load Diff
@@ -2762,6 +2762,10 @@ struct tg3 {
|
||||
#define SST_25VF0X0_PAGE_SIZE 4098
|
||||
|
||||
struct ethtool_coalesce coal;
|
||||
|
||||
/* firmware info */
|
||||
const struct firmware *fw;
|
||||
u32 fw_len; /* includes BSS */
|
||||
};
|
||||
|
||||
#endif /* !(_T3_H) */
|
||||
|
||||
+1
-1
@@ -213,7 +213,7 @@ static int check_filter(struct tap_filter *filter, const struct sk_buff *skb)
|
||||
|
||||
/* Network device part of the driver */
|
||||
|
||||
static unsigned int tun_net_id;
|
||||
static int tun_net_id;
|
||||
struct tun_net {
|
||||
struct list_head dev_list;
|
||||
};
|
||||
|
||||
@@ -643,7 +643,6 @@ struct qeth_card_options {
|
||||
int macaddr_mode;
|
||||
int fake_broadcast;
|
||||
int add_hhlen;
|
||||
int fake_ll;
|
||||
int layer2;
|
||||
enum qeth_large_send_types large_send;
|
||||
int performance_stats;
|
||||
|
||||
@@ -287,8 +287,15 @@ int qeth_set_large_send(struct qeth_card *card,
|
||||
card->options.large_send = type;
|
||||
switch (card->options.large_send) {
|
||||
case QETH_LARGE_SEND_EDDP:
|
||||
card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
|
||||
if (card->info.type != QETH_CARD_TYPE_IQD) {
|
||||
card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
|
||||
NETIF_F_HW_CSUM;
|
||||
} else {
|
||||
card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
|
||||
NETIF_F_HW_CSUM);
|
||||
card->options.large_send = QETH_LARGE_SEND_NO;
|
||||
rc = -EOPNOTSUPP;
|
||||
}
|
||||
break;
|
||||
case QETH_LARGE_SEND_TSO:
|
||||
if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
|
||||
@@ -572,6 +579,10 @@ static void qeth_send_control_data_cb(struct qeth_channel *channel,
|
||||
card = CARD_FROM_CDEV(channel->ccwdev);
|
||||
if (qeth_check_idx_response(iob->data)) {
|
||||
qeth_clear_ipacmd_list(card);
|
||||
if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
|
||||
dev_err(&card->gdev->dev,
|
||||
"The qeth device is not configured "
|
||||
"for the OSI layer required by z/VM\n");
|
||||
qeth_schedule_recovery(card);
|
||||
goto out;
|
||||
}
|
||||
@@ -1072,7 +1083,6 @@ static void qeth_set_intial_options(struct qeth_card *card)
|
||||
card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
|
||||
card->options.fake_broadcast = 0;
|
||||
card->options.add_hhlen = DEFAULT_ADD_HHLEN;
|
||||
card->options.fake_ll = 0;
|
||||
card->options.performance_stats = 0;
|
||||
card->options.rx_sg_cb = QETH_RX_SG_CB;
|
||||
}
|
||||
@@ -1682,6 +1692,7 @@ int qeth_send_control_data(struct qeth_card *card, int len,
|
||||
unsigned long flags;
|
||||
struct qeth_reply *reply = NULL;
|
||||
unsigned long timeout;
|
||||
struct qeth_ipa_cmd *cmd;
|
||||
|
||||
QETH_DBF_TEXT(TRACE, 2, "sendctl");
|
||||
|
||||
@@ -1728,17 +1739,34 @@ int qeth_send_control_data(struct qeth_card *card, int len,
|
||||
wake_up(&card->wait_q);
|
||||
return rc;
|
||||
}
|
||||
while (!atomic_read(&reply->received)) {
|
||||
if (time_after(jiffies, timeout)) {
|
||||
spin_lock_irqsave(&reply->card->lock, flags);
|
||||
list_del_init(&reply->list);
|
||||
spin_unlock_irqrestore(&reply->card->lock, flags);
|
||||
reply->rc = -ETIME;
|
||||
atomic_inc(&reply->received);
|
||||
wake_up(&reply->wait_q);
|
||||
}
|
||||
cpu_relax();
|
||||
};
|
||||
|
||||
/* we have only one long running ipassist, since we can ensure
|
||||
process context of this command we can sleep */
|
||||
cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
|
||||
if ((cmd->hdr.command == IPA_CMD_SETIP) &&
|
||||
(cmd->hdr.prot_version == QETH_PROT_IPV4)) {
|
||||
if (!wait_event_timeout(reply->wait_q,
|
||||
atomic_read(&reply->received), timeout))
|
||||
goto time_err;
|
||||
} else {
|
||||
while (!atomic_read(&reply->received)) {
|
||||
if (time_after(jiffies, timeout))
|
||||
goto time_err;
|
||||
cpu_relax();
|
||||
};
|
||||
}
|
||||
|
||||
rc = reply->rc;
|
||||
qeth_put_reply(reply);
|
||||
return rc;
|
||||
|
||||
time_err:
|
||||
spin_lock_irqsave(&reply->card->lock, flags);
|
||||
list_del_init(&reply->list);
|
||||
spin_unlock_irqrestore(&reply->card->lock, flags);
|
||||
reply->rc = -ETIME;
|
||||
atomic_inc(&reply->received);
|
||||
wake_up(&reply->wait_q);
|
||||
rc = reply->rc;
|
||||
qeth_put_reply(reply);
|
||||
return rc;
|
||||
@@ -2250,7 +2278,8 @@ void qeth_print_status_message(struct qeth_card *card)
|
||||
}
|
||||
/* fallthrough */
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
if (card->info.guestlan) {
|
||||
if ((card->info.guestlan) ||
|
||||
(card->info.mcl_level[0] & 0x80)) {
|
||||
card->info.mcl_level[0] = (char) _ebcasc[(__u8)
|
||||
card->info.mcl_level[0]];
|
||||
card->info.mcl_level[1] = (char) _ebcasc[(__u8)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user