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drm/nouveau/fifo: convert to new-style nvkm_engine

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
2015-08-20 14:54:22 +10:00
parent 70aa8670e5
commit 13de7f4629
56 changed files with 650 additions and 811 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
+17 -66
View File
@@ -1,7 +1,5 @@
#ifndef __NVKM_FIFO_H__
#define __NVKM_FIFO_H__
#define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object)
#define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine)
#include <core/engine.h>
#include <core/event.h>
@@ -33,46 +31,21 @@ struct nvkm_fifo_chan {
extern const struct nvkm_object_func nvkm_fifo_chan_func;
#include <core/gpuobj.h>
struct nvkm_fifo_base {
struct nvkm_gpuobj gpuobj;
};
#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d) \
nvkm_gpuobj_create((p), (e), (c), NV_ENGCTX_CLASS, (g), (s), (a), (f), (d))
#define nvkm_fifo_context_destroy(p) \
nvkm_gpuobj_destroy(&(p)->gpuobj)
#define nvkm_fifo_context_init(p) \
nvkm_gpuobj_init(&(p)->gpuobj)
#define nvkm_fifo_context_fini(p,s) \
nvkm_gpuobj_fini(&(p)->gpuobj, (s))
#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor
#define _nvkm_fifo_context_init _nvkm_gpuobj_init
#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini
#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32
#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32
struct nvkm_fifo {
struct nvkm_engine engine;
const struct nvkm_fifo_func *func;
struct nvkm_event cevent; /* channel creation event */
struct nvkm_event uevent; /* async user trigger */
struct nvkm_engine engine;
DECLARE_BITMAP(mask, NVKM_FIFO_CHID_NR);
int nr;
struct list_head chan;
spinlock_t lock;
void (*pause)(struct nvkm_fifo *, unsigned long *);
void (*start)(struct nvkm_fifo *, unsigned long *);
struct nvkm_event uevent; /* async user trigger */
struct nvkm_event cevent; /* channel creation event */
};
struct nvkm_fifo_func {
void *(*dtor)(struct nvkm_fifo *);
const struct nvkm_fifo_chan_oclass *chan[];
};
void nvkm_fifo_pause(struct nvkm_fifo *, unsigned long *);
void nvkm_fifo_start(struct nvkm_fifo *, unsigned long *);
void nvkm_fifo_chan_put(struct nvkm_fifo *, unsigned long flags,
struct nvkm_fifo_chan **);
@@ -81,38 +54,16 @@ nvkm_fifo_chan_inst(struct nvkm_fifo *, u64 inst, unsigned long *flags);
struct nvkm_fifo_chan *
nvkm_fifo_chan_chid(struct nvkm_fifo *, int chid, unsigned long *flags);
#define nvkm_fifo_create(o,e,c,fc,lc,d) \
nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)
#define nvkm_fifo_init(p) \
nvkm_engine_init_old(&(p)->engine)
#define nvkm_fifo_fini(p,s) \
nvkm_engine_fini_old(&(p)->engine, (s))
int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int min, int max,
int size, void **);
void nvkm_fifo_destroy(struct nvkm_fifo *);
#define _nvkm_fifo_init _nvkm_engine_init
#define _nvkm_fifo_fini _nvkm_engine_fini
extern struct nvkm_oclass *nv04_fifo_oclass;
extern struct nvkm_oclass *nv10_fifo_oclass;
extern struct nvkm_oclass *nv17_fifo_oclass;
extern struct nvkm_oclass *nv40_fifo_oclass;
extern struct nvkm_oclass *nv50_fifo_oclass;
extern struct nvkm_oclass *g84_fifo_oclass;
extern struct nvkm_oclass *gf100_fifo_oclass;
extern struct nvkm_oclass *gk104_fifo_oclass;
extern struct nvkm_oclass *gk20a_fifo_oclass;
extern struct nvkm_oclass *gk208_fifo_oclass;
extern struct nvkm_oclass *gm204_fifo_oclass;
extern struct nvkm_oclass *gm20b_fifo_oclass;
int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32,
struct nvkm_notify *);
void nvkm_fifo_uevent(struct nvkm_fifo *);
void nv04_fifo_intr(struct nvkm_subdev *);
int nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *);
int nv04_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int nv10_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int nv17_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int nv40_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int nv50_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int g84_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gf100_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gk104_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gk208_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gk20a_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gm204_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
int gm20b_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
#endif
drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
+1 -1
View File
@@ -231,7 +231,7 @@ nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj)
nvkm_object_destroy(&gpuobj->object);
}
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
int
nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
+1
View File
@@ -26,6 +26,7 @@
#include <core/client.h>
#include <core/enum.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <nvif/class.h>
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+68 -68
View File
File diff suppressed because it is too large Load Diff
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
-9
View File
@@ -28,55 +28,46 @@ gf100_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xc0:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc4:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc3:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xce:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xcf:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc1:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
break;
case 0xc8:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd9:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
case 0xd7:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
-8
View File
@@ -28,48 +28,40 @@ gk104_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xe4:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe7:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe6:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xea:
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xf0:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0xf1:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0x106:
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
break;
case 0x108:
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
break;
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
-4
View File
@@ -31,7 +31,6 @@ gm100_identify(struct nvkm_device *device)
#if 0
#endif
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
#if 0
@@ -46,7 +45,6 @@ gm100_identify(struct nvkm_device *device)
#endif
#if 0
#endif
device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
#if 0
@@ -59,7 +57,6 @@ gm100_identify(struct nvkm_device *device)
#endif
#if 0
#endif
device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
#if 0
@@ -67,7 +64,6 @@ gm100_identify(struct nvkm_device *device)
break;
case 0x12b:
device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass;
break;
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
-2
View File
@@ -28,12 +28,10 @@ nv04_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x04:
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
break;
case 0x05:
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
break;
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
-7
View File
@@ -31,37 +31,30 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
break;
case 0x15:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
break;
case 0x16:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
break;
case 0x1a:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
break;
case 0x11:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
break;
case 0x17:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
break;
case 0x1f:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
break;
case 0x18:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
break;
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
-4
View File
@@ -28,22 +28,18 @@ nv20_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x20:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
break;
case 0x25:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
break;
case 0x28:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
break;
case 0x2a:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
break;
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
-5
View File
@@ -28,29 +28,24 @@ nv30_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x30:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
break;
case 0x35:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
break;
case 0x31:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
break;
case 0x36:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
break;
case 0x34:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
-16
View File
@@ -28,112 +28,96 @@ nv40_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x40:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x41:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x42:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x43:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x45:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x47:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x49:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4b:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x44:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x46:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4a:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4c:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4e:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x63:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x67:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x68:
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
-14
View File
@@ -28,93 +28,79 @@ nv50_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x50:
device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
break;
case 0x84:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x86:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x92:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x94:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x96:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x98:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa0:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break;
case 0xaa:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xac:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa3:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa5:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa8:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xaf:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
+2 -1
View File
@@ -20,9 +20,10 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <engine/falcon.h>
#include <engine/fifo.h>
#include <core/gpuobj.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
static int
nvkm_falcon_oclass_get(struct nvkm_oclass *oclass, int index)
drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
+1 -1
View File
@@ -7,8 +7,8 @@ nvkm-y += nvkm/engine/fifo/nv50.o
nvkm-y += nvkm/engine/fifo/g84.o
nvkm-y += nvkm/engine/fifo/gf100.o
nvkm-y += nvkm/engine/fifo/gk104.o
nvkm-y += nvkm/engine/fifo/gk20a.o
nvkm-y += nvkm/engine/fifo/gk208.o
nvkm-y += nvkm/engine/fifo/gk20a.o
nvkm-y += nvkm/engine/fifo/gm204.o
nvkm-y += nvkm/engine/fifo/gm20b.o
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
+100 -28
View File
@@ -25,11 +25,24 @@
#include "chan.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <core/notify.h>
#include <nvif/event.h>
#include <nvif/unpack.h>
void
nvkm_fifo_pause(struct nvkm_fifo *fifo, unsigned long *flags)
{
return fifo->func->pause(fifo, flags);
}
void
nvkm_fifo_start(struct nvkm_fifo *fifo, unsigned long *flags)
{
return fifo->func->start(fifo, flags);
}
void
nvkm_fifo_chan_put(struct nvkm_fifo *fifo, unsigned long flags,
struct nvkm_fifo_chan **pchan)
@@ -95,7 +108,21 @@ nvkm_fifo_event_func = {
.ctor = nvkm_fifo_event_ctor,
};
int
static void
nvkm_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
{
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
fifo->func->uevent_fini(fifo);
}
static void
nvkm_fifo_uevent_init(struct nvkm_event *event, int type, int index)
{
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
fifo->func->uevent_init(fifo);
}
static int
nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
struct nvkm_notify *notify)
{
@@ -113,6 +140,13 @@ nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
return ret;
}
static const struct nvkm_event_func
nvkm_fifo_uevent_func = {
.ctor = nvkm_fifo_uevent_ctor,
.init = nvkm_fifo_uevent_init,
.fini = nvkm_fifo_uevent_fini,
};
void
nvkm_fifo_uevent(struct nvkm_fifo *fifo)
{
@@ -156,50 +190,88 @@ nvkm_fifo_class_get(struct nvkm_oclass *oclass, int index,
return c;
}
void
nvkm_fifo_destroy(struct nvkm_fifo *fifo)
static void
nvkm_fifo_intr(struct nvkm_engine *engine)
{
nvkm_event_fini(&fifo->uevent);
struct nvkm_fifo *fifo = nvkm_fifo(engine);
fifo->func->intr(fifo);
}
static int
nvkm_fifo_fini(struct nvkm_engine *engine, bool suspend)
{
struct nvkm_fifo *fifo = nvkm_fifo(engine);
if (fifo->func->fini)
fifo->func->fini(fifo);
return 0;
}
static int
nvkm_fifo_oneinit(struct nvkm_engine *engine)
{
struct nvkm_fifo *fifo = nvkm_fifo(engine);
if (fifo->func->oneinit)
return fifo->func->oneinit(fifo);
return 0;
}
static int
nvkm_fifo_init(struct nvkm_engine *engine)
{
struct nvkm_fifo *fifo = nvkm_fifo(engine);
fifo->func->init(fifo);
return 0;
}
static void *
nvkm_fifo_dtor(struct nvkm_engine *engine)
{
struct nvkm_fifo *fifo = nvkm_fifo(engine);
void *data = fifo;
if (fifo->func->dtor)
data = fifo->func->dtor(fifo);
nvkm_event_fini(&fifo->cevent);
nvkm_engine_destroy(&fifo->engine);
nvkm_event_fini(&fifo->uevent);
return data;
}
static const struct nvkm_engine_func
nvkm_fifo_func = {
nvkm_fifo = {
.dtor = nvkm_fifo_dtor,
.oneinit = nvkm_fifo_oneinit,
.init = nvkm_fifo_init,
.fini = nvkm_fifo_fini,
.intr = nvkm_fifo_intr,
.base.sclass = nvkm_fifo_class_get,
};
int
nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass,
int min, int max, int length, void **pobject)
nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device,
int index, int nr, struct nvkm_fifo *fifo)
{
struct nvkm_fifo *fifo;
int nr = max + 1;
int cnt = nr - min;
int ret;
ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO",
"fifo", length, pobject);
fifo = *pobject;
if (ret)
return ret;
fifo->engine.func = &nvkm_fifo_func;
fifo->func = func;
INIT_LIST_HEAD(&fifo->chan);
spin_lock_init(&fifo->lock);
fifo->nr = nr;
if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR)) {
if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR))
fifo->nr = NVKM_FIFO_CHID_NR;
cnt = fifo->nr - min;
}
bitmap_fill(fifo->mask, NVKM_FIFO_CHID_NR);
bitmap_clear(fifo->mask, min, cnt);
else
fifo->nr = nr;
bitmap_clear(fifo->mask, 0, fifo->nr);
ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent);
ret = nvkm_engine_ctor(&nvkm_fifo, device, index, 0x00000100,
true, &fifo->engine);
if (ret)
return ret;
spin_lock_init(&fifo->lock);
return 0;
if (func->uevent_init) {
ret = nvkm_event_init(&nvkm_fifo_uevent_func, 1, 1,
&fifo->uevent);
if (ret)
return ret;
}
return nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent);
}
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
+1
View File
@@ -24,6 +24,7 @@
#include "chan.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <core/oproxy.h>
#include <subdev/mmu.h>
#include <engine/dma.h>
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h
+1
View File
@@ -1,5 +1,6 @@
#ifndef __NVKM_FIFO_CHAN_H__
#define __NVKM_FIFO_CHAN_H__
#define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object)
#include "priv.h"
struct nvkm_fifo_chan_func {
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
+4 -4
View File
@@ -73,7 +73,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
struct nv04_fifo *fifo = chan->fifo;
struct nvkm_device *device = fifo->base.engine.subdev.device;
struct nvkm_memory *fctx = device->imem->ramfc;
struct ramfc_desc *c;
const struct nv04_fifo_ramfc *c;
unsigned long flags;
u32 mask = fifo->base.nr - 1;
u32 data = chan->ramfc;
@@ -90,7 +90,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0);
nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
c = fifo->ramfc_desc;
c = fifo->ramfc;
do {
u32 rm = ((1ULL << c->bits) - 1) << c->regs;
u32 cm = ((1ULL << c->bits) - 1) << c->ctxs;
@@ -99,7 +99,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs));
} while ((++c)->bits);
c = fifo->ramfc_desc;
c = fifo->ramfc;
do {
nvkm_wr32(device, c->regp, 0x00000000);
} while ((++c)->bits);
@@ -136,7 +136,7 @@ nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base)
struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
struct nv04_fifo *fifo = chan->fifo;
struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
struct ramfc_desc *c = fifo->ramfc_desc;
const struct nv04_fifo_ramfc *c = fifo->ramfc;
nvkm_kmap(imem->ramfc);
do {
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c
+1
View File
@@ -25,6 +25,7 @@
#include "regsnv04.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/instmem.h>
#include <nvif/class.h>

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