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Merge tag 'spi-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"A quiet release, more bug fixes than anything else. A few things do
stand out though:
- updates to several drivers to move towards the standard GPIO chip
select handling in the core.
- DMA support for the SH MSIOF driver.
- support for Rockchip SPI controllers (their first mainline
submission)"
* tag 'spi-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (64 commits)
spi: davinci: use spi_device.cs_gpio to store gpio cs per spi device
spi: davinci: add support to configure gpio cs through dt
spi/pl022: Explicitly truncate large bitmask
spi/atmel: Fix pointer to int conversion warnings on 64 bit builds
spi: davinci: fix to support more than 2 chip selects
spi: topcliff-pch: don't hardcode PCI slot to get DMA device
spi: orion: fix incorrect handling of cell-index DT property
spi: orion: Fix error return code in orion_spi_probe()
spi/rockchip: fix error return code in rockchip_spi_probe()
spi/rockchip: remove redundant dev_err call in rockchip_spi_probe()
spi/rockchip: remove duplicated include from spi-rockchip.c
ARM: dts: fix the chip select gpios definition in the SPI nodes
spi: s3c64xx: Update binding documentation
spi: s3c64xx: use the generic SPI "cs-gpios" property
spi: s3c64xx: Revert "spi: s3c64xx: Added provision for dedicated cs pin"
spi: atmel: Use dmaengine_prep_slave_sg() API
spi: topcliff-pch: Update error messages for dmaengine_prep_slave_sg() API
spi: sh-msiof: Use correct device for DMA mapping with IOMMU
spi: sh-msiof: Handle dmaengine_prep_slave_single() failures gracefully
spi: rspi: Handle dmaengine_prep_slave_sg() failures gracefully
...
This commit is contained in:
Linus Torvalds
@@ -10,11 +10,12 @@ Required properties:
|
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- cs-gpios: see spi-bus.txt
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Recommended properties :
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- efm32,location: Value to write to the ROUTE register's LOCATION bitfield to
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configure the pinmux for the device, see datasheet for values.
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If "efm32,location" property is not provided, keeping what is
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already configured in the hardware, so its either the reset
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default 0 or whatever the bootloader did.
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- energymicro,location: Value to write to the ROUTE register's LOCATION
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bitfield to configure the pinmux for the device, see
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datasheet for values.
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If this property is not provided, keeping what is
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already configured in the hardware, so its either the
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reset default 0 or whatever the bootloader did.
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Example:
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@@ -26,7 +27,7 @@ spi1: spi@0x4000c400 { /* USART1 */
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interrupts = <15 16>;
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clocks = <&cmu 20>;
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cs-gpios = <&gpio 51 1>; // D3
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efm32,location = <1>;
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energymicro,location = <1>;
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status = "ok";
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ks8851@0 {
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@@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz, up to four chip selects, programmable
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data path from 4 bits to 32 bits and numerous protocol variants.
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Required properties:
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- compatible: Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
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- compatible: Should contain:
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"qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
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"qcom,spi-qup-v2.1.1" for 8974 and later
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"qcom,spi-qup-v2.2.1" for 8974 v2 and later.
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- reg: Should contain base register location and length
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- interrupts: Interrupt number used by this controller
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@@ -0,0 +1,28 @@
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Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
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Required properties:
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- compatible : "snps,dw-apb-ssi"
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- reg : The register base for the controller.
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- interrupts : One interrupt, used by the controller.
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- #address-cells : <1>, as required by generic SPI binding.
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- #size-cells : <0>, also as required by generic SPI binding.
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Optional properties:
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- cs-gpios : Specifies the gpio pis to be used for chipselects.
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- num-cs : The number of chipselects. If omitted, this will default to 4.
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Child nodes as per the generic SPI binding.
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Example:
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spi@fff00000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 154 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <2>;
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cs-gpios = <&gpio0 13 0>,
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<&gpio0 14 0>;
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};
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@@ -8,7 +8,8 @@ Required properties:
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- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
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- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
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- reg: Offset and length of SPI controller register space
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- num-cs: Number of chip selects
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- num-cs: Number of chip selects. This includes internal as well as
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GPIO chip selects.
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- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
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IP to the interrupt controller within the SoC. Possible values
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are 0 and 1. Manual says one of the two possible interrupt
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@@ -17,6 +18,12 @@ Required properties:
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- interrupts: interrupt number mapped to CPU.
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- clocks: spi clk phandle
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Optional:
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- cs-gpios: gpio chip selects
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For example to have 3 internal CS and 2 GPIO CS, user could define
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cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
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where first three are internal CS and last two are GPIO CS.
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Example of a NOR flash slave device (n25q032) connected to DaVinci
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SPI controller device over the SPI bus.
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@@ -0,0 +1,37 @@
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* Rockchip SPI Controller
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The Rockchip SPI controller is used to interface with various devices such as flash
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and display controllers using the SPI communication interface.
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Required Properties:
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- compatible: should be one of the following.
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"rockchip,rk3066-spi" for rk3066.
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"rockchip,rk3188-spi", "rockchip,rk3066-spi" for rk3188.
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"rockchip,rk3288-spi", "rockchip,rk3066-spi" for rk3288.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: The interrupt number to the cpu. The interrupt specifier format
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depends on the interrupt controller.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Shall be "spiclk" for the transfer-clock, and "apb_pclk" for
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the peripheral clock.
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- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
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Documentation/devicetree/bindings/dma/dma.txt
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- dma-names: DMA request names should include "tx" and "rx" if present.
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- #address-cells: should be 1.
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- #size-cells: should be 0.
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Example:
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spi0: spi@ff110000 {
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compatible = "rockchip,rk3066-spi";
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reg = <0xff110000 0x1000>;
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dmas = <&pdma1 11>, <&pdma1 12>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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};
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@@ -18,14 +18,11 @@ Required SoC Specific Properties:
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- interrupts: The interrupt number to the cpu. The interrupt specifier format
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depends on the interrupt controller.
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[PRELIMINARY: the dma channel allocation will change once there are
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official DMA bindings]
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- dmas : Two or more DMA channel specifiers following the convention outlined
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in bindings/dma/dma.txt
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- tx-dma-channel: The dma channel specifier for tx operations. The format of
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the dma specifier depends on the dma controller.
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- rx-dma-channel: The dma channel specifier for rx operations. The format of
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the dma specifier depends on the dma controller.
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- dma-names: Names for the dma channels. There must be at least one channel
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named "tx" for transmit and named "rx" for receive.
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Required Board Specific Properties:
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@@ -42,15 +39,13 @@ Optional Board Specific Properties:
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- num-cs: Specifies the number of chip select lines supported. If
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not specified, the default number of chip select lines is set to 1.
|
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- cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt)
|
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SPI Controller specific data in SPI slave nodes:
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- The spi slave nodes should provide the following information which is required
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by the spi controller.
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- cs-gpio: A gpio specifier that specifies the gpio line used as
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the slave select line by the spi controller. The format of the gpio
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specifier depends on the gpio controller.
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- samsung,spi-feedback-delay: The sampling phase shift to be applied on the
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miso line (to account for any lag in the miso line). The following are the
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valid values.
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@@ -74,8 +69,11 @@ Example:
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compatible = "samsung,exynos4210-spi";
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reg = <0x12d20000 0x100>;
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interrupts = <0 66 0>;
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tx-dma-channel = <&pdma0 5>;
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rx-dma-channel = <&pdma0 4>;
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dmas = <&pdma0 5
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&pdma0 4>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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- Board Specific Portion:
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@@ -85,6 +83,7 @@ Example:
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_bus>;
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cs-gpios = <&gpa2 5 0>;
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w25q80bw@0 {
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#address-cells = <1>;
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@@ -94,7 +93,6 @@ Example:
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spi-max-frequency = <10000>;
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controller-data {
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cs-gpio = <&gpa2 5 1 0 3>;
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samsung,spi-feedback-delay = <0>;
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};
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@@ -168,6 +168,7 @@
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};
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spi_2: spi@13940000 {
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cs-gpios = <&gpc1 2 0>;
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status = "okay";
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w25x80@0 {
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@@ -178,7 +179,6 @@
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spi-max-frequency = <1000000>;
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controller-data {
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cs-gpio = <&gpc1 2 0>;
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samsung,spi-feedback-delay = <0>;
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};
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@@ -589,6 +589,7 @@
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spi_1: spi@13930000 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_bus>;
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cs-gpios = <&gpb 5 0>;
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status = "okay";
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s5c73m3_spi: s5c73m3 {
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@@ -596,7 +597,6 @@
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spi-max-frequency = <50000000>;
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reg = <0>;
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controller-data {
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cs-gpio = <&gpb 5 0>;
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samsung,spi-feedback-delay = <2>;
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};
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};
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@@ -316,6 +316,7 @@
|
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};
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spi_1: spi@12d30000 {
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cs-gpios = <&gpa2 5 0>;
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status = "okay";
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w25q80bw@0 {
|
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@@ -326,7 +327,6 @@
|
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spi-max-frequency = <1000000>;
|
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|
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controller-data {
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cs-gpio = <&gpa2 5 0>;
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samsung,spi-feedback-delay = <0>;
|
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};
|
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|
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|
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+14
-2
@@ -382,9 +382,21 @@ config SPI_PXA2XX
|
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config SPI_PXA2XX_PCI
|
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def_tristate SPI_PXA2XX && PCI
|
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|
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config SPI_ROCKCHIP
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tristate "Rockchip SPI controller driver"
|
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depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH
|
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help
|
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This selects a driver for Rockchip SPI controller.
|
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|
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If you say yes to this option, support will be included for
|
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RK3066, RK3188 and RK3288 families of SPI controller.
|
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Rockchip SPI controller support DMA transport and PIO mode.
|
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The main usecase of this controller is to use spi flash as boot
|
||||
device.
|
||||
|
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config SPI_RSPI
|
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tristate "Renesas RSPI/QSPI controller"
|
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depends on (SUPERH && SH_DMAE_BASE) || ARCH_SHMOBILE
|
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depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
|
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help
|
||||
SPI driver for Renesas RSPI and QSPI blocks.
|
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|
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@@ -434,7 +446,7 @@ config SPI_SC18IS602
|
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|
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config SPI_SH_MSIOF
|
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tristate "SuperH MSIOF SPI controller"
|
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depends on HAVE_CLK
|
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depends on HAVE_CLK && HAS_DMA
|
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depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
|
||||
help
|
||||
SPI driver for SuperH and SH Mobile MSIOF blocks.
|
||||
|
||||
@@ -61,6 +61,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
|
||||
obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
|
||||
obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
|
||||
obj-$(CONFIG_SPI_QUP) += spi-qup.o
|
||||
obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
|
||||
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
|
||||
obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
|
||||
spi-s3c24xx-hw-y := spi-s3c24xx.o
|
||||
|
||||
@@ -660,10 +660,9 @@ static int adi_spi_setup(struct spi_device *spi)
|
||||
struct adi_spi3_chip *chip_info = spi->controller_data;
|
||||
|
||||
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
|
||||
if (!chip) {
|
||||
dev_err(&spi->dev, "can not allocate chip data\n");
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (chip_info) {
|
||||
if (chip_info->control & ~ctl_reg) {
|
||||
dev_err(&spi->dev,
|
||||
|
||||
+8
-14
@@ -597,21 +597,15 @@ static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
|
||||
goto err_exit;
|
||||
|
||||
/* Send both scatterlists */
|
||||
rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
|
||||
&as->dma.sgrx,
|
||||
1,
|
||||
DMA_FROM_DEVICE,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
|
||||
NULL);
|
||||
rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
|
||||
DMA_FROM_DEVICE,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
if (!rxdesc)
|
||||
goto err_dma;
|
||||
|
||||
txdesc = txchan->device->device_prep_slave_sg(txchan,
|
||||
&as->dma.sgtx,
|
||||
1,
|
||||
DMA_TO_DEVICE,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
|
||||
NULL);
|
||||
txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
|
||||
DMA_TO_DEVICE,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
if (!txdesc)
|
||||
goto err_dma;
|
||||
|
||||
@@ -1018,7 +1012,7 @@ static int atmel_spi_setup(struct spi_device *spi)
|
||||
csr |= SPI_BF(DLYBCT, 0);
|
||||
|
||||
/* chipselect must have been muxed as GPIO (e.g. in board setup) */
|
||||
npcs_pin = (unsigned int)spi->controller_data;
|
||||
npcs_pin = (unsigned long)spi->controller_data;
|
||||
|
||||
if (gpio_is_valid(spi->cs_gpio))
|
||||
npcs_pin = spi->cs_gpio;
|
||||
@@ -1253,7 +1247,7 @@ msg_done:
|
||||
static void atmel_spi_cleanup(struct spi_device *spi)
|
||||
{
|
||||
struct atmel_spi_device *asd = spi->controller_state;
|
||||
unsigned gpio = (unsigned) spi->controller_data;
|
||||
unsigned gpio = (unsigned long) spi->controller_data;
|
||||
|
||||
if (!asd)
|
||||
return;
|
||||
|
||||
@@ -925,8 +925,7 @@ err_no_txdma:
|
||||
iounmap((void __iomem *)hw->regs);
|
||||
|
||||
err_ioremap:
|
||||
release_resource(hw->ioarea);
|
||||
kfree(hw->ioarea);
|
||||
release_mem_region(r->start, sizeof(psc_spi_t));
|
||||
|
||||
err_no_iores:
|
||||
err_no_pdata:
|
||||
@@ -946,8 +945,7 @@ static int au1550_spi_remove(struct platform_device *pdev)
|
||||
spi_bitbang_stop(&hw->bitbang);
|
||||
free_irq(hw->irq, hw);
|
||||
iounmap((void __iomem *)hw->regs);
|
||||
release_resource(hw->ioarea);
|
||||
kfree(hw->ioarea);
|
||||
release_mem_region(r->start, sizeof(psc_spi_t));
|
||||
|
||||
if (hw->usedma) {
|
||||
au1550_spi_dma_rxtmp_free(hw);
|
||||
|
||||
@@ -205,18 +205,30 @@ static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
|
||||
static void cdns_spi_config_clock_mode(struct spi_device *spi)
|
||||
{
|
||||
struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
|
||||
u32 ctrl_reg;
|
||||
u32 ctrl_reg, new_ctrl_reg;
|
||||
|
||||
ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
|
||||
new_ctrl_reg = ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
|
||||
|
||||
/* Set the SPI clock phase and clock polarity */
|
||||
ctrl_reg &= ~(CDNS_SPI_CR_CPHA_MASK | CDNS_SPI_CR_CPOL_MASK);
|
||||
new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA_MASK | CDNS_SPI_CR_CPOL_MASK);
|
||||
if (spi->mode & SPI_CPHA)
|
||||
ctrl_reg |= CDNS_SPI_CR_CPHA_MASK;
|
||||
new_ctrl_reg |= CDNS_SPI_CR_CPHA_MASK;
|
||||
if (spi->mode & SPI_CPOL)
|
||||
ctrl_reg |= CDNS_SPI_CR_CPOL_MASK;
|
||||
new_ctrl_reg |= CDNS_SPI_CR_CPOL_MASK;
|
||||
|
||||
cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
|
||||
if (new_ctrl_reg != ctrl_reg) {
|
||||
/*
|
||||
* Just writing the CR register does not seem to apply the clock
|
||||
* setting changes. This is problematic when changing the clock
|
||||
* polarity as it will cause the SPI slave to see spurious clock
|
||||
* transitions. To workaround the issue toggle the ER register.
|
||||
*/
|
||||
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
|
||||
CDNS_SPI_ER_DISABLE_MASK);
|
||||
cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, new_ctrl_reg);
|
||||
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
|
||||
CDNS_SPI_ER_ENABLE_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -370,6 +382,12 @@ static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
|
||||
|
||||
return status;
|
||||
}
|
||||
static int cdns_prepare_message(struct spi_master *master,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
cdns_spi_config_clock_mode(msg->spi);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* cdns_transfer_one - Initiates the SPI transfer
|
||||
@@ -416,8 +434,6 @@ static int cdns_prepare_transfer_hardware(struct spi_master *master)
|
||||
{
|
||||
struct cdns_spi *xspi = spi_master_get_devdata(master);
|
||||
|
||||
cdns_spi_config_clock_mode(master->cur_msg->spi);
|
||||
|
||||
cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
|
||||
CDNS_SPI_ER_ENABLE_MASK);
|
||||
|
||||
@@ -532,6 +548,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
|
||||
xspi->is_decoded_cs = 0;
|
||||
|
||||
master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
|
||||
master->prepare_message = cdns_prepare_message;
|
||||
master->transfer_one = cdns_transfer_one;
|
||||
master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
|
||||
master->set_cs = cdns_spi_chipselect;
|
||||
@@ -647,7 +664,7 @@ static int __maybe_unused cdns_spi_resume(struct device *dev)
|
||||
static SIMPLE_DEV_PM_OPS(cdns_spi_dev_pm_ops, cdns_spi_suspend,
|
||||
cdns_spi_resume);
|
||||
|
||||
static struct of_device_id cdns_spi_of_match[] = {
|
||||
static const struct of_device_id cdns_spi_of_match[] = {
|
||||
{ .compatible = "xlnx,zynq-spi-r1p6" },
|
||||
{ .compatible = "cdns,spi-r1p6" },
|
||||
{ /* end of table */ }
|
||||
|
||||
@@ -184,8 +184,6 @@ static int spi_clps711x_probe(struct platform_device *pdev)
|
||||
}
|
||||
master->max_speed_hz = clk_get_rate(hw->spi_clk);
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
|
||||
hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3");
|
||||
if (IS_ERR(hw->syscon)) {
|
||||
ret = PTR_ERR(hw->syscon);
|
||||
|
||||
+54
-20
@@ -30,6 +30,7 @@
|
||||
#include <linux/edma.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/spi_bitbang.h>
|
||||
#include <linux/slab.h>
|
||||
@@ -38,8 +39,6 @@
|
||||
|
||||
#define SPI_NO_RESOURCE ((resource_size_t)-1)
|
||||
|
||||
#define SPI_MAX_CHIPSELECT 2
|
||||
|
||||
#define CS_DEFAULT 0xFF
|
||||
|
||||
#define SPIFMT_PHASE_MASK BIT(16)
|
||||
@@ -142,7 +141,7 @@ struct davinci_spi {
|
||||
void (*get_rx)(u32 rx_data, struct davinci_spi *);
|
||||
u32 (*get_tx)(struct davinci_spi *);
|
||||
|
||||
u8 bytes_per_word[SPI_MAX_CHIPSELECT];
|
||||
u8 *bytes_per_word;
|
||||
};
|
||||
|
||||
static struct davinci_spi_config davinci_spi_default_cfg;
|
||||
@@ -213,13 +212,16 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
|
||||
u8 chip_sel = spi->chip_select;
|
||||
u16 spidat1 = CS_DEFAULT;
|
||||
bool gpio_chipsel = false;
|
||||
int gpio;
|
||||
|
||||
dspi = spi_master_get_devdata(spi->master);
|
||||
pdata = &dspi->pdata;
|
||||
|
||||
if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
|
||||
pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
|
||||
if (spi->cs_gpio >= 0) {
|
||||
/* SPI core parse and update master->cs_gpio */
|
||||
gpio_chipsel = true;
|
||||
gpio = spi->cs_gpio;
|
||||
}
|
||||
|
||||
/*
|
||||
* Board specific chip select logic decides the polarity and cs
|
||||
@@ -227,9 +229,9 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
|
||||
*/
|
||||
if (gpio_chipsel) {
|
||||
if (value == BITBANG_CS_ACTIVE)
|
||||
gpio_set_value(pdata->chip_sel[chip_sel], 0);
|
||||
gpio_set_value(gpio, spi->mode & SPI_CS_HIGH);
|
||||
else
|
||||
gpio_set_value(pdata->chip_sel[chip_sel], 1);
|
||||
gpio_set_value(gpio, !(spi->mode & SPI_CS_HIGH));
|
||||
} else {
|
||||
if (value == BITBANG_CS_ACTIVE) {
|
||||
spidat1 |= SPIDAT1_CSHOLD_MASK;
|
||||
@@ -392,17 +394,40 @@ static int davinci_spi_setup(struct spi_device *spi)
|
||||
int retval = 0;
|
||||
struct davinci_spi *dspi;
|
||||
struct davinci_spi_platform_data *pdata;
|
||||
struct spi_master *master = spi->master;
|
||||
struct device_node *np = spi->dev.of_node;
|
||||
bool internal_cs = true;
|
||||
unsigned long flags = GPIOF_DIR_OUT;
|
||||
|
||||
dspi = spi_master_get_devdata(spi->master);
|
||||
pdata = &dspi->pdata;
|
||||
|
||||
if (!(spi->mode & SPI_NO_CS)) {
|
||||
if ((pdata->chip_sel == NULL) ||
|
||||
(pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
|
||||
set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
|
||||
flags |= (spi->mode & SPI_CS_HIGH) ? GPIOF_INIT_LOW : GPIOF_INIT_HIGH;
|
||||
|
||||
if (!(spi->mode & SPI_NO_CS)) {
|
||||
if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
|
||||
retval = gpio_request_one(spi->cs_gpio,
|
||||
flags, dev_name(&spi->dev));
|
||||
internal_cs = false;
|
||||
} else if (pdata->chip_sel &&
|
||||
spi->chip_select < pdata->num_chipselect &&
|
||||
pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) {
|
||||
spi->cs_gpio = pdata->chip_sel[spi->chip_select];
|
||||
retval = gpio_request_one(spi->cs_gpio,
|
||||
flags, dev_name(&spi->dev));
|
||||
internal_cs = false;
|
||||
}
|
||||
}
|
||||
|
||||
if (retval) {
|
||||
dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
|
||||
spi->cs_gpio, retval);
|
||||
return retval;
|
||||
}
|
||||
|
||||
if (internal_cs)
|
||||
set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
|
||||
|
||||
if (spi->mode & SPI_READY)
|
||||
set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
|
||||
|
||||
@@ -414,6 +439,12 @@ static int davinci_spi_setup(struct spi_device *spi)
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void davinci_spi_cleanup(struct spi_device *spi)
|
||||
{
|
||||
if (spi->cs_gpio >= 0)
|
||||
gpio_free(spi->cs_gpio);
|
||||
}
|
||||
|
||||
static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
|
||||
{
|
||||
struct device *sdev = dspi->bitbang.master->dev.parent;
|
||||
@@ -812,6 +843,8 @@ static int spi_davinci_get_pdata(struct platform_device *pdev,
|
||||
|
||||
/*
|
||||
* default num_cs is 1 and all chipsel are internal to the chip
|
||||
* indicated by chip_sel being NULL or cs_gpios being NULL or
|
||||
* set to -ENOENT. num-cs includes internal as well as gpios.
|
||||
* indicated by chip_sel being NULL. GPIO based CS is not
|
||||
* supported yet in DT bindings.
|
||||
*/
|
||||
@@ -850,7 +883,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
|
||||
struct resource *r;
|
||||
resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
|
||||
resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
|
||||
int i = 0, ret = 0;
|
||||
int ret = 0;
|
||||
u32 spipc0;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
|
||||
@@ -876,6 +909,14 @@ static int davinci_spi_probe(struct platform_device *pdev)
|
||||
/* pdata in dspi is now updated and point pdata to that */
|
||||
pdata = &dspi->pdata;
|
||||
|
||||
dspi->bytes_per_word = devm_kzalloc(&pdev->dev,
|
||||
sizeof(*dspi->bytes_per_word) *
|
||||
pdata->num_chipselect, GFP_KERNEL);
|
||||
if (dspi->bytes_per_word == NULL) {
|
||||
ret = -ENOMEM;
|
||||
goto free_master;
|
||||
}
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (r == NULL) {
|
||||
ret = -ENOENT;
|
||||
@@ -915,6 +956,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
|
||||
master->num_chipselect = pdata->num_chipselect;
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
|
||||
master->setup = davinci_spi_setup;
|
||||
master->cleanup = davinci_spi_cleanup;
|
||||
|
||||
dspi->bitbang.chipselect = davinci_spi_chipselect;
|
||||
dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
|
||||
@@ -962,14 +1004,6 @@ static int davinci_spi_probe(struct platform_device *pdev)
|
||||
spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
|
||||
iowrite32(spipc0, dspi->base + SPIPC0);
|
||||
|
||||
/* initialize chip selects */
|
||||
if (pdata->chip_sel) {
|
||||
for (i = 0; i < pdata->num_chipselect; i++) {
|
||||
if (pdata->chip_sel[i] != SPI_INTERN_CS)
|
||||
gpio_direction_output(pdata->chip_sel[i], 1);
|
||||
}
|
||||
}
|
||||
|
||||
if (pdata->intr_line)
|
||||
iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
|
||||
else
|
||||
|
||||
@@ -16,7 +16,9 @@
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include "spi-dw.h"
|
||||
|
||||
@@ -33,6 +35,7 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
|
||||
struct dw_spi *dws;
|
||||
struct resource *mem;
|
||||
int ret;
|
||||
int num_cs;
|
||||
|
||||
dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
|
||||
GFP_KERNEL);
|
||||
@@ -68,9 +71,16 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
|
||||
dws->bus_num = pdev->id;
|
||||
dws->num_cs = 4;
|
||||
|
||||
dws->max_freq = clk_get_rate(dwsmmio->clk);
|
||||
|
||||
num_cs = 4;
|
||||
|
||||
if (pdev->dev.of_node)
|
||||
of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
|
||||
|
||||
dws->num_cs = num_cs;
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
int i;
|
||||
|
||||
@@ -114,12 +124,19 @@ static int dw_spi_mmio_remove(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id dw_spi_mmio_of_match[] = {
|
||||
{ .compatible = "snps,dw-apb-ssi", },
|
||||
{ /* end of table */}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
|
||||
|
||||
static struct platform_driver dw_spi_mmio_driver = {
|
||||
.probe = dw_spi_mmio_probe,
|
||||
.remove = dw_spi_mmio_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = dw_spi_mmio_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(dw_spi_mmio_driver);
|
||||
|
||||
@@ -294,10 +294,16 @@ static void efm32_spi_probe_dt(struct platform_device *pdev,
|
||||
u32 location;
|
||||
int ret;
|
||||
|
||||
ret = of_property_read_u32(np, "efm32,location", &location);
|
||||
ret = of_property_read_u32(np, "energymicro,location", &location);
|
||||
|
||||
if (ret)
|
||||
/* fall back to wrongly namespaced property */
|
||||
ret = of_property_read_u32(np, "efm32,location", &location);
|
||||
|
||||
if (ret)
|
||||
/* fall back to old and (wrongly) generic property "location" */
|
||||
ret = of_property_read_u32(np, "location", &location);
|
||||
|
||||
if (!ret) {
|
||||
dev_dbg(&pdev->dev, "using location %u\n", location);
|
||||
} else {
|
||||
|
||||
@@ -425,8 +425,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
|
||||
master->unprepare_transfer_hardware = falcon_sflash_unprepare_xfer;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
ret = devm_spi_register_master(&pdev->dev, master);
|
||||
if (ret)
|
||||
spi_master_put(master);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user