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Merge branch 'wells/lpc32xx-arch_v2' of git://git.lpclinux.com/linux-2.6-lpc into devel-stable
This commit is contained in:
Russell King
@@ -32,8 +32,6 @@ DocBook/
|
||||
- directory with DocBook templates etc. for kernel documentation.
|
||||
HOWTO
|
||||
- the process and procedures of how to do Linux kernel development.
|
||||
IO-mapping.txt
|
||||
- how to access I/O mapped memory from within device drivers.
|
||||
IPMI.txt
|
||||
- info on Linux Intelligent Platform Management Interface (IPMI) Driver.
|
||||
IRQ-affinity.txt
|
||||
@@ -84,6 +82,8 @@ blockdev/
|
||||
- info on block devices & drivers
|
||||
btmrvl.txt
|
||||
- info on Marvell Bluetooth driver usage.
|
||||
bus-virt-phys-mapping.txt
|
||||
- how to access I/O mapped memory from within device drivers.
|
||||
cachetlb.txt
|
||||
- describes the cache/TLB flushing interfaces Linux uses.
|
||||
cdrom/
|
||||
@@ -168,6 +168,8 @@ initrd.txt
|
||||
- how to use the RAM disk as an initial/temporary root filesystem.
|
||||
input/
|
||||
- info on Linux input device support.
|
||||
io-mapping.txt
|
||||
- description of io_mapping functions in linux/io-mapping.h
|
||||
io_ordering.txt
|
||||
- info on ordering I/O writes to memory-mapped addresses.
|
||||
ioctl/
|
||||
|
||||
@@ -647,3 +647,10 @@ Who: Stefan Richter <stefanr@s5r6.in-berlin.de>
|
||||
|
||||
----------------------------
|
||||
|
||||
What: The acpi_sleep=s4_nonvs command line option
|
||||
When: 2.6.37
|
||||
Files: arch/x86/kernel/acpi/sleep.c
|
||||
Why: superseded by acpi_sleep=nonvs
|
||||
Who: Rafael J. Wysocki <rjw@sisk.pl>
|
||||
|
||||
----------------------------
|
||||
|
||||
@@ -254,8 +254,8 @@ and is between 256 and 4096 characters. It is defined in the file
|
||||
control method, with respect to putting devices into
|
||||
low power states, to be enforced (the ACPI 2.0 ordering
|
||||
of _PTS is used by default).
|
||||
s4_nonvs prevents the kernel from saving/restoring the
|
||||
ACPI NVS memory during hibernation.
|
||||
nonvs prevents the kernel from saving/restoring the
|
||||
ACPI NVS memory during suspend/hibernation and resume.
|
||||
sci_force_enable causes the kernel to set SCI_EN directly
|
||||
on resume from S1/S3 (which is against the ACPI spec,
|
||||
but some broken systems don't work without it).
|
||||
|
||||
@@ -5336,6 +5336,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next-2.6.git
|
||||
S: Maintained
|
||||
F: arch/sparc/
|
||||
F: drivers/sbus
|
||||
|
||||
SPARC SERIAL DRIVERS
|
||||
M: "David S. Miller" <davem@davemloft.net>
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
VERSION = 2
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 35
|
||||
EXTRAVERSION = -rc5
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Sheep on Meth
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
||||
@@ -483,6 +483,19 @@ config ARCH_LOKI
|
||||
help
|
||||
Support for the Marvell Loki (88RC8480) SoC.
|
||||
|
||||
config ARCH_LPC32XX
|
||||
bool "NXP LPC32XX"
|
||||
select CPU_ARM926T
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select HAVE_IDE
|
||||
select ARM_AMBA
|
||||
select USB_ARCH_HAS_OHCI
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select COMMON_CLKDEV
|
||||
select GENERIC_TIME
|
||||
select GENERIC_CLOCKEVENTS
|
||||
help
|
||||
Support for the NXP LPC32XX family of processors
|
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|
||||
config ARCH_MV78XX0
|
||||
bool "Marvell MV78xx0"
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||||
select CPU_FEROCEON
|
||||
@@ -847,6 +860,8 @@ source "arch/arm/mach-lh7a40x/Kconfig"
|
||||
|
||||
source "arch/arm/mach-loki/Kconfig"
|
||||
|
||||
source "arch/arm/mach-lpc32xx/Kconfig"
|
||||
|
||||
source "arch/arm/mach-msm/Kconfig"
|
||||
|
||||
source "arch/arm/mach-mv78xx0/Kconfig"
|
||||
|
||||
@@ -146,6 +146,7 @@ machine-$(CONFIG_ARCH_KS8695) := ks8695
|
||||
machine-$(CONFIG_ARCH_L7200) := l7200
|
||||
machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
|
||||
machine-$(CONFIG_ARCH_LOKI) := loki
|
||||
machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
|
||||
machine-$(CONFIG_ARCH_MMP) := mmp
|
||||
machine-$(CONFIG_ARCH_MSM) := msm
|
||||
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/hardware/clps7111.h>
|
||||
|
||||
.macro addruart, rx, tmp
|
||||
|
||||
@@ -232,7 +232,7 @@ EXPORT_SYMBOL(__bus_to_virt);
|
||||
|
||||
unsigned long __pfn_to_bus(unsigned long pfn)
|
||||
{
|
||||
return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET));
|
||||
return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
|
||||
}
|
||||
EXPORT_SYMBOL(__pfn_to_bus);
|
||||
|
||||
|
||||
@@ -11,8 +11,10 @@
|
||||
*
|
||||
*/
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||||
|
||||
.equ io_virt, IO_BASE
|
||||
.equ io_phys, IO_START
|
||||
#include <mach/hardware.h>
|
||||
|
||||
.equ io_virt, IO_VIRT
|
||||
.equ io_phys, IO_PHYS
|
||||
|
||||
.macro addruart, rx, tmp
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H
|
||||
#define __ARCH_KIRKWOOD_TSX1X_COMMON_H
|
||||
|
||||
extern void qnap_tsx1x_register_flash(void);
|
||||
extern void __init qnap_tsx1x_register_flash(void);
|
||||
extern void qnap_tsx1x_power_off(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
if ARCH_LPC32XX
|
||||
|
||||
menu "Individual UART enable selections"
|
||||
|
||||
config ARCH_LPC32XX_UART3_SELECT
|
||||
bool "Add support for standard UART3"
|
||||
help
|
||||
Adds support for standard UART 3 when the 8250 serial support
|
||||
is enabled.
|
||||
|
||||
config ARCH_LPC32XX_UART4_SELECT
|
||||
bool "Add support for standard UART4"
|
||||
help
|
||||
Adds support for standard UART 4 when the 8250 serial support
|
||||
is enabled.
|
||||
|
||||
config ARCH_LPC32XX_UART5_SELECT
|
||||
bool "Add support for standard UART5"
|
||||
default y
|
||||
help
|
||||
Adds support for standard UART 5 when the 8250 serial support
|
||||
is enabled.
|
||||
|
||||
config ARCH_LPC32XX_UART6_SELECT
|
||||
bool "Add support for standard UART6"
|
||||
help
|
||||
Adds support for standard UART 6 when the 8250 serial support
|
||||
is enabled.
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
||||
@@ -0,0 +1,8 @@
|
||||
#
|
||||
# Makefile for the linux kernel.
|
||||
#
|
||||
|
||||
obj-y := timer.o irq.o common.o serial.o clock.o
|
||||
obj-y += gpiolib.o pm.o suspend.o
|
||||
obj-y += phy3250.o
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
zreladdr-y := 0x80008000
|
||||
params_phys-y := 0x80000100
|
||||
initrd_phys-y := 0x82000000
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* arch/arm/mach-lpc32xx/clock.h
|
||||
*
|
||||
* Author: Kevin Wells <kevin.wells@nxp.com>
|
||||
*
|
||||
* Copyright (C) 2010 NXP Semiconductors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __LPC32XX_CLOCK_H
|
||||
#define __LPC32XX_CLOCK_H
|
||||
|
||||
struct clk {
|
||||
struct list_head node;
|
||||
struct clk *parent;
|
||||
u32 rate;
|
||||
u32 usecount;
|
||||
|
||||
int (*set_rate) (struct clk *, unsigned long);
|
||||
unsigned long (*round_rate) (struct clk *, unsigned long);
|
||||
unsigned long (*get_rate) (struct clk *clk);
|
||||
int (*enable) (struct clk *, int);
|
||||
|
||||
/* Register address and bit mask for simple clocks */
|
||||
void __iomem *enable_reg;
|
||||
u32 enable_mask;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,271 @@
|
||||
/*
|
||||
* arch/arm/mach-lpc32xx/common.c
|
||||
*
|
||||
* Author: Kevin Wells <kevin.wells@nxp.com>
|
||||
*
|
||||
* Copyright (C) 2010 NXP Semiconductors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c-pnx.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/i2c.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* Watchdog timer
|
||||
*/
|
||||
static struct resource watchdog_resources[] = {
|
||||
[0] = {
|
||||
.start = LPC32XX_WDTIM_BASE,
|
||||
.end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device lpc32xx_watchdog_device = {
|
||||
.name = "pnx4008-watchdog",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(watchdog_resources),
|
||||
.resource = watchdog_resources,
|
||||
};
|
||||
|
||||
/*
|
||||
* I2C busses
|
||||
*/
|
||||
static struct i2c_pnx_data i2c0_data = {
|
||||
.name = I2C_CHIP_NAME "1",
|
||||
.base = LPC32XX_I2C1_BASE,
|
||||
.irq = IRQ_LPC32XX_I2C_1,
|
||||
};
|
||||
|
||||
static struct i2c_pnx_data i2c1_data = {
|
||||
.name = I2C_CHIP_NAME "2",
|
||||
.base = LPC32XX_I2C2_BASE,
|
||||
.irq = IRQ_LPC32XX_I2C_2,
|
||||
};
|
||||
|
||||
static struct i2c_pnx_data i2c2_data = {
|
||||
.name = "USB-I2C",
|
||||
.base = LPC32XX_OTG_I2C_BASE,
|
||||
.irq = IRQ_LPC32XX_USB_I2C,
|
||||
};
|
||||
|
||||
struct platform_device lpc32xx_i2c0_device = {
|
||||
.name = "pnx-i2c",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &i2c0_data,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device lpc32xx_i2c1_device = {
|
||||
.name = "pnx-i2c",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &i2c1_data,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device lpc32xx_i2c2_device = {
|
||||
.name = "pnx-i2c",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.platform_data = &i2c2_data,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Returns the unique ID for the device
|
||||
*/
|
||||
void lpc32xx_get_uid(u32 devid[4])
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns SYSCLK source
|
||||
* 0 = PLL397, 1 = main oscillator
|
||||
*/
|
||||
int clk_is_sysclk_mainosc(void)
|
||||
{
|
||||
if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
|
||||
LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* System reset via the watchdog timer
|
||||
*/
|
||||
void lpc32xx_watchdog_reset(void)
|
||||
{
|
||||
/* Make sure WDT clocks are enabled */
|
||||
__raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
|
||||
LPC32XX_CLKPWR_TIMER_CLK_CTRL);
|
||||
|
||||
/* Instant assert of RESETOUT_N with pulse length 1mS */
|
||||
__raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
|
||||
__raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
|
||||
}
|
||||
|
||||
/*
|
||||
* Detects and returns IRAM size for the device variation
|
||||
*/
|
||||
#define LPC32XX_IRAM_BANK_SIZE SZ_128K
|
||||
static u32 iram_size;
|
||||
u32 lpc32xx_return_iram_size(void)
|
||||
{
|
||||
if (iram_size == 0) {
|
||||
u32 savedval1, savedval2;
|
||||
void __iomem *iramptr1, *iramptr2;
|
||||
|
||||
iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
|
||||
iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
|
||||
savedval1 = __raw_readl(iramptr1);
|
||||
savedval2 = __raw_readl(iramptr2);
|
||||
|
||||
if (savedval1 == savedval2) {
|
||||
__raw_writel(savedval2 + 1, iramptr2);
|
||||
if (__raw_readl(iramptr1) == savedval2 + 1)
|
||||
iram_size = LPC32XX_IRAM_BANK_SIZE;
|
||||
else
|
||||
iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
|
||||
__raw_writel(savedval2, iramptr2);
|
||||
} else
|
||||
iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
|
||||
}
|
||||
|
||||
return iram_size;
|
||||
}
|
||||
|
||||
/*
|
||||
* Computes PLL rate from PLL register and input clock
|
||||
*/
|
||||
u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
|
||||
{
|
||||
u32 ilfreq, p, m, n, fcco, fref, cfreq;
|
||||
int mode;
|
||||
|
||||
/*
|
||||
* PLL requirements
|
||||
* ifreq must be >= 1MHz and <= 20MHz
|
||||
* FCCO must be >= 156MHz and <= 320MHz
|
||||
* FREF must be >= 1MHz and <= 27MHz
|
||||
* Assume the passed input data is not valid
|
||||
*/
|
||||
|
||||
ilfreq = ifreq;
|
||||
m = pllsetup->pll_m;
|
||||
n = pllsetup->pll_n;
|
||||
p = pllsetup->pll_p;
|
||||
|
||||
mode = (pllsetup->cco_bypass_b15 << 2) |
|
||||
(pllsetup->direct_output_b14 << 1) |
|
||||
pllsetup->fdbk_div_ctrl_b13;
|
||||
|
||||
switch (mode) {
|
||||
case 0x0: /* Non-integer mode */
|
||||
cfreq = (m * ilfreq) / (2 * p * n);
|
||||
fcco = (m * ilfreq) / n;
|
||||
fref = ilfreq / n;
|
||||
break;
|
||||
|
||||
case 0x1: /* integer mode */
|
||||
cfreq = (m * ilfreq) / n;
|
||||
fcco = (m * ilfreq) / (n * 2 * p);
|
||||
fref = ilfreq / n;
|
||||
break;
|
||||
|
||||
case 0x2:
|
||||
case 0x3: /* Direct mode */
|
||||
cfreq = (m * ilfreq) / n;
|
||||
fcco = cfreq;
|
||||
fref = ilfreq / n;
|
||||
break;
|
||||
|
||||
case 0x4:
|
||||
case 0x5: /* Bypass mode */
|
||||
cfreq = ilfreq / (2 * p);
|
||||
fcco = 156000000;
|
||||
fref = 1000000;
|
||||
break;
|
||||
|
||||
case 0x6:
|
||||
case 0x7: /* Direct bypass mode */
|
||||
default:
|
||||
cfreq = ilfreq;
|
||||
fcco = 156000000;
|
||||
fref = 1000000;
|
||||
break;
|
||||
}
|
||||
|
||||
if (fcco < 156000000 || fcco > 320000000)
|
||||
cfreq = 0;
|
||||
|
||||
if (fref < 1000000 || fref > 27000000)
|
||||
cfreq = 0;
|
||||
|
||||
return (u32) cfreq;
|
||||
}
|
||||
|
||||
u32 clk_get_pclk_div(void)
|
||||
{
|
||||
return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
|
||||
}
|
||||
|
||||
static struct map_desc lpc32xx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = IO_ADDRESS(LPC32XX_AHB0_START),
|
||||
.pfn = __phys_to_pfn(LPC32XX_AHB0_START),
|
||||
.length = LPC32XX_AHB0_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = IO_ADDRESS(LPC32XX_AHB1_START),
|
||||
.pfn = __phys_to_pfn(LPC32XX_AHB1_START),
|
||||
.length = LPC32XX_AHB1_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = IO_ADDRESS(LPC32XX_FABAPB_START),
|
||||
.pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
|
||||
.length = LPC32XX_FABAPB_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = IO_ADDRESS(LPC32XX_IRAM_BASE),
|
||||
.pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
|
||||
.length = (LPC32XX_IRAM_BANK_SIZE * 2),
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
};
|
||||
|
||||
void __init lpc32xx_map_io(void)
|
||||
{
|
||||
iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
|
||||
}
|
||||
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* arch/arm/mach-lpc32xx/common.h
|
||||
*
|
||||
* Author: Kevin Wells <kevin.wells@nxp.com>
|
||||
*
|
||||
* Copyright (C) 2009-2010 NXP Semiconductors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __LPC32XX_COMMON_H
|
||||
#define __LPC32XX_COMMON_H
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
/*
|
||||
* Arch specific platform device structures
|
||||
*/
|
||||
extern struct platform_device lpc32xx_watchdog_device;
|
||||
extern struct platform_device lpc32xx_i2c0_device;
|
||||
extern struct platform_device lpc32xx_i2c1_device;
|
||||
extern struct platform_device lpc32xx_i2c2_device;
|
||||
|
||||
/*
|
||||
* Other arch specific structures and functions
|
||||
*/
|
||||
extern struct sys_timer lpc32xx_timer;
|
||||
extern void __init lpc32xx_init_irq(void);
|
||||
extern void __init lpc32xx_map_io(void);
|
||||
extern void __init lpc32xx_serial_init(void);
|
||||
extern void __init lpc32xx_gpio_init(void);
|
||||
|
||||
/*
|
||||
* Structure used for setting up and querying the PLLS
|
||||
*/
|
||||
struct clk_pll_setup {
|
||||
int analog_on;
|
||||
int cco_bypass_b15;
|
||||
int direct_output_b14;
|
||||
int fdbk_div_ctrl_b13;
|
||||
int pll_p;
|
||||
int pll_n;
|
||||
u32 pll_m;
|
||||
};
|
||||
|
||||
extern int clk_is_sysclk_mainosc(void);
|
||||
extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup);
|
||||
extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
|
||||
extern u32 clk_get_pclk_div(void);
|
||||
|
||||
/*
|
||||
* Returns the LPC32xx unique 128-bit chip ID
|
||||
*/
|
||||
extern void lpc32xx_get_uid(u32 devid[4]);
|
||||
|
||||
extern void lpc32xx_watchdog_reset(void);
|
||||
extern u32 lpc32xx_return_iram_size(void);
|
||||
|
||||
/*
|
||||
* Pointers used for sizing and copying suspend function data
|
||||
*/
|
||||
extern int lpc32xx_sys_suspend(void);
|
||||
extern int lpc32xx_sys_suspend_sz;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,446 @@
|
||||
/*
|
||||
* arch/arm/mach-lpc32xx/gpiolib.c
|
||||
*
|
||||
* Author: Kevin Wells <kevin.wells@nxp.com>
|
||||
*
|
||||
* Copyright (C) 2010 NXP Semiconductors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
#include "common.h"
|
||||
|
||||
#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
|
||||
#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
|
||||
#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
|
||||
#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
|
||||
#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
|
||||
#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
|
||||
#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
|
||||
#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
|
||||
#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
|
||||
#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
|
||||
#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
|
||||
#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
|
||||
#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
|
||||
#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
|
||||
#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
|
||||
#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
|
||||
#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
|
||||
#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
|
||||
#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
|
||||
#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
|
||||
#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
|
||||
#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
|
||||
#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
|
||||
#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
|
||||
#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
|
||||
#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
|
||||
#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
|
||||
|
||||
#define GPIO012_PIN_TO_BIT(x) (1 << (x))
|
||||
#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
|
||||
#define GPO3_PIN_TO_BIT(x) (1 << (x))
|
||||
#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
|
||||
#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
|
||||
#define GPIO3_PIN_IN_SEL(x, y) ((x) >> GPIO3_PIN_IN_SHIFT(y))
|
||||
#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
|
||||
#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
|
||||
|
||||
struct gpio_regs {
|
||||
void __iomem *inp_state;
|
||||
void __iomem *outp_set;
|
||||
void __iomem *outp_clr;
|
||||
void __iomem *dir_set;
|
||||
void __iomem *dir_clr;
|
||||
};
|
||||
|
||||
/*
|
||||
* GPIO names
|
||||
*/
|
||||
static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
|
||||
"p0.0", "p0.1", "p0.2", "p0.3",
|
||||
"p0.4", "p0.5", "p0.6", "p0.7"
|
||||
};
|
||||
|
||||
static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
|
||||
"p1.0", "p1.1", "p1.2", "p1.3",
|
||||
"p1.4", "p1.5", "p1.6", "p1.7",
|
||||
"p1.8", "p1.9", "p1.10", "p1.11",
|
||||
"p1.12", "p1.13", "p1.14", "p1.15",
|
||||
"p1.16", "p1.17", "p1.18", "p1.19",
|
||||
"p1.20", "p1.21", "p1.22", "p1.23",
|
||||
};
|
||||
|
||||
static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
|
||||
"p2.0", "p2.1", "p2.2", "p2.3",
|
||||
"p2.4", "p2.5", "p2.6", "p2.7",
|
||||
"p2.8", "p2.9", "p2.10", "p2.11",
|
||||
"p2.12"
|
||||
};
|
||||
|
||||
static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
|
||||
"gpi000", "gpio01", "gpio02", "gpio03",
|
||||
"gpio04", "gpio05"
|
||||
};
|
||||
|
||||
static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
|
||||
"gpi00", "gpi01", "gpi02", "gpi03",
|
||||
"gpi04", "gpi05", "gpi06", "gpi07",
|
||||
"gpi08", "gpi09", NULL, NULL,
|
||||
NULL, NULL, NULL, "gpi15",
|
||||
"gpi16", "gpi17", "gpi18", "gpi19",
|
||||
"gpi20", "gpi21", "gpi22", "gpi23",
|
||||
"gpi24", "gpi25", "gpi26", "gpi27"
|
||||
};
|
||||
|
||||
static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
|
||||
"gpo00", "gpo01", "gpo02", "gpo03",
|
||||
"gpo04", "gpo05", "gpo06", "gpo07",
|
||||
"gpo08", "gpo09", "gpo10", "gpo11",
|
||||
"gpo12", "gpo13", "gpo14", "gpo15",
|
||||
"gpo16", "gpo17", "gpo18", "gpo19",
|
||||
"gpo20", "gpo21", "gpo22", "gpo23"
|
||||
};
|
||||
|
||||
static struct gpio_regs gpio_grp_regs_p0 = {
|
||||
.inp_state = LPC32XX_GPIO_P0_INP_STATE,
|
||||
.outp_set = LPC32XX_GPIO_P0_OUTP_SET,
|
||||
.outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
|
||||
.dir_set = LPC32XX_GPIO_P0_DIR_SET,
|
||||
.dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
|
||||
};
|
||||
|
||||
static struct gpio_regs gpio_grp_regs_p1 = {
|
||||
.inp_state = LPC32XX_GPIO_P1_INP_STATE,
|
||||
.outp_set = LPC32XX_GPIO_P1_OUTP_SET,
|
||||
.outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
|
||||
.dir_set = LPC32XX_GPIO_P1_DIR_SET,
|
||||
.dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
|
||||
};
|
||||
|
||||
static struct gpio_regs gpio_grp_regs_p2 = {
|
||||
.inp_state = LPC32XX_GPIO_P2_INP_STATE,
|
||||
.outp_set = LPC32XX_GPIO_P2_OUTP_SET,
|
||||
.outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
|
||||
.dir_set = LPC32XX_GPIO_P2_DIR_SET,
|
||||
.dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
|
||||
};
|
||||
|
||||
static struct gpio_regs gpio_grp_regs_p3 = {
|
||||
.inp_state = LPC32XX_GPIO_P3_INP_STATE,
|
||||
.outp_set = LPC32XX_GPIO_P3_OUTP_SET,
|
||||
.outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
|
||||
.dir_set = LPC32XX_GPIO_P2_DIR_SET,
|
||||
.dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
|
||||
};
|
||||
|
||||
struct lpc32xx_gpio_chip {
|
||||
struct gpio_chip chip;
|
||||
struct gpio_regs *gpio_grp;
|
||||
};
|
||||
|
||||
static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
|
||||
struct gpio_chip *gpc)
|
||||
{
|
||||
return container_of(gpc, struct lpc32xx_gpio_chip, chip);
|
||||
}
|
||||
|
||||
static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
|
||||
unsigned pin, int input)
|
||||
{
|
||||
if (input)
|
||||
__raw_writel(GPIO012_PIN_TO_BIT(pin),
|
||||
group->gpio_grp->dir_clr);
|
||||
else
|
||||
__raw_writel(GPIO012_PIN_TO_BIT(pin),
|
||||
group->gpio_grp->dir_set);
|
||||
}
|
||||
|
||||
static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
|
||||
unsigned pin, int input)
|
||||
{
|
||||
u32 u = GPIO3_PIN_TO_BIT(pin);
|
||||
|
||||
if (input)
|
||||
__raw_writel(u, group->gpio_grp->dir_clr);
|
||||
else
|
||||
__raw_writel(u, group->gpio_grp->dir_set);
|
||||
}
|
||||
|
||||
static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
|
||||
unsigned pin, int high)
|
||||
{
|
||||
if (high)
|
||||
__raw_writel(GPIO012_PIN_TO_BIT(pin),
|
||||
group->gpio_grp->outp_set);
|
||||
else
|
||||
__raw_writel(GPIO012_PIN_TO_BIT(pin),
|
||||
group->gpio_grp->outp_clr);
|
||||
}
|
||||
|
||||
static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
|
||||
unsigned pin, int high)
|
||||
{
|
||||
u32 u = GPIO3_PIN_TO_BIT(pin);
|
||||
|
||||
if (high)
|
||||
__raw_writel(u, group->gpio_grp->outp_set);
|
||||
else
|
||||
__raw_writel(u, group->gpio_grp->outp_clr);
|
||||
}
|
||||
|
||||
static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
|
||||
unsigned pin, int high)
|
||||
{
|
||||
if (high)
|
||||
__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
|
||||
else
|
||||
__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
|
||||
}
|
||||
|
||||
static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
|
||||
unsigned pin)
|
||||
{
|
||||
return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
|
||||
pin);
|
||||
}
|
||||
|
||||
static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
|
||||
unsigned pin)
|
||||
{
|
||||
int state = __raw_readl(group->gpio_grp->inp_state);
|
||||
|
||||
/*
|
||||
* P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
|
||||
* to bits 10..14, while GPIOP3-5 is mapped to bit 24.
|
||||
*/
|
||||
return GPIO3_PIN_IN_SEL(state, pin);
|
||||
}
|
||||
|
||||
static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
|
||||
unsigned pin)
|
||||
{
|
||||
return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
|
||||
}
|
||||
|
||||
/*
|
||||
* GENERIC_GPIO primitives.
|
||||
*/
|
||||
static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
|
||||
unsigned pin)
|
||||
{
|
||||
struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
|
||||
|
||||
__set_gpio_dir_p012(group, pin, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
|
||||
unsigned pin)
|
||||
{
|
||||
struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
|
||||
|
||||
__set_gpio_dir_p3(group, pin, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
|
||||
unsigned pin)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
|
||||
|
||||
return __get_gpio_state_p012(group, pin);
|
||||
}
|
||||
|
||||
static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
|
||||
|
||||
return __get_gpio_state_p3(group, pin);
|
||||
}
|
||||
|
||||
static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
|
||||
|
||||
return __get_gpi_state_p3(group, pin);
|
||||
}
|
||||
|
||||
static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
|
||||
int value)
|
||||
{
|
||||
struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
|
||||
|
||||
__set_gpio_dir_p012(group, pin, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
|
||||
int value)
|
||||
{
|
||||
struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
|
||||
|
||||
__set_gpio_dir_p3(group, pin, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
|
||||
int value)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
|
||||
int value)
|
||||
{
|
||||
struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
|
||||
|
||||
__set_gpio_level_p012(group, pin, value);
|
||||
}
|
||||
|
||||
static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
|
||||
int value)
|
||||
{
|
||||
struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
|
||||
|
||||
__set_gpio_level_p3(group, pin, value);
|
||||
}
|
||||
|
||||
static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
|
||||
int value)
|
||||
{
|
||||
struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
|
||||
|
||||
__set_gpo_level_p3(group, pin, value);
|
||||
}
|
||||
|
||||
static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
if (pin < chip->ngpio)
|
||||
return 0;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
|
||||
{
|
||||
.chip = {
|
||||
.label = "gpio_p0",
|
||||
.direction_input = lpc32xx_gpio_dir_input_p012,
|
||||
.get = lpc32xx_gpio_get_value_p012,
|
||||
.direction_output = lpc32xx_gpio_dir_output_p012,
|
||||
.set = lpc32xx_gpio_set_value_p012,
|
||||
.request = lpc32xx_gpio_request,
|
||||
.base = LPC32XX_GPIO_P0_GRP,
|
||||
.ngpio = LPC32XX_GPIO_P0_MAX,
|
||||
.names = gpio_p0_names,
|
||||
.can_sleep = 0,
|
||||
},
|
||||
.gpio_grp = &gpio_grp_regs_p0,
|
||||
},
|
||||
{
|
||||
.chip = {
|
||||
.label = "gpio_p1",
|
||||
.direction_input = lpc32xx_gpio_dir_input_p012,
|
||||
.get = lpc32xx_gpio_get_value_p012,
|
||||
.direction_output = lpc32xx_gpio_dir_output_p012,
|
||||
.set = lpc32xx_gpio_set_value_p012,
|
||||
.request = lpc32xx_gpio_request,
|
||||
.base = LPC32XX_GPIO_P1_GRP,
|
||||
.ngpio = LPC32XX_GPIO_P1_MAX,
|
||||
.names = gpio_p1_names,
|
||||
.can_sleep = 0,
|
||||
},
|
||||
.gpio_grp = &gpio_grp_regs_p1,
|
||||
},
|
||||
{
|
||||
.chip = {
|
||||
.label = "gpio_p2",
|
||||
.direction_input = lpc32xx_gpio_dir_input_p012,
|
||||
.get = lpc32xx_gpio_get_value_p012,
|
||||
.direction_output = lpc32xx_gpio_dir_output_p012,
|
||||
.set = lpc32xx_gpio_set_value_p012,
|
||||
.request = lpc32xx_gpio_request,
|
||||
.base = LPC32XX_GPIO_P2_GRP,
|
||||
.ngpio = LPC32XX_GPIO_P2_MAX,
|
||||
.names = gpio_p2_names,
|
||||
.can_sleep = 0,
|
||||
},
|
||||
.gpio_grp = &gpio_grp_regs_p2,
|
||||
},
|
||||
{
|
||||
.chip = {
|
||||
.label = "gpio_p3",
|
||||
.direction_input = lpc32xx_gpio_dir_input_p3,
|
||||
.get = lpc32xx_gpio_get_value_p3,
|
||||
.direction_output = lpc32xx_gpio_dir_output_p3,
|
||||
.set = lpc32xx_gpio_set_value_p3,
|
||||
.request = lpc32xx_gpio_request,
|
||||
.base = LPC32XX_GPIO_P3_GRP,
|
||||
.ngpio = LPC32XX_GPIO_P3_MAX,
|
||||
.names = gpio_p3_names,
|
||||
.can_sleep = 0,
|
||||
},
|
||||
.gpio_grp = &gpio_grp_regs_p3,
|
||||
},
|
||||
{
|
||||
.chip = {
|
||||
.label = "gpi_p3",
|
||||
.direction_input = lpc32xx_gpio_dir_in_always,
|
||||
.get = lpc32xx_gpi_get_value,
|
||||
.request = lpc32xx_gpio_request,
|
||||
.base = LPC32XX_GPI_P3_GRP,
|
||||
.ngpio = LPC32XX_GPI_P3_MAX,
|
||||
.names = gpi_p3_names,
|
||||
.can_sleep = 0,
|
||||
},
|
||||
.gpio_grp = &gpio_grp_regs_p3,
|
||||
},
|
||||
{
|
||||
.chip = {
|
||||
.label = "gpo_p3",
|
||||
.direction_output = lpc32xx_gpio_dir_out_always,
|
||||
.set = lpc32xx_gpo_set_value,
|
||||
.request = lpc32xx_gpio_request,
|
||||
.base = LPC32XX_GPO_P3_GRP,
|
||||
.ngpio = LPC32XX_GPO_P3_MAX,
|
||||
.names = gpo_p3_names,
|
||||
.can_sleep = 0,
|
||||
},
|
||||
.gpio_grp = &gpio_grp_regs_p3,
|
||||
},
|
||||
};
|
||||
|
||||
void __init lpc32xx_gpio_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++)
|
||||
gpiochip_add(&lpc32xx_gpiochip[i].chip);
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user