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drm/amdgpu: add PSP driver for vega10 (v2)
PSP is responsible for firmware loading on SOC-15 asics. v2: fix memory leak (Ken) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Huang Rui
Alex Deucher
@@ -51,6 +51,11 @@ amdgpu-y += \
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cz_ih.o \
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vega10_ih.o
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# add PSP block
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amdgpu-y += \
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amdgpu_psp.o \
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psp_v3_1.o
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# add SMC block
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amdgpu-y += \
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amdgpu_dpm.o \
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@@ -52,6 +52,7 @@
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#include "amdgpu_irq.h"
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#include "amdgpu_ucode.h"
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#include "amdgpu_ttm.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_gds.h"
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#include "amdgpu_sync.h"
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#include "amdgpu_ring.h"
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@@ -1213,6 +1214,10 @@ struct amdgpu_firmware {
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struct amdgpu_bo *fw_buf;
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unsigned int fw_size;
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unsigned int max_ucodes;
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/* firmwares are loaded by psp instead of smu from vega10 */
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const struct amdgpu_psp_funcs *funcs;
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struct amdgpu_bo *rbuf;
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struct mutex mutex;
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};
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/*
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@@ -1571,6 +1576,9 @@ struct amdgpu_device {
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/* firmwares */
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struct amdgpu_firmware firmware;
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/* PSP */
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struct psp_context psp;
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/* GDS */
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struct amdgpu_gds gds;
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@@ -1825,6 +1833,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
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#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
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#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
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#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
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#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
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/* Common functions */
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int amdgpu_gpu_reset(struct amdgpu_device *adev);
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@@ -1837,6 +1837,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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* can recall function without having locking issues */
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mutex_init(&adev->vm_manager.lock);
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atomic_set(&adev->irq.ih.lock, 0);
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mutex_init(&adev->firmware.mutex);
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mutex_init(&adev->pm.mutex);
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mutex_init(&adev->gfx.gpu_clock_mutex);
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mutex_init(&adev->srbm_mutex);
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@@ -0,0 +1,481 @@
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Huang Rui
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*
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*/
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#include <linux/firmware.h>
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#include "drmP.h"
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#include "amdgpu.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_ucode.h"
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#include "soc15_common.h"
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#include "psp_v3_1.h"
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static void psp_set_funcs(struct amdgpu_device *adev);
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static int psp_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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psp_set_funcs(adev);
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return 0;
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}
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static int psp_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct psp_context *psp = &adev->psp;
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int ret;
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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psp->init_microcode = psp_v3_1_init_microcode;
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psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
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psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
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psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
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psp->ring_init = psp_v3_1_ring_init;
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psp->cmd_submit = psp_v3_1_cmd_submit;
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psp->compare_sram_data = psp_v3_1_compare_sram_data;
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psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
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break;
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default:
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return -EINVAL;
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}
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psp->adev = adev;
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ret = psp_init_microcode(psp);
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if (ret) {
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DRM_ERROR("Failed to load psp firmware!\n");
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return ret;
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}
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return 0;
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}
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static int psp_sw_fini(void *handle)
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{
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return 0;
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}
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int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
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uint32_t reg_val, uint32_t mask, bool check_changed)
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{
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uint32_t val;
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int i;
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struct amdgpu_device *adev = psp->adev;
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val = RREG32(reg_index);
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for (i = 0; i < adev->usec_timeout; i++) {
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if (check_changed) {
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if (val != reg_val)
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return 0;
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} else {
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if ((val & mask) == reg_val)
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return 0;
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}
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udelay(1);
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}
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return -ETIME;
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}
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static int
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psp_cmd_submit_buf(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
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int index)
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{
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int ret;
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struct amdgpu_bo *cmd_buf_bo;
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uint64_t cmd_buf_mc_addr;
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struct psp_gfx_cmd_resp *cmd_buf_mem;
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struct amdgpu_device *adev = psp->adev;
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ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&cmd_buf_bo, &cmd_buf_mc_addr,
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(void **)&cmd_buf_mem);
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if (ret)
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return ret;
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memset(cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
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memcpy(cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
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ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr,
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fence_mc_addr, index);
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while (*((unsigned int *)psp->fence_buf) != index) {
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msleep(1);
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};
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amdgpu_bo_free_kernel(&cmd_buf_bo,
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&cmd_buf_mc_addr,
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(void **)&cmd_buf_mem);
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return ret;
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}
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static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
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uint64_t tmr_mc, uint32_t size)
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{
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cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
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cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;
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cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32);
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cmd->cmd.cmd_setup_tmr.buf_size = size;
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}
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/* Set up Trusted Memory Region */
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static int psp_tmr_init(struct psp_context *psp)
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{
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int ret;
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struct psp_gfx_cmd_resp *cmd;
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cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
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if (!cmd)
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return -ENOMEM;
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/*
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* Allocate 3M memory aligned to 1M from Frame Buffer (local
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* physical).
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*
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* Note: this memory need be reserved till the driver
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* uninitializes.
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*/
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ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
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AMDGPU_GEM_DOMAIN_VRAM,
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&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
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if (ret)
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goto failed;
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psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
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ret = psp_cmd_submit_buf(psp, NULL, cmd,
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psp->fence_buf_mc_addr, 1);
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if (ret)
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goto failed_mem;
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kfree(cmd);
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return 0;
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failed_mem:
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amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
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failed:
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kfree(cmd);
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return ret;
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}
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static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
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uint64_t asd_mc, uint64_t asd_mc_shared,
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uint32_t size, uint32_t shared_size)
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{
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cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
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cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
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cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
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cmd->cmd.cmd_load_ta.app_len = size;
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cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
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cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
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cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
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}
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static int psp_asd_load(struct psp_context *psp)
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{
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int ret;
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struct amdgpu_bo *asd_bo, *asd_shared_bo;
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uint64_t asd_mc_addr, asd_shared_mc_addr;
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void *asd_buf, *asd_shared_buf;
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struct psp_gfx_cmd_resp *cmd;
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cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
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if (!cmd)
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return -ENOMEM;
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/*
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* Allocate 16k memory aligned to 4k from Frame Buffer (local
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* physical) for shared ASD <-> Driver
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*/
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ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&asd_shared_bo, &asd_shared_mc_addr, &asd_buf);
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if (ret)
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goto failed;
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/*
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* Allocate 256k memory aligned to 4k from Frame Buffer (local
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* physical) for ASD firmware
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*/
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ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_BIN_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&asd_bo, &asd_mc_addr, &asd_buf);
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if (ret)
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goto failed_mem;
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memcpy(asd_buf, psp->asd_start_addr, psp->asd_ucode_size);
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psp_prep_asd_cmd_buf(cmd, asd_mc_addr, asd_shared_mc_addr,
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psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
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ret = psp_cmd_submit_buf(psp, NULL, cmd,
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psp->fence_buf_mc_addr, 2);
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if (ret)
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goto failed_mem1;
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amdgpu_bo_free_kernel(&asd_bo, &asd_mc_addr, &asd_buf);
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amdgpu_bo_free_kernel(&asd_shared_bo, &asd_shared_mc_addr, &asd_shared_buf);
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kfree(cmd);
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return 0;
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failed_mem1:
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amdgpu_bo_free_kernel(&asd_bo, &asd_mc_addr, &asd_buf);
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failed_mem:
|
||||
amdgpu_bo_free_kernel(&asd_shared_bo, &asd_shared_mc_addr, &asd_shared_buf);
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failed:
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||||
kfree(cmd);
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return ret;
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}
|
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static int psp_load_fw(struct amdgpu_device *adev)
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{
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int ret;
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struct psp_gfx_cmd_resp *cmd;
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int i;
|
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struct amdgpu_firmware_info *ucode;
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struct psp_context *psp = &adev->psp;
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cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
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if (!cmd)
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return -ENOMEM;
|
||||
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ret = psp_bootloader_load_sysdrv(psp);
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if (ret)
|
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goto failed;
|
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ret = psp_bootloader_load_sos(psp);
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if (ret)
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goto failed;
|
||||
|
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ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
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if (ret)
|
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goto failed;
|
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|
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ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
|
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AMDGPU_GEM_DOMAIN_VRAM,
|
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&psp->fence_buf_bo,
|
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&psp->fence_buf_mc_addr,
|
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&psp->fence_buf);
|
||||
if (ret)
|
||||
goto failed;
|
||||
|
||||
memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
|
||||
|
||||
ret = psp_tmr_init(psp);
|
||||
if (ret)
|
||||
goto failed_mem;
|
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|
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ret = psp_asd_load(psp);
|
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if (ret)
|
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goto failed_mem;
|
||||
|
||||
for (i = 0; i < adev->firmware.max_ucodes; i++) {
|
||||
ucode = &adev->firmware.ucode[i];
|
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if (!ucode->fw)
|
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continue;
|
||||
|
||||
if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
|
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psp_smu_reload_quirk(psp))
|
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continue;
|
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|
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ret = psp_prep_cmd_buf(ucode, cmd);
|
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if (ret)
|
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goto failed_mem;
|
||||
|
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ret = psp_cmd_submit_buf(psp, ucode, cmd,
|
||||
psp->fence_buf_mc_addr, i + 3);
|
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if (ret)
|
||||
goto failed_mem;
|
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|
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#if 0
|
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/* check if firmware loaded sucessfully */
|
||||
if (!amdgpu_psp_check_fw_loading_status(adev, i))
|
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return -EINVAL;
|
||||
#endif
|
||||
}
|
||||
|
||||
amdgpu_bo_free_kernel(&psp->fence_buf_bo,
|
||||
&psp->fence_buf_mc_addr, &psp->fence_buf);
|
||||
kfree(cmd);
|
||||
|
||||
return 0;
|
||||
|
||||
failed_mem:
|
||||
amdgpu_bo_free_kernel(&psp->fence_buf_bo,
|
||||
&psp->fence_buf_mc_addr, &psp->fence_buf);
|
||||
failed:
|
||||
kfree(cmd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int psp_hw_init(void *handle)
|
||||
{
|
||||
int ret;
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
|
||||
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&adev->firmware.mutex);
|
||||
/*
|
||||
* This sequence is just used on hw_init only once, no need on
|
||||
* resume.
|
||||
*/
|
||||
ret = amdgpu_ucode_init_bo(adev);
|
||||
if (ret)
|
||||
goto failed;
|
||||
|
||||
ret = psp_load_fw(adev);
|
||||
if (ret) {
|
||||
DRM_ERROR("PSP firmware loading failed\n");
|
||||
goto failed;
|
||||
}
|
||||
|
||||
mutex_unlock(&adev->firmware.mutex);
|
||||
return 0;
|
||||
|
||||
failed:
|
||||
adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
|
||||
mutex_unlock(&adev->firmware.mutex);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int psp_hw_fini(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
struct psp_context *psp = &adev->psp;
|
||||
|
||||
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
|
||||
amdgpu_ucode_fini_bo(adev);
|
||||
|
||||
if (psp->tmr_buf)
|
||||
amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int psp_suspend(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int psp_resume(void *handle)
|
||||
{
|
||||
int ret;
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&adev->firmware.mutex);
|
||||
|
||||
ret = psp_load_fw(adev);
|
||||
if (ret)
|
||||
DRM_ERROR("PSP resume failed\n");
|
||||
|
||||
mutex_unlock(&adev->firmware.mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
|
||||
enum AMDGPU_UCODE_ID ucode_type)
|
||||
{
|
||||
struct amdgpu_firmware_info *ucode = NULL;
|
||||
|
||||
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
|
||||
DRM_INFO("firmware is not loaded by PSP\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
if (!adev->firmware.fw_size)
|
||||
return false;
|
||||
|
||||
ucode = &adev->firmware.ucode[ucode_type];
|
||||
if (!ucode->fw || !ucode->ucode_size)
|
||||
return false;
|
||||
|
||||
return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
|
||||
}
|
||||
|
||||
static int psp_set_clockgating_state(void *handle,
|
||||
enum amd_clockgating_state state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int psp_set_powergating_state(void *handle,
|
||||
enum amd_powergating_state state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct amd_ip_funcs psp_ip_funcs = {
|
||||
.name = "psp",
|
||||
.early_init = psp_early_init,
|
||||
.late_init = NULL,
|
||||
.sw_init = psp_sw_init,
|
||||
.sw_fini = psp_sw_fini,
|
||||
.hw_init = psp_hw_init,
|
||||
.hw_fini = psp_hw_fini,
|
||||
.suspend = psp_suspend,
|
||||
.resume = psp_resume,
|
||||
.is_idle = NULL,
|
||||
.wait_for_idle = NULL,
|
||||
.soft_reset = NULL,
|
||||
.set_clockgating_state = psp_set_clockgating_state,
|
||||
.set_powergating_state = psp_set_powergating_state,
|
||||
};
|
||||
|
||||
static const struct amdgpu_psp_funcs psp_funcs = {
|
||||
.check_fw_loading_status = psp_check_fw_loading_status,
|
||||
};
|
||||
|
||||
static void psp_set_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
if (NULL == adev->firmware.funcs)
|
||||
adev->firmware.funcs = &psp_funcs;
|
||||
}
|
||||
|
||||
const struct amdgpu_ip_block_version psp_v3_1_ip_block =
|
||||
{
|
||||
.type = AMD_IP_BLOCK_TYPE_PSP,
|
||||
.major = 3,
|
||||
.minor = 1,
|
||||
.rev = 0,
|
||||
.funcs = &psp_ip_funcs,
|
||||
};
|
||||
@@ -0,0 +1,127 @@
|
||||
/*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Author: Huang Rui
|
||||
*
|
||||
*/
|
||||
#ifndef __AMDGPU_PSP_H__
|
||||
#define __AMDGPU_PSP_H__
|
||||
|
||||
#include "amdgpu.h"
|
||||
#include "psp_gfx_if.h"
|
||||
|
||||
#define PSP_FENCE_BUFFER_SIZE 0x1000
|
||||
#define PSP_CMD_BUFFER_SIZE 0x1000
|
||||
#define PSP_ASD_BIN_SIZE 0x40000
|
||||
#define PSP_ASD_SHARED_MEM_SIZE 0x4000
|
||||
|
||||
enum psp_ring_type
|
||||
{
|
||||
PSP_RING_TYPE__INVALID = 0,
|
||||
/*
|
||||
* These values map to the way the PSP kernel identifies the
|
||||
* rings.
|
||||
*/
|
||||
PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
|
||||
PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
|
||||
};
|
||||
|
||||
struct psp_ring
|
||||
{
|
||||
enum psp_ring_type ring_type;
|
||||
struct psp_gfx_rb_frame *ring_mem;
|
||||
uint64_t ring_mem_mc_addr;
|
||||
void *ring_mem_handle;
|
||||
uint32_t ring_size;
|
||||
};
|
||||
|
||||
struct psp_context
|
||||
{
|
||||
struct amdgpu_device *adev;
|
||||
struct psp_ring km_ring;
|
||||
|
||||
int (*init_microcode)(struct psp_context *psp);
|
||||
int (*bootloader_load_sysdrv)(struct psp_context *psp);
|
||||
int (*bootloader_load_sos)(struct psp_context *psp);
|
||||
int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
|
||||
struct psp_gfx_cmd_resp *cmd);
|
||||
int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
|
||||
int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
|
||||
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index);
|
||||
bool (*compare_sram_data)(struct psp_context *psp,
|
||||
struct amdgpu_firmware_info *ucode,
|
||||
enum AMDGPU_UCODE_ID ucode_type);
|
||||
bool (*smu_reload_quirk)(struct psp_context *psp);
|
||||
|
||||
/* sos firmware */
|
||||
const struct firmware *sos_fw;
|
||||
uint32_t sos_fw_version;
|
||||
uint32_t sos_feature_version;
|
||||
uint32_t sys_bin_size;
|
||||
uint32_t sos_bin_size;
|
||||
uint8_t *sys_start_addr;
|
||||
uint8_t *sos_start_addr;
|
||||
|
||||
/* tmr buffer */
|
||||
struct amdgpu_bo *tmr_bo;
|
||||
uint64_t tmr_mc_addr;
|
||||
void *tmr_buf;
|
||||
|
||||
/* asd firmware */
|
||||
const struct firmware *asd_fw;
|
||||
uint32_t asd_fw_version;
|
||||
uint32_t asd_feature_version;
|
||||
uint32_t asd_ucode_size;
|
||||
uint8_t *asd_start_addr;
|
||||
|
||||
/* fence buffer */
|
||||
struct amdgpu_bo *fence_buf_bo;
|
||||
uint64_t fence_buf_mc_addr;
|
||||
void *fence_buf;
|
||||
};
|
||||
|
||||
struct amdgpu_psp_funcs {
|
||||
bool (*check_fw_loading_status)(struct amdgpu_device *adev,
|
||||
enum AMDGPU_UCODE_ID);
|
||||
};
|
||||
|
||||
#define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type))
|
||||
#define psp_ring_init(psp, type) (psp)->ring_init((psp), (type))
|
||||
#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
|
||||
(psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
|
||||
#define psp_compare_sram_data(psp, ucode, type) \
|
||||
(psp)->compare_sram_data((psp), (ucode), (type))
|
||||
#define psp_init_microcode(psp) \
|
||||
((psp)->init_microcode ? (psp)->init_microcode((psp)) : 0)
|
||||
#define psp_bootloader_load_sysdrv(psp) \
|
||||
((psp)->bootloader_load_sysdrv ? (psp)->bootloader_load_sysdrv((psp)) : 0)
|
||||
#define psp_bootloader_load_sos(psp) \
|
||||
((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0)
|
||||
#define psp_smu_reload_quirk(psp) \
|
||||
((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false)
|
||||
|
||||
extern const struct amd_ip_funcs psp_ip_funcs;
|
||||
|
||||
extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
|
||||
extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
|
||||
uint32_t field_val, uint32_t mask, bool check_changed);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,269 @@
|
||||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _PSP_TEE_GFX_IF_H_
|
||||
#define _PSP_TEE_GFX_IF_H_
|
||||
|
||||
#define PSP_GFX_CMD_BUF_VERSION 0x00000001
|
||||
|
||||
#define GFX_CMD_STATUS_MASK 0x0000FFFF
|
||||
#define GFX_CMD_ID_MASK 0x000F0000
|
||||
#define GFX_CMD_RESERVED_MASK 0x7FF00000
|
||||
#define GFX_CMD_RESPONSE_MASK 0x80000000
|
||||
|
||||
/* TEE Gfx Command IDs for the register interface.
|
||||
* Command ID must be between 0x00010000 and 0x000F0000.
|
||||
*/
|
||||
enum psp_gfx_crtl_cmd_id
|
||||
{
|
||||
GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */
|
||||
GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */
|
||||
GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */
|
||||
GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */
|
||||
|
||||
GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
|
||||
};
|
||||
|
||||
|
||||
/* Control registers of the TEE Gfx interface. These are located in
|
||||
* SRBM-to-PSP mailbox registers (total 8 registers).
|
||||
*/
|
||||
struct psp_gfx_ctrl
|
||||
{
|
||||
volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */
|
||||
volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */
|
||||
volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */
|
||||
volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */
|
||||
volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */
|
||||
volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of physical address of ring buffer */
|
||||
volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of physical address of ring buffer */
|
||||
volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* Response flag is set in the command when command is completed by PSP.
|
||||
* Used in the GFX_CTRL.CmdResp.
|
||||
* When PSP GFX I/F is initialized, the flag is set.
|
||||
*/
|
||||
#define GFX_FLAG_RESPONSE 0x80000000
|
||||
|
||||
|
||||
/* TEE Gfx Command IDs for the ring buffer interface. */
|
||||
enum psp_gfx_cmd_id
|
||||
{
|
||||
GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */
|
||||
GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */
|
||||
GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */
|
||||
GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */
|
||||
GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */
|
||||
GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* Command to load Trusted Application binary into PSP OS. */
|
||||
struct psp_gfx_cmd_load_ta
|
||||
{
|
||||
uint32_t app_phy_addr_lo; /* bits [31:0] of the physical address of the TA binary (must be 4 KB aligned) */
|
||||
uint32_t app_phy_addr_hi; /* bits [63:32] of the physical address of the TA binary */
|
||||
uint32_t app_len; /* length of the TA binary in bytes */
|
||||
uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the physical address of CMD buffer (must be 4 KB aligned) */
|
||||
uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the physical address of CMD buffer */
|
||||
uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */
|
||||
|
||||
/* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
|
||||
* for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead
|
||||
* of using global persistent buffer.
|
||||
*/
|
||||
};
|
||||
|
||||
|
||||
/* Command to Unload Trusted Application binary from PSP OS. */
|
||||
struct psp_gfx_cmd_unload_ta
|
||||
{
|
||||
uint32_t session_id; /* Session ID of the loaded TA to be unloaded */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* Shared buffers for InvokeCommand.
|
||||
*/
|
||||
struct psp_gfx_buf_desc
|
||||
{
|
||||
uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of the buffer (must be 4 KB aligned) */
|
||||
uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of the buffer */
|
||||
uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
|
||||
|
||||
};
|
||||
|
||||
/* Max number of descriptors for one shared buffer (in how many different
|
||||
* physical locations one shared buffer can be stored). If buffer is too much
|
||||
* fragmented, error will be returned.
|
||||
*/
|
||||
#define GFX_BUF_MAX_DESC 64
|
||||
|
||||
struct psp_gfx_buf_list
|
||||
{
|
||||
uint32_t num_desc; /* number of buffer descriptors in the list */
|
||||
uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
|
||||
struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */
|
||||
|
||||
/* total 776 bytes */
|
||||
};
|
||||
|
||||
/* Command to execute InvokeCommand entry point of the TA. */
|
||||
struct psp_gfx_cmd_invoke_cmd
|
||||
{
|
||||
uint32_t session_id; /* Session ID of the TA to be executed */
|
||||
uint32_t ta_cmd_id; /* Command ID to be sent to TA */
|
||||
struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* Command to setup TMR region. */
|
||||
struct psp_gfx_cmd_setup_tmr
|
||||
{
|
||||
uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of TMR buffer (must be 4 KB aligned) */
|
||||
uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of TMR buffer */
|
||||
uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
|
||||
enum psp_gfx_fw_type
|
||||
{
|
||||
GFX_FW_TYPE_NONE = 0,
|
||||
GFX_FW_TYPE_CP_ME = 1,
|
||||
GFX_FW_TYPE_CP_PFP = 2,
|
||||
GFX_FW_TYPE_CP_CE = 3,
|
||||
GFX_FW_TYPE_CP_MEC = 4,
|
||||
GFX_FW_TYPE_CP_MEC_ME1 = 5,
|
||||
GFX_FW_TYPE_CP_MEC_ME2 = 6,
|
||||
GFX_FW_TYPE_RLC_V = 7,
|
||||
GFX_FW_TYPE_RLC_G = 8,
|
||||
GFX_FW_TYPE_SDMA0 = 9,
|
||||
GFX_FW_TYPE_SDMA1 = 10,
|
||||
GFX_FW_TYPE_DMCU_ERAM = 11,
|
||||
GFX_FW_TYPE_DMCU_ISR = 12,
|
||||
GFX_FW_TYPE_VCN = 13,
|
||||
GFX_FW_TYPE_UVD = 14,
|
||||
GFX_FW_TYPE_VCE = 15,
|
||||
GFX_FW_TYPE_ISP = 16,
|
||||
GFX_FW_TYPE_ACP = 17,
|
||||
GFX_FW_TYPE_SMU = 18,
|
||||
};
|
||||
|
||||
/* Command to load HW IP FW. */
|
||||
struct psp_gfx_cmd_load_ip_fw
|
||||
{
|
||||
uint32_t fw_phy_addr_lo; /* bits [31:0] of physical address of FW location (must be 4 KB aligned) */
|
||||
uint32_t fw_phy_addr_hi; /* bits [63:32] of physical address of FW location */
|
||||
uint32_t fw_size; /* FW buffer size in bytes */
|
||||
enum psp_gfx_fw_type fw_type; /* FW type */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* All GFX ring buffer commands. */
|
||||
union psp_gfx_commands
|
||||
{
|
||||
struct psp_gfx_cmd_load_ta cmd_load_ta;
|
||||
struct psp_gfx_cmd_unload_ta cmd_unload_ta;
|
||||
struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd;
|
||||
struct psp_gfx_cmd_setup_tmr cmd_setup_tmr;
|
||||
struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw;
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* Structure of GFX Response buffer.
|
||||
* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
|
||||
* it is separate buffer.
|
||||
*/
|
||||
struct psp_gfx_resp
|
||||
{
|
||||
uint32_t status; /* +0 status of command execution */
|
||||
uint32_t session_id; /* +4 session ID in response to LoadTa command */
|
||||
uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
|
||||
uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
|
||||
|
||||
uint32_t reserved[4];
|
||||
|
||||
/* total 32 bytes */
|
||||
};
|
||||
|
||||
/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
|
||||
* and psp_gfx_rb_frame.cmd_buf_addr_lo.
|
||||
*/
|
||||
struct psp_gfx_cmd_resp
|
||||
{
|
||||
uint32_t buf_size; /* +0 total size of the buffer in bytes */
|
||||
uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */
|
||||
uint32_t cmd_id; /* +8 command ID */
|
||||
|
||||
/* These fields are used for RBI only. They are all 0 in GPCOM commands
|
||||
*/
|
||||
uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of physical address of response buffer (must be 4 KB aligned) */
|
||||
uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of physical address of response buffer */
|
||||
uint32_t resp_offset; /* +20 offset within response buffer */
|
||||
uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */
|
||||
|
||||
union psp_gfx_commands cmd; /* +28 command specific structures */
|
||||
|
||||
uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
|
||||
|
||||
/* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response
|
||||
* is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo.
|
||||
*/
|
||||
struct psp_gfx_resp resp; /* +864 response */
|
||||
|
||||
uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
|
||||
|
||||
/* total size 1024 bytes */
|
||||
};
|
||||
|
||||
|
||||
#define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/
|
||||
|
||||
/* Structure of the Ring Buffer Frame */
|
||||
struct psp_gfx_rb_frame
|
||||
{
|
||||
uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of physical address of command buffer (must be 4 KB aligned) */
|
||||
uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of physical address of command buffer */
|
||||
uint32_t cmd_buf_size; /* +8 command buffer size in bytes */
|
||||
uint32_t fence_addr_lo; /* +12 bits [31:0] of physical address of Fence for this frame */
|
||||
uint32_t fence_addr_hi; /* +16 bits [63:32] of physical address of Fence for this frame */
|
||||
uint32_t fence_value; /* +20 Fence value */
|
||||
uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */
|
||||
uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
|
||||
uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */
|
||||
uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
|
||||
uint8_t reserved1[2]; /* +34 reserved, must be 0 */
|
||||
uint32_t reserved2[7]; /* +40 reserved, must be 0 */
|
||||
/* total 64 bytes */
|
||||
};
|
||||
|
||||
#endif /* _PSP_TEE_GFX_IF_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Author: Huang Rui
|
||||
*
|
||||
*/
|
||||
#ifndef __PSP_V3_1_H__
|
||||
#define __PSP_V3_1_H__
|
||||
|
||||
#include "amdgpu_psp.h"
|
||||
|
||||
enum { PSP_DIRECTORY_TABLE_ENTRIES = 4 };
|
||||
enum { PSP_BINARY_ALIGNMENT = 64 };
|
||||
enum { PSP_BOOTLOADER_1_MEG_ALIGNMENT = 0x100000 };
|
||||
enum { PSP_BOOTLOADER_8_MEM_ALIGNMENT = 0x800000 };
|
||||
|
||||
extern int psp_v3_1_init_microcode(struct psp_context *psp);
|
||||
extern int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp);
|
||||
extern int psp_v3_1_bootloader_load_sos(struct psp_context *psp);
|
||||
extern int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
|
||||
struct psp_gfx_cmd_resp *cmd);
|
||||
extern int psp_v3_1_ring_init(struct psp_context *psp,
|
||||
enum psp_ring_type ring_type);
|
||||
extern int psp_v3_1_cmd_submit(struct psp_context *psp,
|
||||
struct amdgpu_firmware_info *ucode,
|
||||
uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
|
||||
int index);
|
||||
extern bool psp_v3_1_compare_sram_data(struct psp_context *psp,
|
||||
struct amdgpu_firmware_info *ucode,
|
||||
enum AMDGPU_UCODE_ID ucode_type);
|
||||
extern bool psp_v3_1_smu_reload_quirk(struct psp_context *psp);
|
||||
#endif
|
||||
@@ -68,6 +68,7 @@ enum amd_ip_block_type {
|
||||
AMD_IP_BLOCK_TYPE_GMC,
|
||||
AMD_IP_BLOCK_TYPE_IH,
|
||||
AMD_IP_BLOCK_TYPE_SMC,
|
||||
AMD_IP_BLOCK_TYPE_PSP,
|
||||
AMD_IP_BLOCK_TYPE_DCE,
|
||||
AMD_IP_BLOCK_TYPE_GFX,
|
||||
AMD_IP_BLOCK_TYPE_SDMA,
|
||||
|
||||
Reference in New Issue
Block a user