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[I/OAT]: Driver for the Intel(R) I/OAT DMA engine
Adds a new ioatdma driver Signed-off-by: Chris Leech <christopher.leech@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Chris Leech
committed by
David S. Miller
David S. Miller
parent
c13c8260da
commit
0bbd5f4e97
@@ -10,4 +10,13 @@ config DMA_ENGINE
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DMA engines offload copy operations from the CPU to dedicated
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hardware, allowing the copies to happen asynchronously.
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comment "DMA Devices"
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config INTEL_IOATDMA
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tristate "Intel I/OAT DMA support"
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depends on DMA_ENGINE && PCI
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default m
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---help---
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Enable support for the Intel(R) I/OAT DMA engine.
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endmenu
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@@ -1 +1,2 @@
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obj-y += dmaengine.o
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obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,126 @@
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/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef IOATDMA_H
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#define IOATDMA_H
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#include <linux/dmaengine.h>
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#include "ioatdma_hw.h"
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#include <linux/init.h>
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#include <linux/dmapool.h>
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#include <linux/cache.h>
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#define PCI_DEVICE_ID_INTEL_IOAT 0x1a38
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#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
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extern struct list_head dma_device_list;
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extern struct list_head dma_client_list;
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/**
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* struct ioat_device - internal representation of a IOAT device
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* @pdev: PCI-Express device
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* @reg_base: MMIO register space base address
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* @dma_pool: for allocating DMA descriptors
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* @common: embedded struct dma_device
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* @msi: Message Signaled Interrupt number
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*/
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struct ioat_device {
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struct pci_dev *pdev;
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void *reg_base;
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struct pci_pool *dma_pool;
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struct pci_pool *completion_pool;
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struct dma_device common;
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u8 msi;
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};
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/**
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* struct ioat_dma_chan - internal representation of a DMA channel
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* @device:
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* @reg_base:
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* @sw_in_use:
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* @completion:
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* @completion_low:
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* @completion_high:
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* @completed_cookie: last cookie seen completed on cleanup
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* @cookie: value of last cookie given to client
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* @last_completion:
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* @xfercap:
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* @desc_lock:
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* @free_desc:
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* @used_desc:
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* @resource:
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* @device_node:
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*/
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struct ioat_dma_chan {
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void *reg_base;
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dma_cookie_t completed_cookie;
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unsigned long last_completion;
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u32 xfercap; /* XFERCAP register value expanded out */
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spinlock_t cleanup_lock;
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spinlock_t desc_lock;
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struct list_head free_desc;
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struct list_head used_desc;
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int pending;
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struct ioat_device *device;
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struct dma_chan common;
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dma_addr_t completion_addr;
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union {
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u64 full; /* HW completion writeback */
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struct {
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u32 low;
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u32 high;
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};
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} *completion_virt;
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};
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/* wrapper around hardware descriptor format + additional software fields */
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/**
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* struct ioat_desc_sw - wrapper around hardware descriptor
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* @hw: hardware DMA descriptor
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* @node:
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* @cookie:
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* @phys:
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*/
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struct ioat_desc_sw {
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struct ioat_dma_descriptor *hw;
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struct list_head node;
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dma_cookie_t cookie;
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dma_addr_t phys;
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DECLARE_PCI_UNMAP_ADDR(src)
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DECLARE_PCI_UNMAP_LEN(src_len)
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DECLARE_PCI_UNMAP_ADDR(dst)
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DECLARE_PCI_UNMAP_LEN(dst_len)
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};
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#endif /* IOATDMA_H */
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@@ -0,0 +1,52 @@
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/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef _IOAT_HW_H_
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#define _IOAT_HW_H_
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/* PCI Configuration Space Values */
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#define IOAT_PCI_VID 0x8086
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#define IOAT_PCI_DID 0x1A38
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#define IOAT_PCI_RID 0x00
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#define IOAT_PCI_SVID 0x8086
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#define IOAT_PCI_SID 0x8086
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#define IOAT_VER 0x12 /* Version 1.2 */
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struct ioat_dma_descriptor {
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uint32_t size;
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uint32_t ctl;
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uint64_t src_addr;
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uint64_t dst_addr;
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uint64_t next;
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uint64_t rsv1;
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uint64_t rsv2;
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uint64_t user1;
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uint64_t user2;
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};
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#define IOAT_DMA_DESCRIPTOR_CTL_INT_GN 0x00000001
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#define IOAT_DMA_DESCRIPTOR_CTL_SRC_SN 0x00000002
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#define IOAT_DMA_DESCRIPTOR_CTL_DST_SN 0x00000004
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#define IOAT_DMA_DESCRIPTOR_CTL_CP_STS 0x00000008
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#define IOAT_DMA_DESCRIPTOR_CTL_FRAME 0x00000010
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#define IOAT_DMA_DESCRIPTOR_NUL 0x00000020
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#define IOAT_DMA_DESCRIPTOR_OPCODE 0xFF000000
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#endif
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@@ -0,0 +1,118 @@
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/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef IOATDMA_IO_H
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#define IOATDMA_IO_H
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#include <asm/io.h>
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/*
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* device and per-channel MMIO register read and write functions
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* this is a lot of anoying inline functions, but it's typesafe
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*/
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static inline u8 ioatdma_read8(struct ioat_device *device,
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unsigned int offset)
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{
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return readb(device->reg_base + offset);
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}
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static inline u16 ioatdma_read16(struct ioat_device *device,
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unsigned int offset)
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{
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return readw(device->reg_base + offset);
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}
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static inline u32 ioatdma_read32(struct ioat_device *device,
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unsigned int offset)
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{
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return readl(device->reg_base + offset);
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}
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static inline void ioatdma_write8(struct ioat_device *device,
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unsigned int offset, u8 value)
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{
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writeb(value, device->reg_base + offset);
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}
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static inline void ioatdma_write16(struct ioat_device *device,
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unsigned int offset, u16 value)
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{
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writew(value, device->reg_base + offset);
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}
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static inline void ioatdma_write32(struct ioat_device *device,
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unsigned int offset, u32 value)
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{
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writel(value, device->reg_base + offset);
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}
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static inline u8 ioatdma_chan_read8(struct ioat_dma_chan *chan,
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unsigned int offset)
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{
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return readb(chan->reg_base + offset);
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}
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static inline u16 ioatdma_chan_read16(struct ioat_dma_chan *chan,
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unsigned int offset)
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{
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return readw(chan->reg_base + offset);
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}
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static inline u32 ioatdma_chan_read32(struct ioat_dma_chan *chan,
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unsigned int offset)
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{
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return readl(chan->reg_base + offset);
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}
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static inline void ioatdma_chan_write8(struct ioat_dma_chan *chan,
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unsigned int offset, u8 value)
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{
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writeb(value, chan->reg_base + offset);
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}
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static inline void ioatdma_chan_write16(struct ioat_dma_chan *chan,
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unsigned int offset, u16 value)
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{
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writew(value, chan->reg_base + offset);
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}
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static inline void ioatdma_chan_write32(struct ioat_dma_chan *chan,
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unsigned int offset, u32 value)
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{
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writel(value, chan->reg_base + offset);
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}
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#if (BITS_PER_LONG == 64)
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static inline u64 ioatdma_chan_read64(struct ioat_dma_chan *chan,
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unsigned int offset)
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{
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return readq(chan->reg_base + offset);
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}
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static inline void ioatdma_chan_write64(struct ioat_dma_chan *chan,
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unsigned int offset, u64 value)
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{
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writeq(value, chan->reg_base + offset);
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}
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#endif
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#endif /* IOATDMA_IO_H */
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@@ -0,0 +1,126 @@
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/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef _IOAT_REGISTERS_H_
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#define _IOAT_REGISTERS_H_
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/* MMIO Device Registers */
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#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
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#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
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#define IOAT_XFERCAP_4KB 12
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#define IOAT_XFERCAP_8KB 13
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#define IOAT_XFERCAP_16KB 14
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#define IOAT_XFERCAP_32KB 15
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#define IOAT_XFERCAP_32GB 0
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#define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */
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#define IOAT_GENCTRL_DEBUG_EN 0x01
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#define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */
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#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */
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#define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */
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#define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */
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#define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
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#define IOAT_VER_OFFSET 0x08 /* 8-bit */
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#define IOAT_VER_MAJOR_MASK 0xF0
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#define IOAT_VER_MINOR_MASK 0x0F
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#define GET_IOAT_VER_MAJOR(x) ((x) & IOAT_VER_MAJOR_MASK)
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#define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK)
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#define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */
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#define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */
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#define IOAT_INTRDELAY_INT_DELAY_MASK 0x3FFF /* Interrupt Delay Time */
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#define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalesing Supported */
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#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
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#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001
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#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
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/* DMA Channel Registers */
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#define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */
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#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
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#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
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#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
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#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
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#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
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#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
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#define IOAT_CHANCTRL_INT_DISABLE 0x0001
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#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatability */
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#define IOAT_DMA_COMP_V1 0x0001 /* Compatability with DMA version 1 */
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#define IOAT_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */
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#define IOAT_CHANSTS_OFFSET_LOW 0x04
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#define IOAT_CHANSTS_OFFSET_HIGH 0x08
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#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR 0xFFFFFFFFFFFFFFC0
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#define IOAT_CHANSTS_SOFT_ERR 0x0000000000000010
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#define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x0000000000000007
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#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0
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#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE 0x1
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#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED 0x2
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#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED 0x3
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#define IOAT_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */
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#define IOAT_CHAINADDR_OFFSET_LOW 0x0C
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#define IOAT_CHAINADDR_OFFSET_HIGH 0x10
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#define IOAT_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */
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#define IOAT_CHANCMD_RESET 0x20
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#define IOAT_CHANCMD_RESUME 0x10
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#define IOAT_CHANCMD_ABORT 0x08
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#define IOAT_CHANCMD_SUSPEND 0x04
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#define IOAT_CHANCMD_APPEND 0x02
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#define IOAT_CHANCMD_START 0x01
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#define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */
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#define IOAT_CHANCMP_OFFSET_LOW 0x18
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#define IOAT_CHANCMP_OFFSET_HIGH 0x1C
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#define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */
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#define IOAT_CDAR_OFFSET_LOW 0x20
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#define IOAT_CDAR_OFFSET_HIGH 0x24
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#define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */
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#define IOAT_CHANERR_DMA_TRANSFER_SRC_ADDR_ERR 0x0001
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#define IOAT_CHANERR_DMA_TRANSFER_DEST_ADDR_ERR 0x0002
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#define IOAT_CHANERR_NEXT_DESCRIPTOR_ADDR_ERR 0x0004
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#define IOAT_CHANERR_NEXT_DESCRIPTOR_ALIGNMENT_ERR 0x0008
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#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010
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#define IOAT_CHANERR_CHANCMD_ERR 0x0020
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#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040
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#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080
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#define IOAT_CHANERR_READ_DATA_ERR 0x0100
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#define IOAT_CHANERR_WRITE_DATA_ERR 0x0200
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#define IOAT_CHANERR_DESCRIPTOR_CONTROL_ERR 0x0400
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#define IOAT_CHANERR_DESCRIPTOR_LENGTH_ERR 0x0800
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#define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000
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#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000
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#define IOAT_CHANERR_SOFT_ERR 0x4000
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#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
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#endif /* _IOAT_REGISTERS_H_ */
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