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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

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* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Rename PC speaker code
  [MIPS] Don't use genrtc.
  [MIPS] Remove unused time.c for swarm
  [MIPS] Sparse: Use NULL for pointer
  [MIPS] Fix a sparse warning in arch/mips/pci/pci.c
  [MIPS] SMTC: Interrupt mask backstop hack
  [MIPS] separate platform_device registration for VR41xx RTC
  [MIPS] Separate platform_device registration for VR41xx GPIO
  [MIPS] MIPSsim: Fix build.
  [MIPS] separate platform_device registration for VR41xx serial interface
  [MIPS] Include cacheflush.h in uncache.c
  [MIPS] Cleanup tlbdebug.h
  [MIPS] Change names of local variables to silence sparse (part 2)
  [MIPS] Workaround for a sparse warning in include/asm-mips/io.h
  [MIPS] RM: Use only phyiscal address for 82596 and 53c710
  [MIPS] Hydrogen3: Remove remaining bits of code.
  [MIPS] DEC: Fix modpost warning.
  Revert "[MIPS] DEC: Fix modpost warning."
  [MIPS] Fix resume for 64K page size on R4000 class processors.
This commit is contained in:
Linus Torvalds
2007-07-12 13:28:54 -07:00
parent 82afee684f de61b542b8
commit 0b9062f6b5
38 changed files with 570 additions and 700 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/mips/Kconfig
+17 -4
View File
@@ -117,9 +117,9 @@ config MACH_JAZZ
select ARC32
select ARCH_MAY_HAVE_PC_FDC
select GENERIC_ISA_DMA
select I8253
select I8259
select ISA
select PCSPEAKER
select SYS_HAS_CPU_R4X00
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
@@ -347,9 +347,9 @@ config QEMU
select DMA_COHERENT
select GENERIC_ISA_DMA
select HAVE_STD_PC_SERIAL_PORT
select I8253
select I8259
select ISA
select PCSPEAKER
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
@@ -562,9 +562,9 @@ config SNI_RM
select HW_HAS_EISA
select HW_HAS_PCI
select IRQ_CPU
select I8253
select I8259
select ISA
select PCSPEAKER
select SWAP_IO_SPACE if CPU_BIG_ENDIAN
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000
@@ -1404,6 +1404,19 @@ config MIPS_MT_SMTC_INSTANT_REPLAY
it off), but ensures that IPIs are handled promptly even under
heavy I/O interrupt load.
config MIPS_MT_SMTC_IM_BACKSTOP
bool "Use per-TC register bits as backstop for inhibited IM bits"
depends on MIPS_MT_SMTC
default y
help
To support multiple TC microthreads acting as "CPUs" within
a VPE, VPE-wide interrupt mask bits must be specially manipulated
during interrupt handling. To support legacy drivers and interrupt
controller management code, SMTC has a "backstop" to track and
if necessary restore the interrupt mask. This has some performance
impact on interrupt service overhead. Disable it only if you know
what you are doing.
config MIPS_VPE_LOADER_TOM
bool "Load VPE program into memory hidden from linux"
depends on MIPS_VPE_LOADER
@@ -1851,7 +1864,7 @@ config MMU
bool
default y
config I8253
config PCSPEAKER
bool
source "drivers/pcmcia/Kconfig"
arch/mips/au1000/common/setup.c
-3
View File
@@ -100,9 +100,6 @@ void __init plat_mem_setup(void)
argptr = prom_getcmdline();
/* default panel */
/*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
#ifdef CONFIG_MIPS_HYDROGEN3
strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor");
#endif
}
#endif
arch/mips/configs/jazz_defconfig
+1 -1
View File
@@ -241,7 +241,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
#
CONFIG_ISA=y
CONFIG_MMU=y
CONFIG_I8253=y
CONFIG_PCSPEAKER=y
#
# PCCARD (PCMCIA/CardBus) support
arch/mips/configs/qemu_defconfig
+1 -1
View File
@@ -221,7 +221,7 @@ CONFIG_DEFAULT_IOSCHED="noop"
#
CONFIG_ISA=y
CONFIG_MMU=y
CONFIG_I8253=y
CONFIG_PCSPEAKER=y
#
# PCCARD (PCMCIA/CardBus) support
arch/mips/configs/rm200_defconfig
+1 -1
View File
@@ -251,7 +251,7 @@ CONFIG_PCI=y
CONFIG_ISA=y
# CONFIG_EISA is not set
CONFIG_MMU=y
CONFIG_I8253=y
CONFIG_PCSPEAKER=y
#
# PCCARD (PCMCIA/CardBus) support
arch/mips/configs/yosemite_defconfig
-2
View File
@@ -592,8 +592,6 @@ CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_RTC is not set
CONFIG_GEN_RTC=y
CONFIG_GEN_RTC_X=y
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
arch/mips/kernel/Makefile
+1 -1
View File
@@ -63,7 +63,7 @@ obj-$(CONFIG_PROC_FS) += proc.o
obj-$(CONFIG_64BIT) += cpu-bugs64.o
obj-$(CONFIG_I8253) += i8253.o
obj-$(CONFIG_PCSPEAKER) += pcspeaker.o
obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
arch/mips/kernel/entry.S
+2
View File
@@ -84,6 +84,7 @@ FEXPORT(restore_all) # restore full frame
LONG_S sp, TI_REGS($28)
jal deferred_smtc_ipi
LONG_S s0, TI_REGS($28)
#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
/* Re-arm any temporarily masked interrupts not explicitly "acked" */
mfc0 v0, CP0_TCSTATUS
ori v1, v0, TCSTATUS_IXMT
@@ -110,6 +111,7 @@ FEXPORT(restore_all) # restore full frame
_ehb
xor t0, t0, t3
mtc0 t0, CP0_TCCONTEXT
#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
#endif /* CONFIG_MIPS_MT_SMTC */
.set noat
RESTORE_TEMP
arch/mips/kernel/genex.S
+2
View File
@@ -243,9 +243,11 @@ NESTED(except_vec_vi_handler, 0, sp)
*/
mfc0 t1, CP0_STATUS
and t0, a0, t1
#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
mfc0 t2, CP0_TCCONTEXT
or t0, t0, t2
mtc0 t0, CP0_TCCONTEXT
#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
xor t1, t1, t0
mtc0 t1, CP0_STATUS
_ehb
arch/mips/kernel/i8253.c → arch/mips/kernel/pcspeaker.c
View File
arch/mips/kernel/r4k_switch.S
+1 -6
View File
@@ -85,12 +85,7 @@
move $28, a2
cpu_restore_nonscratch a1
#if (_THREAD_SIZE - 32) < 0x10000
PTR_ADDIU t0, $28, _THREAD_SIZE - 32
#else
PTR_LI t0, _THREAD_SIZE - 32
PTR_ADDU t0, $28
#endif
PTR_ADDU t0, $28, _THREAD_SIZE - 32
set_saved_sp t0, t1, t2
#ifdef CONFIG_MIPS_MT_SMTC
/* Read-modify-writes of Status must be atomic on a VPE */
arch/mips/kernel/traps.c
+1 -1
View File
@@ -373,7 +373,7 @@ asmlinkage void do_be(struct pt_regs *regs)
action = MIPS_BE_FIXUP;
if (board_be_handler)
action = board_be_handler(regs, fixup != 0);
action = board_be_handler(regs, fixup != NULL);
switch (action) {
case MIPS_BE_DISCARD:
arch/mips/lib/dump_tlb.c
+1
View File
@@ -10,6 +10,7 @@
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/tlbdebug.h>
static inline const char *msk2str(unsigned int mask)
{
arch/mips/lib/r3k_dump_tlb.c
+1
View File
@@ -11,6 +11,7 @@
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/tlbdebug.h>
extern int r3k_have_wired_reg; /* defined in tlb-r3k.c */
arch/mips/lib/uncached.c
+1
View File
@@ -12,6 +12,7 @@
#include <asm/addrspace.h>
#include <asm/bug.h>
#include <asm/cacheflush.h>
#ifndef CKSEG2
#define CKSEG2 CKSSEG
arch/mips/mipssim/sim_int.c
+1 -1
View File
@@ -77,7 +77,7 @@ asmlinkage void plat_irq_dispatch(void)
irq = irq_ffs(pending);
if (irq > 0)
do_IRQ(MIPSCPU_INT_BASE + irq);
do_IRQ(MIPS_CPU_IRQ_BASE + irq);
else
spurious_interrupt();
}
arch/mips/mipssim/sim_setup.c
+1 -1
View File
@@ -84,7 +84,7 @@ static void __init serial_init(void)
/* hardware int 4 - the serial int, is CPU int 6
but poll for now */
s.irq = 0;
s.uartclk = BASE_BAUD * 16;
s.uartclk = 1843200;
s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
s.iotype = UPIO_PORT;
s.regshift = 0;
arch/mips/mipssim/sim_time.c
-1
View File
@@ -5,7 +5,6 @@
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/mipsregs.h>
#include <linux/smp.h>
#include <linux/timex.h>
arch/mips/pci/pci.c
+1 -1
View File
@@ -269,7 +269,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
}
for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
struct pci_dev *dev = pci_dev_b(ln);
dev = pci_dev_b(ln);
if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
pcibios_fixup_device_resources(dev, bus);
arch/mips/sibyte/swarm/time.c
-244
View File
@@ -1,244 +0,0 @@
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Time routines for the swarm board. We pass all the hard stuff
* through to the sb1250 handling code. Only thing we really keep
* track of here is what time of day we think it is. And we don't
* really even do a good job of that...
*/
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/time.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <asm/system.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_smbus.h>
static unsigned long long sec_bias = 0;
static unsigned int usec_bias = 0;
/* Xicor 1241 definitions */
/*
* Register bits
*/
#define X1241REG_SR_BAT 0x80 /* currently on battery power */
#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */
#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */
#define X1241REG_SR_RTCF 0x01 /* clock failed */
#define X1241REG_BL_BP2 0x80 /* block protect 2 */
#define X1241REG_BL_BP1 0x40 /* block protect 1 */
#define X1241REG_BL_BP0 0x20 /* block protect 0 */
#define X1241REG_BL_WD1 0x10
#define X1241REG_BL_WD0 0x08
#define X1241REG_HR_MIL 0x80 /* military time format */
/*
* Register numbers
*/
#define X1241REG_BL 0x10 /* block protect bits */
#define X1241REG_INT 0x11 /* */
#define X1241REG_SC 0x30 /* Seconds */
#define X1241REG_MN 0x31 /* Minutes */
#define X1241REG_HR 0x32 /* Hours */
#define X1241REG_DT 0x33 /* Day of month */
#define X1241REG_MO 0x34 /* Month */
#define X1241REG_YR 0x35 /* Year */
#define X1241REG_DW 0x36 /* Day of Week */
#define X1241REG_Y2K 0x37 /* Year 2K */
#define X1241REG_SR 0x3F /* Status register */
#define X1241_CCR_ADDRESS 0x6F
#define SMB_CSR(reg) (IOADDR(A_SMB_REGISTER(1, reg)))
static int xicor_read(uint8_t addr)
{
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
__raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
__raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
__raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
SMB_CSR(R_SMB_START));
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
__raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
SMB_CSR(R_SMB_START));
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
/* Clear error bit by writing a 1 */
__raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
return -1;
}
return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
}
static int xicor_write(uint8_t addr, int b)
{
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
__raw_writeq(addr, SMB_CSR(R_SMB_CMD));
__raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
__raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
SMB_CSR(R_SMB_START));
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
/* Clear error bit by writing a 1 */
__raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
return -1;
} else {
return 0;
}
}
/*
* In order to set the CMOS clock precisely, set_rtc_mmss has to be
* called 500 ms after the second nowtime has started, because when
* nowtime is written into the registers of the CMOS clock, it will
* jump to the next second precisely 500 ms later. Check the Motorola
* MC146818A or Dallas DS12887 data sheet for details.
*
* BUG: This routine does not handle hour overflow properly; it just
* sets the minutes. Usually you'll only notice that after reboot!
*/
int set_rtc_mmss(unsigned long nowtime)
{
int retval = 0;
int real_seconds, real_minutes, cmos_minutes;
cmos_minutes = xicor_read(X1241REG_MN);
cmos_minutes = BCD2BIN(cmos_minutes);
/*
* since we're only adjusting minutes and seconds,
* don't interfere with hour overflow. This avoids
* messing with unknown time zones but requires your
* RTC not to be off by more than 15 minutes
*/
real_seconds = nowtime % 60;
real_minutes = nowtime / 60;
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
real_minutes += 30; /* correct for half hour time zone */
real_minutes %= 60;
/* unlock writes to the CCR */
xicor_write(X1241REG_SR, X1241REG_SR_WEL);
xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL);
if (abs(real_minutes - cmos_minutes) < 30) {
real_seconds = BIN2BCD(real_seconds);
real_minutes = BIN2BCD(real_minutes);
xicor_write(X1241REG_SC, real_seconds);
xicor_write(X1241REG_MN, real_minutes);
} else {
printk(KERN_WARNING
"set_rtc_mmss: can't update from %d to %d\n",
cmos_minutes, real_minutes);
retval = -1;
}
xicor_write(X1241REG_SR, 0);
printk("set_rtc_mmss: %02d:%02d\n", real_minutes, real_seconds);
return retval;
}
static unsigned long __init get_swarm_time(void)
{
unsigned int year, mon, day, hour, min, sec, y2k;
sec = xicor_read(X1241REG_SC);
min = xicor_read(X1241REG_MN);
hour = xicor_read(X1241REG_HR);
if (hour & X1241REG_HR_MIL) {
hour &= 0x3f;
} else {
if (hour & 0x20)
hour = (hour & 0xf) + 0x12;
}
sec = BCD2BIN(sec);
min = BCD2BIN(min);
hour = BCD2BIN(hour);
day = xicor_read(X1241REG_DT);
mon = xicor_read(X1241REG_MO);
year = xicor_read(X1241REG_YR);
y2k = xicor_read(X1241REG_Y2K);
day = BCD2BIN(day);
mon = BCD2BIN(mon);
year = BCD2BIN(year);
y2k = BCD2BIN(y2k);
year += (y2k * 100);
return mktime(year, mon, day, hour, min, sec);
}
/*
* Bring up the timer at 100 Hz.
*/
void __init swarm_time_init(void)
{
unsigned int flags;
int status;
/* Set up the scd general purpose timer 0 to cpu 0 */
sb1250_time_init();
/* Establish communication with the Xicor 1241 RTC */
/* XXXKW how do I share the SMBus with the I2C subsystem? */
__raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
__raw_writeq(0, SMB_CSR(R_SMB_CONTROL));
if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) {
printk("x1241: couldn't detect on SWARM SMBus 1\n");
} else {
if (status & X1241REG_SR_RTCF)
printk("x1241: battery failed -- time is probably wrong\n");
write_seqlock_irqsave(&xtime_lock, flags);
xtime.tv_sec = get_swarm_time();
xtime.tv_nsec = 0;
write_sequnlock_irqrestore(&xtime_lock, flags);
}
}

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