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Merge branch 'for-linus' into for-next
Back merge HD-audio quirks to for-next branch, so that we can apply a couple of more quirks. Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Takashi Iwai
+11
-3
@@ -1186,7 +1186,7 @@ M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-mvebu/
|
||||
F: drivers/rtc/armada38x-rtc
|
||||
F: drivers/rtc/rtc-armada38x.c
|
||||
|
||||
ARM/Marvell Berlin SoC support
|
||||
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
||||
@@ -1362,6 +1362,7 @@ F: drivers/i2c/busses/i2c-rk3x.c
|
||||
F: drivers/*/*rockchip*
|
||||
F: drivers/*/*/*rockchip*
|
||||
F: sound/soc/rockchip/
|
||||
N: rockchip
|
||||
|
||||
ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
|
||||
M: Kukjin Kim <kgene@kernel.org>
|
||||
@@ -1675,8 +1676,8 @@ F: drivers/misc/eeprom/at24.c
|
||||
F: include/linux/platform_data/at24.h
|
||||
|
||||
ATA OVER ETHERNET (AOE) DRIVER
|
||||
M: "Ed L. Cashin" <ecashin@coraid.com>
|
||||
W: http://support.coraid.com/support/linux
|
||||
M: "Ed L. Cashin" <ed.cashin@acm.org>
|
||||
W: http://www.openaoe.org/
|
||||
S: Supported
|
||||
F: Documentation/aoe/
|
||||
F: drivers/block/aoe/
|
||||
@@ -3252,6 +3253,13 @@ S: Maintained
|
||||
F: Documentation/hwmon/dme1737
|
||||
F: drivers/hwmon/dme1737.c
|
||||
|
||||
DMI/SMBIOS SUPPORT
|
||||
M: Jean Delvare <jdelvare@suse.de>
|
||||
S: Maintained
|
||||
F: drivers/firmware/dmi-id.c
|
||||
F: drivers/firmware/dmi_scan.c
|
||||
F: include/linux/dmi.h
|
||||
|
||||
DOCKING STATION DRIVER
|
||||
M: Shaohua Li <shaohua.li@intel.com>
|
||||
L: linux-acpi@vger.kernel.org
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
VERSION = 4
|
||||
PATCHLEVEL = 0
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc5
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Hurr durr I'ma sheep
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
||||
@@ -67,7 +67,7 @@ stash_usr_regs(struct rt_sigframe __user *sf, struct pt_regs *regs,
|
||||
sigset_t *set)
|
||||
{
|
||||
int err;
|
||||
err = __copy_to_user(&(sf->uc.uc_mcontext.regs), regs,
|
||||
err = __copy_to_user(&(sf->uc.uc_mcontext.regs.scratch), regs,
|
||||
sizeof(sf->uc.uc_mcontext.regs.scratch));
|
||||
err |= __copy_to_user(&sf->uc.uc_sigmask, set, sizeof(sigset_t));
|
||||
|
||||
@@ -83,7 +83,7 @@ static int restore_usr_regs(struct pt_regs *regs, struct rt_sigframe __user *sf)
|
||||
if (!err)
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||||
set_current_blocked(&set);
|
||||
|
||||
err |= __copy_from_user(regs, &(sf->uc.uc_mcontext.regs),
|
||||
err |= __copy_from_user(regs, &(sf->uc.uc_mcontext.regs.scratch),
|
||||
sizeof(sf->uc.uc_mcontext.regs.scratch));
|
||||
|
||||
return err;
|
||||
@@ -131,6 +131,15 @@ SYSCALL_DEFINE0(rt_sigreturn)
|
||||
/* Don't restart from sigreturn */
|
||||
syscall_wont_restart(regs);
|
||||
|
||||
/*
|
||||
* Ensure that sigreturn always returns to user mode (in case the
|
||||
* regs saved on user stack got fudged between save and sigreturn)
|
||||
* Otherwise it is easy to panic the kernel with a custom
|
||||
* signal handler and/or restorer which clobberes the status32/ret
|
||||
* to return to a bogus location in kernel mode.
|
||||
*/
|
||||
regs->status32 |= STATUS_U_MASK;
|
||||
|
||||
return regs->r0;
|
||||
|
||||
badframe:
|
||||
@@ -229,8 +238,11 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
|
||||
|
||||
/*
|
||||
* handler returns using sigreturn stub provided already by userpsace
|
||||
* If not, nuke the process right away
|
||||
*/
|
||||
BUG_ON(!(ksig->ka.sa.sa_flags & SA_RESTORER));
|
||||
if(!(ksig->ka.sa.sa_flags & SA_RESTORER))
|
||||
return 1;
|
||||
|
||||
regs->blink = (unsigned long)ksig->ka.sa.sa_restorer;
|
||||
|
||||
/* User Stack for signal handler will be above the frame just carved */
|
||||
@@ -296,12 +308,12 @@ static void
|
||||
handle_signal(struct ksignal *ksig, struct pt_regs *regs)
|
||||
{
|
||||
sigset_t *oldset = sigmask_to_save();
|
||||
int ret;
|
||||
int failed;
|
||||
|
||||
/* Set up the stack frame */
|
||||
ret = setup_rt_frame(ksig, oldset, regs);
|
||||
failed = setup_rt_frame(ksig, oldset, regs);
|
||||
|
||||
signal_setup_done(ret, ksig, 0);
|
||||
signal_setup_done(failed, ksig, 0);
|
||||
}
|
||||
|
||||
void do_signal(struct pt_regs *regs)
|
||||
|
||||
@@ -619,6 +619,7 @@ config ARCH_PXA
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GPIO_PXA
|
||||
select HAVE_IDE
|
||||
select IRQ_DOMAIN
|
||||
select MULTI_IRQ_HANDLER
|
||||
select PLAT_PXA
|
||||
select SPARSE_IRQ
|
||||
|
||||
@@ -36,6 +36,20 @@
|
||||
>;
|
||||
};
|
||||
|
||||
mmc_pins: pinmux_mmc_pins {
|
||||
pinctrl-single,pins = <
|
||||
DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */
|
||||
DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */
|
||||
DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */
|
||||
DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */
|
||||
DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */
|
||||
DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */
|
||||
DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */
|
||||
DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */
|
||||
DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */
|
||||
>;
|
||||
};
|
||||
|
||||
usb0_pins: pinmux_usb0_pins {
|
||||
pinctrl-single,pins = <
|
||||
DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */
|
||||
@@ -137,7 +151,12 @@
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc_pins>;
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* At least dm8168-evm rev c won't support multipoint, later may */
|
||||
|
||||
@@ -150,17 +150,27 @@
|
||||
};
|
||||
|
||||
gpio1: gpio@48032000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio1";
|
||||
ti,gpio-always-on;
|
||||
reg = <0x48032000 0x1000>;
|
||||
interrupts = <97>;
|
||||
interrupts = <96>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@4804c000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio2";
|
||||
ti,gpio-always-on;
|
||||
reg = <0x4804c000 0x1000>;
|
||||
interrupts = <99>;
|
||||
interrupts = <98>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
|
||||
@@ -1111,7 +1111,6 @@
|
||||
"wkupclk", "refclk",
|
||||
"div-clk", "phy-div";
|
||||
#phy-cells = <0>;
|
||||
ti,hwmods = "pcie1-phy";
|
||||
};
|
||||
|
||||
pcie2_phy: pciephy@4a095000 {
|
||||
@@ -1130,7 +1129,6 @@
|
||||
"wkupclk", "refclk",
|
||||
"div-clk", "phy-div";
|
||||
#phy-cells = <0>;
|
||||
ti,hwmods = "pcie2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -92,6 +92,8 @@
|
||||
ti,hwmods = "aes";
|
||||
reg = <0x480c5000 0x50>;
|
||||
interrupts = <0>;
|
||||
dmas = <&sdma 65 &sdma 66>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
prm: prm@48306000 {
|
||||
@@ -550,6 +552,8 @@
|
||||
ti,hwmods = "sham";
|
||||
reg = <0x480c3000 0x64>;
|
||||
interrupts = <49>;
|
||||
dmas = <&sdma 69>;
|
||||
dma-names = "rx";
|
||||
};
|
||||
|
||||
smartreflex_core: smartreflex@480cb000 {
|
||||
|
||||
@@ -411,6 +411,7 @@
|
||||
"mac_clk_rx", "mac_clk_tx",
|
||||
"clk_mac_ref", "clk_mac_refout",
|
||||
"aclk_mac", "pclk_mac";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@ff500000 {
|
||||
|
||||
@@ -660,7 +660,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xfff01000 0x1000>;
|
||||
interrupts = <0 156 4>;
|
||||
interrupts = <0 155 4>;
|
||||
num-cs = <4>;
|
||||
clocks = <&spi_m_clk>;
|
||||
status = "disabled";
|
||||
|
||||
@@ -56,6 +56,22 @@
|
||||
model = "Olimex A10-OLinuXino-LIME";
|
||||
compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10";
|
||||
|
||||
cpus {
|
||||
cpu0: cpu@0 {
|
||||
/*
|
||||
* The A10-Lime is known to be unstable
|
||||
* when running at 1008 MHz
|
||||
*/
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
912000 1350000
|
||||
864000 1300000
|
||||
624000 1250000
|
||||
>;
|
||||
cooling-max-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
emac: ethernet@01c0b000 {
|
||||
pinctrl-names = "default";
|
||||
|
||||
@@ -75,7 +75,6 @@
|
||||
clock-latency = <244144>; /* 8 32k periods */
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1056000 1500000
|
||||
1008000 1400000
|
||||
912000 1350000
|
||||
864000 1300000
|
||||
@@ -83,7 +82,7 @@
|
||||
>;
|
||||
#cooling-cells = <2>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <4>;
|
||||
cooling-max-level = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -47,7 +47,6 @@
|
||||
clock-latency = <244144>; /* 8 32k periods */
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1104000 1500000
|
||||
1008000 1400000
|
||||
912000 1350000
|
||||
864000 1300000
|
||||
@@ -57,7 +56,7 @@
|
||||
>;
|
||||
#cooling-cells = <2>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <6>;
|
||||
cooling-max-level = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -105,7 +105,6 @@
|
||||
clock-latency = <244144>; /* 8 32k periods */
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1008000 1450000
|
||||
960000 1400000
|
||||
912000 1400000
|
||||
864000 1300000
|
||||
@@ -116,7 +115,7 @@
|
||||
>;
|
||||
#cooling-cells = <2>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <7>;
|
||||
cooling-max-level = <6>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
|
||||
@@ -720,6 +720,8 @@ static const char * __init omap_get_family(void)
|
||||
return kasprintf(GFP_KERNEL, "OMAP4");
|
||||
else if (soc_is_omap54xx())
|
||||
return kasprintf(GFP_KERNEL, "OMAP5");
|
||||
else if (soc_is_am33xx() || soc_is_am335x())
|
||||
return kasprintf(GFP_KERNEL, "AM33xx");
|
||||
else if (soc_is_am43xx())
|
||||
return kasprintf(GFP_KERNEL, "AM43xx");
|
||||
else if (soc_is_dra7xx())
|
||||
|
||||
+48
-63
@@ -11,6 +11,7 @@
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
@@ -40,7 +41,6 @@
|
||||
#define ICHP_VAL_IRQ (1 << 31)
|
||||
#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
|
||||
#define IPR_VALID (1 << 31)
|
||||
#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
|
||||
|
||||
#define MAX_INTERNAL_IRQS 128
|
||||
|
||||
@@ -51,6 +51,7 @@
|
||||
static void __iomem *pxa_irq_base;
|
||||
static int pxa_internal_irq_nr;
|
||||
static bool cpu_has_ipr;
|
||||
static struct irq_domain *pxa_irq_domain;
|
||||
|
||||
static inline void __iomem *irq_base(int i)
|
||||
{
|
||||
@@ -66,18 +67,20 @@ static inline void __iomem *irq_base(int i)
|
||||
void pxa_mask_irq(struct irq_data *d)
|
||||
{
|
||||
void __iomem *base = irq_data_get_irq_chip_data(d);
|
||||
irq_hw_number_t irq = irqd_to_hwirq(d);
|
||||
uint32_t icmr = __raw_readl(base + ICMR);
|
||||
|
||||
icmr &= ~(1 << IRQ_BIT(d->irq));
|
||||
icmr &= ~BIT(irq & 0x1f);
|
||||
__raw_writel(icmr, base + ICMR);
|
||||
}
|
||||
|
||||
void pxa_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
void __iomem *base = irq_data_get_irq_chip_data(d);
|
||||
irq_hw_number_t irq = irqd_to_hwirq(d);
|
||||
uint32_t icmr = __raw_readl(base + ICMR);
|
||||
|
||||
icmr |= 1 << IRQ_BIT(d->irq);
|
||||
icmr |= BIT(irq & 0x1f);
|
||||
__raw_writel(icmr, base + ICMR);
|
||||
}
|
||||
|
||||
@@ -118,40 +121,63 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
|
||||
} while (1);
|
||||
}
|
||||
|
||||
void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
|
||||
static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
int irq, i, n;
|
||||
void __iomem *base = irq_base(hw / 32);
|
||||
|
||||
BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
|
||||
/* initialize interrupt priority */
|
||||
if (cpu_has_ipr)
|
||||
__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
|
||||
|
||||
irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_data(virq, base);
|
||||
set_irq_flags(virq, IRQF_VALID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops pxa_irq_ops = {
|
||||
.map = pxa_irq_map,
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
};
|
||||
|
||||
static __init void
|
||||
pxa_init_irq_common(struct device_node *node, int irq_nr,
|
||||
int (*fn)(struct irq_data *, unsigned int))
|
||||
{
|
||||
int n;
|
||||
|
||||
pxa_internal_irq_nr = irq_nr;
|
||||
cpu_has_ipr = !cpu_is_pxa25x();
|
||||
pxa_irq_base = io_p2v(0x40d00000);
|
||||
pxa_irq_domain = irq_domain_add_legacy(node, irq_nr,
|
||||
PXA_IRQ(0), 0,
|
||||
&pxa_irq_ops, NULL);
|
||||
if (!pxa_irq_domain)
|
||||
panic("Unable to add PXA IRQ domain\n");
|
||||
irq_set_default_host(pxa_irq_domain);
|
||||
|
||||
for (n = 0; n < irq_nr; n += 32) {
|
||||
void __iomem *base = irq_base(n >> 5);
|
||||
|
||||
__raw_writel(0, base + ICMR); /* disable all IRQs */
|
||||
__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
|
||||
for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
|
||||
/* initialize interrupt priority */
|
||||
if (cpu_has_ipr)
|
||||
__raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
|
||||
|
||||
irq = PXA_IRQ(i);
|
||||
irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_data(irq, base);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
}
|
||||
|
||||
/* only unmasked interrupts kick us out of idle */
|
||||
__raw_writel(1, irq_base(0) + ICCR);
|
||||
|
||||
pxa_internal_irq_chip.irq_set_wake = fn;
|
||||
}
|
||||
|
||||
void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
|
||||
{
|
||||
BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
|
||||
|
||||
pxa_irq_base = io_p2v(0x40d00000);
|
||||
cpu_has_ipr = !cpu_is_pxa25x();
|
||||
pxa_init_irq_common(NULL, irq_nr, fn);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
|
||||
static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
|
||||
@@ -203,30 +229,6 @@ struct syscore_ops pxa_irq_syscore_ops = {
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static struct irq_domain *pxa_irq_domain;
|
||||
|
||||
static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
void __iomem *base = irq_base(hw / 32);
|
||||
|
||||
/* initialize interrupt priority */
|
||||
if (cpu_has_ipr)
|
||||
__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
|
||||
|
||||
irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_data(hw, base);
|
||||
set_irq_flags(hw, IRQF_VALID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops pxa_irq_ops = {
|
||||
.map = pxa_irq_map,
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
};
|
||||
|
||||
static const struct of_device_id intc_ids[] __initconst = {
|
||||
{ .compatible = "marvell,pxa-intc", },
|
||||
{}
|
||||
@@ -236,7 +238,7 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
|
||||
{
|
||||
struct device_node *node;
|
||||
struct resource res;
|
||||
int n, ret;
|
||||
int ret;
|
||||
|
||||
node = of_find_matching_node(NULL, intc_ids);
|
||||
if (!node) {
|
||||
@@ -267,23 +269,6 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
|
||||
return;
|
||||
}
|
||||
|
||||
pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
|
||||
&pxa_irq_ops, NULL);
|
||||
if (!pxa_irq_domain)
|
||||
panic("Unable to add PXA IRQ domain\n");
|
||||
|
||||
irq_set_default_host(pxa_irq_domain);
|
||||
|
||||
for (n = 0; n < pxa_internal_irq_nr; n += 32) {
|
||||
void __iomem *base = irq_base(n >> 5);
|
||||
|
||||
__raw_writel(0, base + ICMR); /* disable all IRQs */
|
||||
__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
|
||||
}
|
||||
|
||||
/* only unmasked interrupts kick us out of idle */
|
||||
__raw_writel(1, irq_base(0) + ICCR);
|
||||
|
||||
pxa_internal_irq_chip.irq_set_wake = fn;
|
||||
pxa_init_irq_common(node, pxa_internal_irq_nr, fn);
|
||||
}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
@@ -412,7 +412,7 @@ static struct fixed_voltage_config can_regulator_pdata = {
|
||||
};
|
||||
|
||||
static struct platform_device can_regulator_device = {
|
||||
.name = "reg-fixed-volage",
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &can_regulator_pdata,
|
||||
|
||||
@@ -1,10 +1,12 @@
|
||||
menuconfig ARCH_SUNXI
|
||||
bool "Allwinner SoCs" if ARCH_MULTI_V7
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_IRQ_CHIP
|
||||
select PINCTRL
|
||||
select SUN4I_TIMER
|
||||
select RESET_CONTROLLER
|
||||
|
||||
if ARCH_SUNXI
|
||||
|
||||
@@ -20,10 +22,8 @@ config MACH_SUN5I
|
||||
config MACH_SUN6I
|
||||
bool "Allwinner A31 (sun6i) SoCs support"
|
||||
default ARCH_SUNXI
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select ARM_GIC
|
||||
select MFD_SUN6I_PRCM
|
||||
select RESET_CONTROLLER
|
||||
select SUN5I_HSTIMER
|
||||
|
||||
config MACH_SUN7I
|
||||
@@ -37,16 +37,12 @@ config MACH_SUN7I
|
||||
config MACH_SUN8I
|
||||
bool "Allwinner A23 (sun8i) SoCs support"
|
||||
default ARCH_SUNXI
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select ARM_GIC
|
||||
select MFD_SUN6I_PRCM
|
||||
select RESET_CONTROLLER
|
||||
|
||||
config MACH_SUN9I
|
||||
bool "Allwinner (sun9i) SoCs support"
|
||||
default ARCH_SUNXI
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select ARM_GIC
|
||||
select RESET_CONTROLLER
|
||||
|
||||
endif
|
||||
|
||||
@@ -799,6 +799,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
|
||||
struct device *dev = &pdev->dev;
|
||||
const struct of_device_id *match;
|
||||
const struct dmtimer_platform_data *pdata;
|
||||
int ret;
|
||||
|
||||
match = of_match_device(of_match_ptr(omap_timer_match), dev);
|
||||
pdata = match ? match->data : dev->platform_data;
|
||||
@@ -860,7 +861,12 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
if (!timer->reserved) {
|
||||
pm_runtime_get_sync(dev);
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
|
||||
__func__);
|
||||
goto err_get_sync;
|
||||
}
|
||||
__omap_dm_timer_init_regs(timer);
|
||||
pm_runtime_put(dev);
|
||||
}
|
||||
@@ -873,6 +879,11 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
|
||||
dev_dbg(dev, "Device Probed.\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_get_sync:
|
||||
pm_runtime_put_noidle(dev);
|
||||
pm_runtime_disable(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -899,6 +910,8 @@ static int omap_dm_timer_remove(struct platform_device *pdev)
|
||||
}
|
||||
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@@ -8,7 +8,7 @@
|
||||
*/
|
||||
|
||||
/* SoC fixed clocks */
|
||||
soc_uartclk: refclk72738khz {
|
||||
soc_uartclk: refclk7273800hz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <7273800>;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user