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Merge branch 'akpm' (Andrew's patch-bomb)
Merge misc patches from Andrew Morton: - the "misc" tree - stuff from all over the map - checkpatch updates - fatfs - kmod changes - procfs - cpumask - UML - kexec - mqueue - rapidio - pidns - some checkpoint-restore feature work. Reluctantly. Most of it delayed a release. I'm still rather worried that we don't have a clear roadmap to completion for this work. * emailed from Andrew Morton <akpm@linux-foundation.org>: (78 patches) kconfig: update compression algorithm info c/r: prctl: add ability to set new mm_struct::exe_file c/r: prctl: extend PR_SET_MM to set up more mm_struct entries c/r: procfs: add arg_start/end, env_start/end and exit_code members to /proc/$pid/stat syscalls, x86: add __NR_kcmp syscall fs, proc: introduce /proc/<pid>/task/<tid>/children entry sysctl: make kernel.ns_last_pid control dependent on CHECKPOINT_RESTORE aio/vfs: cleanup of rw_copy_check_uvector() and compat_rw_copy_check_uvector() eventfd: change int to __u64 in eventfd_signal() fs/nls: add Apple NLS pidns: make killed children autoreap pidns: use task_active_pid_ns in do_notify_parent rapidio/tsi721: add DMA engine support rapidio: add DMA engine support for RIO data transfers ipc/mqueue: add rbtree node caching support tools/selftests: add mq_perf_tests ipc/mqueue: strengthen checks on mqueue creation ipc/mqueue: correct mq_attr_ok test ipc/mqueue: improve performance of send/recv selftests: add mq_open_tests ...
This commit is contained in:
Linus Torvalds
@@ -113,3 +113,5 @@ Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
|
||||
Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
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Takashi YOSHII <takashi.yoshii.zj@renesas.com>
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Yusuke Goda <goda.yusuke@renesas.com>
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Gustavo Padovan <gustavo@las.ic.unicamp.br>
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Gustavo Padovan <padovan@profusion.mobi>
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@@ -671,8 +671,9 @@ ones already enabled by DEBUG.
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Chapter 14: Allocating memory
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The kernel provides the following general purpose memory allocators:
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kmalloc(), kzalloc(), kcalloc(), vmalloc(), and vzalloc(). Please refer to
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the API documentation for further information about them.
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kmalloc(), kzalloc(), kmalloc_array(), kcalloc(), vmalloc(), and
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vzalloc(). Please refer to the API documentation for further information
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about them.
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The preferred form for passing a size of a struct is the following:
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@@ -686,6 +687,17 @@ Casting the return value which is a void pointer is redundant. The conversion
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from void pointer to any other pointer type is guaranteed by the C programming
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language.
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The preferred form for allocating an array is the following:
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p = kmalloc_array(n, sizeof(...), ...);
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The preferred form for allocating a zeroed array is the following:
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p = kcalloc(n, sizeof(...), ...);
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Both forms check for overflow on the allocation size n * sizeof(...),
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and return NULL if that occurred.
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Chapter 15: The inline disease
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@@ -40,6 +40,7 @@ Table of Contents
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3.4 /proc/<pid>/coredump_filter - Core dump filtering settings
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3.5 /proc/<pid>/mountinfo - Information about mounts
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3.6 /proc/<pid>/comm & /proc/<pid>/task/<tid>/comm
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3.7 /proc/<pid>/task/<tid>/children - Information about task children
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4 Configuring procfs
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4.1 Mount options
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@@ -310,6 +311,11 @@ Table 1-4: Contents of the stat files (as of 2.6.30-rc7)
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start_data address above which program data+bss is placed
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end_data address below which program data+bss is placed
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start_brk address above which program heap can be expanded with brk()
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arg_start address above which program command line is placed
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arg_end address below which program command line is placed
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env_start address above which program environment is placed
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env_end address below which program environment is placed
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exit_code the thread's exit_code in the form reported by the waitpid system call
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..............................................................................
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The /proc/PID/maps file containing the currently mapped memory regions and
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@@ -1578,6 +1584,23 @@ then the kernel's TASK_COMM_LEN (currently 16 chars) will result in a truncated
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comm value.
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3.7 /proc/<pid>/task/<tid>/children - Information about task children
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-------------------------------------------------------------------------
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This file provides a fast way to retrieve first level children pids
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of a task pointed by <pid>/<tid> pair. The format is a space separated
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stream of pids.
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Note the "first level" here -- if a child has own children they will
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not be listed here, one needs to read /proc/<children-pid>/task/<tid>/children
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to obtain the descendants.
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Since this interface is intended to be fast and cheap it doesn't
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guarantee to provide precise results and some children might be
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skipped, especially if they've exited right after we printed their
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pids, so one need to either stop or freeze processes being inspected
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if precise results are needed.
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------------------------------------------------------------------------------
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Configuring procfs
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------------------------------------------------------------------------------
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@@ -225,6 +225,13 @@ a queue must be less or equal then msg_max.
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maximum message size value (it is every message queue's attribute set during
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its creation).
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/proc/sys/fs/mqueue/msg_default is a read/write file for setting/getting the
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default number of messages in a queue value if attr parameter of mq_open(2) is
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NULL. If it exceed msg_max, the default value is initialized msg_max.
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/proc/sys/fs/mqueue/msgsize_default is a read/write file for setting/getting
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the default message size value if attr parameter of mq_open(2) is NULL. If it
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exceed msgsize_max, the default value is initialized msgsize_max.
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|
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4. /proc/sys/fs/epoll - Configuration options for the epoll interface
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--------------------------------------------------------
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@@ -16,7 +16,7 @@ There are three components to pagemap:
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* Bits 0-4 swap type if swapped
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* Bits 5-54 swap offset if swapped
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* Bits 55-60 page shift (page size = 1<<page shift)
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* Bit 61 reserved for future use
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* Bit 61 page is file-page or shared-anon
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* Bit 62 page swapped
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* Bit 63 page present
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|
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@@ -109,7 +109,6 @@ static void percpu_timer_stop(void);
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int __cpu_disable(void)
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{
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unsigned int cpu = smp_processor_id();
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struct task_struct *p;
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int ret;
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|
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ret = platform_cpu_disable(cpu);
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@@ -139,12 +138,7 @@ int __cpu_disable(void)
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flush_cache_all();
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local_flush_tlb_all();
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read_lock(&tasklist_lock);
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for_each_process(p) {
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if (p->mm)
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cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
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}
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read_unlock(&tasklist_lock);
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clear_tasks_mm_cpumask(cpu);
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return 0;
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}
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@@ -10,6 +10,8 @@
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#include <linux/hardirq.h>
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#include <linux/thread_info.h>
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#include <linux/mm.h>
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#include <linux/oom.h>
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#include <linux/sched.h>
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#include <linux/uaccess.h>
|
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#include <linux/module.h>
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#include <linux/kallsyms.h>
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@@ -27,8 +29,7 @@ void decode_address(char *buf, unsigned long address)
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{
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struct task_struct *p;
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struct mm_struct *mm;
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unsigned long flags, offset;
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unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
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unsigned long offset;
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struct rb_node *n;
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#ifdef CONFIG_KALLSYMS
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@@ -112,17 +113,17 @@ void decode_address(char *buf, unsigned long address)
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* mappings of all our processes and see if we can't be a whee
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* bit more specific
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*/
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write_lock_irqsave(&tasklist_lock, flags);
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||||
read_lock(&tasklist_lock);
|
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for_each_process(p) {
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||||
mm = (in_atomic ? p->mm : get_task_mm(p));
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if (!mm)
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||||
struct task_struct *t;
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||||
|
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t = find_lock_task_mm(p);
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if (!t)
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continue;
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if (!down_read_trylock(&mm->mmap_sem)) {
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if (!in_atomic)
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mmput(mm);
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continue;
|
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}
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mm = t->mm;
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if (!down_read_trylock(&mm->mmap_sem))
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goto __continue;
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for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
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struct vm_area_struct *vma;
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@@ -131,7 +132,7 @@ void decode_address(char *buf, unsigned long address)
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if (address >= vma->vm_start && address < vma->vm_end) {
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char _tmpbuf[256];
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char *name = p->comm;
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char *name = t->comm;
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struct file *file = vma->vm_file;
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if (file) {
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@@ -164,8 +165,7 @@ void decode_address(char *buf, unsigned long address)
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name, vma->vm_start, vma->vm_end);
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up_read(&mm->mmap_sem);
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if (!in_atomic)
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mmput(mm);
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task_unlock(t);
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if (buf[0] == '\0')
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sprintf(buf, "[ %s ] dynamic memory", name);
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@@ -175,8 +175,8 @@ void decode_address(char *buf, unsigned long address)
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}
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up_read(&mm->mmap_sem);
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if (!in_atomic)
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mmput(mm);
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__continue:
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task_unlock(t);
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}
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/*
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@@ -186,7 +186,7 @@ void decode_address(char *buf, unsigned long address)
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sprintf(buf, "/* kernel dynamic memory */");
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done:
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write_unlock_irqrestore(&tasklist_lock, flags);
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read_unlock(&tasklist_lock);
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}
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#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
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@@ -333,9 +333,7 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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||||
unsigned int cpu = (unsigned int)(long)hcpu;
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#ifdef CONFIG_HOTPLUG_CPU
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struct task_struct *p;
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#endif
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/* We don't touch CPU 0 map, it's allocated at aboot and kept
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* around forever
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*/
|
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@@ -358,12 +356,7 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
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stale_map[cpu] = NULL;
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/* We also clear the cpu_vm_mask bits of CPUs going away */
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read_lock(&tasklist_lock);
|
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for_each_process(p) {
|
||||
if (p->mm)
|
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cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
|
||||
}
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read_unlock(&tasklist_lock);
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clear_tasks_mm_cpumask(cpu);
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||||
break;
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#endif /* CONFIG_HOTPLUG_CPU */
|
||||
}
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||||
|
||||
@@ -123,7 +123,6 @@ void native_play_dead(void)
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int __cpu_disable(void)
|
||||
{
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||||
unsigned int cpu = smp_processor_id();
|
||||
struct task_struct *p;
|
||||
int ret;
|
||||
|
||||
ret = mp_ops->cpu_disable(cpu);
|
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@@ -153,11 +152,7 @@ int __cpu_disable(void)
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flush_cache_all();
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||||
local_flush_tlb_all();
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||||
|
||||
read_lock(&tasklist_lock);
|
||||
for_each_process(p)
|
||||
if (p->mm)
|
||||
cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
|
||||
read_unlock(&tasklist_lock);
|
||||
clear_tasks_mm_cpumask(cpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
+10
-3
@@ -4,7 +4,9 @@
|
||||
*/
|
||||
|
||||
#include "linux/sched.h"
|
||||
#include "linux/spinlock.h"
|
||||
#include "linux/slab.h"
|
||||
#include "linux/oom.h"
|
||||
#include "kern_util.h"
|
||||
#include "os.h"
|
||||
#include "skas.h"
|
||||
@@ -22,13 +24,18 @@ static void kill_off_processes(void)
|
||||
struct task_struct *p;
|
||||
int pid;
|
||||
|
||||
read_lock(&tasklist_lock);
|
||||
for_each_process(p) {
|
||||
if (p->mm == NULL)
|
||||
continue;
|
||||
struct task_struct *t;
|
||||
|
||||
pid = p->mm->context.id.u.pid;
|
||||
t = find_lock_task_mm(p);
|
||||
if (!t)
|
||||
continue;
|
||||
pid = t->mm->context.id.u.pid;
|
||||
task_unlock(t);
|
||||
os_kill_ptraced_process(pid, 1);
|
||||
}
|
||||
read_unlock(&tasklist_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
+19
-5
@@ -30,6 +30,8 @@ int handle_page_fault(unsigned long address, unsigned long ip,
|
||||
pmd_t *pmd;
|
||||
pte_t *pte;
|
||||
int err = -EFAULT;
|
||||
unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
|
||||
(is_write ? FAULT_FLAG_WRITE : 0);
|
||||
|
||||
*code_out = SEGV_MAPERR;
|
||||
|
||||
@@ -40,6 +42,7 @@ int handle_page_fault(unsigned long address, unsigned long ip,
|
||||
if (in_atomic())
|
||||
goto out_nosemaphore;
|
||||
|
||||
retry:
|
||||
down_read(&mm->mmap_sem);
|
||||
vma = find_vma(mm, address);
|
||||
if (!vma)
|
||||
@@ -65,7 +68,11 @@ good_area:
|
||||
do {
|
||||
int fault;
|
||||
|
||||
fault = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0);
|
||||
fault = handle_mm_fault(mm, vma, address, flags);
|
||||
|
||||
if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
|
||||
goto out_nosemaphore;
|
||||
|
||||
if (unlikely(fault & VM_FAULT_ERROR)) {
|
||||
if (fault & VM_FAULT_OOM) {
|
||||
goto out_of_memory;
|
||||
@@ -75,10 +82,17 @@ good_area:
|
||||
}
|
||||
BUG();
|
||||
}
|
||||
if (fault & VM_FAULT_MAJOR)
|
||||
current->maj_flt++;
|
||||
else
|
||||
current->min_flt++;
|
||||
if (flags & FAULT_FLAG_ALLOW_RETRY) {
|
||||
if (fault & VM_FAULT_MAJOR)
|
||||
current->maj_flt++;
|
||||
else
|
||||
current->min_flt++;
|
||||
if (fault & VM_FAULT_RETRY) {
|
||||
flags &= ~FAULT_FLAG_ALLOW_RETRY;
|
||||
|
||||
goto retry;
|
||||
}
|
||||
}
|
||||
|
||||
pgd = pgd_offset(mm, address);
|
||||
pud = pud_offset(pgd, address);
|
||||
|
||||
@@ -355,3 +355,4 @@
|
||||
346 i386 setns sys_setns
|
||||
347 i386 process_vm_readv sys_process_vm_readv compat_sys_process_vm_readv
|
||||
348 i386 process_vm_writev sys_process_vm_writev compat_sys_process_vm_writev
|
||||
349 i386 kcmp sys_kcmp
|
||||
|
||||
@@ -318,6 +318,8 @@
|
||||
309 common getcpu sys_getcpu
|
||||
310 64 process_vm_readv sys_process_vm_readv
|
||||
311 64 process_vm_writev sys_process_vm_writev
|
||||
312 64 kcmp sys_kcmp
|
||||
|
||||
#
|
||||
# x32-specific system call numbers start at 512 to avoid cache impact
|
||||
# for native 64-bit operation.
|
||||
|
||||
@@ -1653,7 +1653,6 @@ mpt_mapresources(MPT_ADAPTER *ioc)
|
||||
unsigned long port;
|
||||
u32 msize;
|
||||
u32 psize;
|
||||
u8 revision;
|
||||
int r = -ENODEV;
|
||||
struct pci_dev *pdev;
|
||||
|
||||
@@ -1670,8 +1669,6 @@ mpt_mapresources(MPT_ADAPTER *ioc)
|
||||
return r;
|
||||
}
|
||||
|
||||
pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
|
||||
|
||||
if (sizeof(dma_addr_t) > 4) {
|
||||
const uint64_t required_mask = dma_get_required_mask
|
||||
(&pdev->dev);
|
||||
@@ -1779,7 +1776,6 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
MPT_ADAPTER *ioc;
|
||||
u8 cb_idx;
|
||||
int r = -ENODEV;
|
||||
u8 revision;
|
||||
u8 pcixcmd;
|
||||
static int mpt_ids = 0;
|
||||
#ifdef CONFIG_PROC_FS
|
||||
@@ -1887,8 +1883,8 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n",
|
||||
ioc->name, &ioc->facts, &ioc->pfacts[0]));
|
||||
|
||||
pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
|
||||
mpt_get_product_name(pdev->vendor, pdev->device, revision, ioc->prod_name);
|
||||
mpt_get_product_name(pdev->vendor, pdev->device, pdev->revision,
|
||||
ioc->prod_name);
|
||||
|
||||
switch (pdev->device)
|
||||
{
|
||||
@@ -1903,7 +1899,7 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
break;
|
||||
|
||||
case MPI_MANUFACTPAGE_DEVICEID_FC929X:
|
||||
if (revision < XL_929) {
|
||||
if (pdev->revision < XL_929) {
|
||||
/* 929X Chip Fix. Set Split transactions level
|
||||
* for PCIX. Set MOST bits to zero.
|
||||
*/
|
||||
@@ -1934,7 +1930,7 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
/* 1030 Chip Fix. Disable Split transactions
|
||||
* for PCIX. Set MOST bits to zero if Rev < C0( = 8).
|
||||
*/
|
||||
if (revision < C0_1030) {
|
||||
if (pdev->revision < C0_1030) {
|
||||
pci_read_config_byte(pdev, 0x6a, &pcixcmd);
|
||||
pcixcmd &= 0x8F;
|
||||
pci_write_config_byte(pdev, 0x6a, pcixcmd);
|
||||
|
||||
@@ -1250,7 +1250,6 @@ mptctl_getiocinfo (unsigned long arg, unsigned int data_size)
|
||||
int iocnum;
|
||||
unsigned int port;
|
||||
int cim_rev;
|
||||
u8 revision;
|
||||
struct scsi_device *sdev;
|
||||
VirtDevice *vdevice;
|
||||
|
||||
@@ -1324,8 +1323,7 @@ mptctl_getiocinfo (unsigned long arg, unsigned int data_size)
|
||||
pdev = (struct pci_dev *) ioc->pcidev;
|
||||
|
||||
karg->pciId = pdev->device;
|
||||
pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
|
||||
karg->hwRev = revision;
|
||||
karg->hwRev = pdev->revision;
|
||||
karg->subSystemDevice = pdev->subsystem_device;
|
||||
karg->subSystemVendor = pdev->subsystem_vendor;
|
||||
|
||||
|
||||
@@ -22,6 +22,20 @@ config RAPIDIO_ENABLE_RX_TX_PORTS
|
||||
ports for Input/Output direction to allow other traffic
|
||||
than Maintenance transfers.
|
||||
|
||||
config RAPIDIO_DMA_ENGINE
|
||||
bool "DMA Engine support for RapidIO"
|
||||
depends on RAPIDIO
|
||||
select DMADEVICES
|
||||
select DMA_ENGINE
|
||||
help
|
||||
Say Y here if you want to use DMA Engine frameork for RapidIO data
|
||||
transfers to/from target RIO devices. RapidIO uses NREAD and
|
||||
NWRITE (NWRITE_R, SWRITE) requests to transfer data between local
|
||||
memory and memory on remote target device. You need a DMA controller
|
||||
capable to perform data transfers to/from RapidIO.
|
||||
|
||||
If you are unsure about this, say Y here.
|
||||
|
||||
config RAPIDIO_DEBUG
|
||||
bool "RapidIO subsystem debug messages"
|
||||
depends on RAPIDIO
|
||||
|
||||
@@ -3,3 +3,6 @@
|
||||
#
|
||||
|
||||
obj-$(CONFIG_RAPIDIO_TSI721) += tsi721.o
|
||||
ifeq ($(CONFIG_RAPIDIO_DMA_ENGINE),y)
|
||||
obj-$(CONFIG_RAPIDIO_TSI721) += tsi721_dma.o
|
||||
endif
|
||||
|
||||
@@ -108,6 +108,7 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
|
||||
u16 destid, u8 hopcount, u32 offset, int len,
|
||||
u32 *data, int do_wr)
|
||||
{
|
||||
void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id);
|
||||
struct tsi721_dma_desc *bd_ptr;
|
||||
u32 rd_count, swr_ptr, ch_stat;
|
||||
int i, err = 0;
|
||||
@@ -116,10 +117,9 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
|
||||
if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32)))
|
||||
return -EINVAL;
|
||||
|
||||
bd_ptr = priv->bdma[TSI721_DMACH_MAINT].bd_base;
|
||||
bd_ptr = priv->mdma.bd_base;
|
||||
|
||||
rd_count = ioread32(
|
||||
priv->regs + TSI721_DMAC_DRDCNT(TSI721_DMACH_MAINT));
|
||||
rd_count = ioread32(regs + TSI721_DMAC_DRDCNT);
|
||||
|
||||
/* Initialize DMA descriptor */
|
||||
bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid);
|
||||
@@ -134,19 +134,18 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
|
||||
mb();
|
||||
|
||||
/* Start DMA operation */
|
||||
iowrite32(rd_count + 2,
|
||||
priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
|
||||
ioread32(priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
|
||||
iowrite32(rd_count + 2, regs + TSI721_DMAC_DWRCNT);
|
||||
ioread32(regs + TSI721_DMAC_DWRCNT);
|
||||
i = 0;
|
||||
|
||||
/* Wait until DMA transfer is finished */
|
||||
while ((ch_stat = ioread32(priv->regs +
|
||||
TSI721_DMAC_STS(TSI721_DMACH_MAINT))) & TSI721_DMAC_STS_RUN) {
|
||||
while ((ch_stat = ioread32(regs + TSI721_DMAC_STS))
|
||||
& TSI721_DMAC_STS_RUN) {
|
||||
udelay(1);
|
||||
if (++i >= 5000000) {
|
||||
dev_dbg(&priv->pdev->dev,
|
||||
"%s : DMA[%d] read timeout ch_status=%x\n",
|
||||
__func__, TSI721_DMACH_MAINT, ch_stat);
|
||||
__func__, priv->mdma.ch_id, ch_stat);
|
||||
if (!do_wr)
|
||||
*data = 0xffffffff;
|
||||
err = -EIO;
|
||||
@@ -162,13 +161,10 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
|
||||
__func__, ch_stat);
|
||||
dev_dbg(&priv->pdev->dev, "OP=%d : destid=%x hc=%x off=%x\n",
|
||||
do_wr ? MAINT_WR : MAINT_RD, destid, hopcount, offset);
|
||||
iowrite32(TSI721_DMAC_INT_ALL,
|
||||
priv->regs + TSI721_DMAC_INT(TSI721_DMACH_MAINT));
|
||||
iowrite32(TSI721_DMAC_CTL_INIT,
|
||||
priv->regs + TSI721_DMAC_CTL(TSI721_DMACH_MAINT));
|
||||
iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
|
||||
iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
|
||||
udelay(10);
|
||||
iowrite32(0, priv->regs +
|
||||
TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
|
||||
iowrite32(0, regs + TSI721_DMAC_DWRCNT);
|
||||
udelay(1);
|
||||
if (!do_wr)
|
||||
*data = 0xffffffff;
|
||||
@@ -184,8 +180,8 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
|
||||
* NOTE: Skipping check and clear FIFO entries because we are waiting
|
||||
* for transfer to be completed.
|
||||
*/
|
||||
swr_ptr = ioread32(priv->regs + TSI721_DMAC_DSWP(TSI721_DMACH_MAINT));
|
||||
iowrite32(swr_ptr, priv->regs + TSI721_DMAC_DSRP(TSI721_DMACH_MAINT));
|
||||
swr_ptr = ioread32(regs + TSI721_DMAC_DSWP);
|
||||
iowrite32(swr_ptr, regs + TSI721_DMAC_DSRP);
|
||||
err_out:
|
||||
|
||||
return err;
|
||||
@@ -541,6 +537,22 @@ static irqreturn_t tsi721_irqhandler(int irq, void *ptr)
|
||||
tsi721_pw_handler(mport);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
if (dev_int & TSI721_DEV_INT_BDMA_CH) {
|
||||
int ch;
|
||||
|
||||
if (dev_ch_int & TSI721_INT_BDMA_CHAN_M) {
|
||||
dev_dbg(&priv->pdev->dev,
|
||||
"IRQ from DMA channel 0x%08x\n", dev_ch_int);
|
||||
|
||||
for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) {
|
||||
if (!(dev_ch_int & TSI721_INT_BDMA_CHAN(ch)))
|
||||
continue;
|
||||
tsi721_bdma_handler(&priv->bdma[ch]);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
@@ -553,18 +565,26 @@ static void tsi721_interrupts_init(struct tsi721_device *priv)
|
||||
priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
|
||||
iowrite32(TSI721_SR_CHINT_IDBQRCV,
|
||||
priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
|
||||
iowrite32(TSI721_INT_SR2PC_CHAN(IDB_QUEUE),
|
||||
priv->regs + TSI721_DEV_CHAN_INTE);
|
||||
|
||||
/* Enable SRIO MAC interrupts */
|
||||
iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT,
|
||||
priv->regs + TSI721_RIO_EM_DEV_INT_EN);
|
||||
|
||||
/* Enable interrupts from channels in use */
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE) |
|
||||
(TSI721_INT_BDMA_CHAN_M &
|
||||
~TSI721_INT_BDMA_CHAN(TSI721_DMACH_MAINT));
|
||||
#else
|
||||
intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE);
|
||||
#endif
|
||||
iowrite32(intr, priv->regs + TSI721_DEV_CHAN_INTE);
|
||||
|
||||
if (priv->flags & TSI721_USING_MSIX)
|
||||
intr = TSI721_DEV_INT_SRIO;
|
||||
else
|
||||
intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
|
||||
TSI721_DEV_INT_SMSG_CH;
|
||||
TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH;
|
||||
|
||||
iowrite32(intr, priv->regs + TSI721_DEV_INTE);
|
||||
ioread32(priv->regs + TSI721_DEV_INTE);
|
||||
@@ -715,12 +735,29 @@ static int tsi721_enable_msix(struct tsi721_device *priv)
|
||||
TSI721_MSIX_OMSG_INT(i);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
/*
|
||||
* Initialize MSI-X entries for Block DMA Engine:
|
||||
* this driver supports XXX DMA channels
|
||||
* (one is reserved for SRIO maintenance transactions)
|
||||
*/
|
||||
for (i = 0; i < TSI721_DMA_CHNUM; i++) {
|
||||
entries[TSI721_VECT_DMA0_DONE + i].entry =
|
||||
TSI721_MSIX_DMACH_DONE(i);
|
||||
entries[TSI721_VECT_DMA0_INT + i].entry =
|
||||
TSI721_MSIX_DMACH_INT(i);
|
||||
}
|
||||
#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
|
||||
|
||||
err = pci_enable_msix(priv->pdev, entries, ARRAY_SIZE(entries));
|
||||
if (err) {
|
||||
if (err > 0)
|
||||
dev_info(&priv->pdev->dev,
|
||||
"Only %d MSI-X vectors available, "
|
||||
"not using MSI-X\n", err);
|
||||
else
|
||||
dev_err(&priv->pdev->dev,
|
||||
"Failed to enable MSI-X (err=%d)\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
@@ -760,6 +797,22 @@ static int tsi721_enable_msix(struct tsi721_device *priv)
|
||||
i, pci_name(priv->pdev));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
for (i = 0; i < TSI721_DMA_CHNUM; i++) {
|
||||
priv->msix[TSI721_VECT_DMA0_DONE + i].vector =
|
||||
entries[TSI721_VECT_DMA0_DONE + i].vector;
|
||||
snprintf(priv->msix[TSI721_VECT_DMA0_DONE + i].irq_name,
|
||||
IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmad%d@pci:%s",
|
||||
i, pci_name(priv->pdev));
|
||||
|
||||
priv->msix[TSI721_VECT_DMA0_INT + i].vector =
|
||||
entries[TSI721_VECT_DMA0_INT + i].vector;
|
||||
snprintf(priv->msix[TSI721_VECT_DMA0_INT + i].irq_name,
|
||||
IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmai%d@pci:%s",
|
||||
i, pci_name(priv->pdev));
|
||||
}
|
||||
#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PCI_MSI */
|
||||
@@ -888,20 +941,34 @@ static void tsi721_doorbell_free(struct tsi721_device *priv)
|
||||
priv->idb_base = NULL;
|
||||
}
|
||||
|
||||
static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
|
||||
/**
|
||||
* tsi721_bdma_maint_init - Initialize maintenance request BDMA channel.
|
||||
* @priv: pointer to tsi721 private data
|
||||
*
|
||||
* Initialize BDMA channel allocated for RapidIO maintenance read/write
|
||||
* request generation
|
||||
* Returns %0 on success or %-ENOMEM on failure.
|
||||
*/
|
||||
static int tsi721_bdma_maint_init(struct tsi721_device *priv)
|
||||
{
|
||||
struct tsi721_dma_desc *bd_ptr;
|
||||
u64 *sts_ptr;
|
||||
dma_addr_t bd_phys, sts_phys;
|
||||
int sts_size;
|
||||
int bd_num = priv->bdma[chnum].bd_num;
|
||||
int bd_num = 2;
|
||||
void __iomem *regs;
|
||||
|
||||
dev_dbg(&priv->pdev->dev, "Init Block DMA Engine, CH%d\n", chnum);
|
||||
dev_dbg(&priv->pdev->dev,
|
||||
"Init Block DMA Engine for Maintenance requests, CH%d\n",
|
||||
TSI721_DMACH_MAINT);
|
||||
|
||||
/*
|
||||
* Initialize DMA channel for maintenance requests
|
||||
*/
|
||||
|
||||
priv->mdma.ch_id = TSI721_DMACH_MAINT;
|
||||
regs = priv->regs + TSI721_DMAC_BASE(TSI721_DMACH_MAINT);
|
||||
|
||||
/* Allocate space for DMA descriptors */
|
||||
bd_ptr = dma_zalloc_coherent(&priv->pdev->dev,
|
||||
bd_num * sizeof(struct tsi721_dma_desc),
|
||||
@@ -909,8 +976,9 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
|
||||
if (!bd_ptr)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->bdma[chnum].bd_phys = bd_phys;
|
||||
priv->bdma[chnum].bd_base = bd_ptr;
|
||||
priv->mdma.bd_num = bd_num;
|
||||
priv->mdma.bd_phys = bd_phys;
|
||||
priv->mdma.bd_base = bd_ptr;
|
||||
|
||||
dev_dbg(&priv->pdev->dev, "DMA descriptors @ %p (phys = %llx)\n",
|
||||
bd_ptr, (unsigned long long)bd_phys);
|
||||
@@ -927,13 +995,13 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
|
||||
dma_free_coherent(&priv->pdev->dev,
|
||||
bd_num * sizeof(struct tsi721_dma_desc),
|
||||
bd_ptr, bd_phys);
|
||||
priv->bdma[chnum].bd_base = NULL;
|
||||
priv->mdma.bd_base = NULL;
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
priv->bdma[chnum].sts_phys = sts_phys;
|
||||
priv->bdma[chnum].sts_base = sts_ptr;
|
||||
priv->bdma[chnum].sts_size = sts_size;
|
||||
priv->mdma.sts_phys = sts_phys;
|
||||
priv->mdma.sts_base = sts_ptr;
|
||||
priv->mdma.sts_size = sts_size;
|
||||
|
||||
dev_dbg(&priv->pdev->dev,
|
||||
"desc status FIFO @ %p (phys = %llx) size=0x%x\n",
|
||||
@@ -946,83 +1014,61 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
|
||||
bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32);
|
||||
|
||||
/* Setup DMA descriptor pointers */
|
||||
iowrite32(((u64)bd_phys >> 32),
|
||||
priv->regs + TSI721_DMAC_DPTRH(chnum));
|
||||
iowrite32(((u64)bd_phys >> 32), regs + TSI721_DMAC_DPTRH);
|
||||
iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
|
||||
priv->regs + TSI721_DMAC_DPTRL(chnum));
|
||||
regs + TSI721_DMAC_DPTRL);
|
||||
|
||||
/* Setup descriptor status FIFO */
|
||||
iowrite32(((u64)sts_phys >> 32),
|
||||
priv->regs + TSI721_DMAC_DSBH(chnum));
|
||||
iowrite32(((u64)sts_phys >> 32), regs + TSI721_DMAC_DSBH);
|
||||
iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
|
||||
priv->regs + TSI721_DMAC_DSBL(chnum));
|
||||
regs + TSI721_DMAC_DSBL);
|
||||
iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
|
||||
priv->regs + TSI721_DMAC_DSSZ(chnum));
|
||||
regs + TSI721_DMAC_DSSZ);
|
||||
|
||||
/* Clear interrupt bits */
|
||||
iowrite32(TSI721_DMAC_INT_ALL,
|
||||
priv->regs + TSI721_DMAC_INT(chnum));
|
||||
iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
|
||||
|
||||
ioread32(priv->regs + TSI721_DMAC_INT(chnum));
|
||||
ioread32(regs + TSI721_DMAC_INT);
|
||||
|
||||
/* Toggle DMA channel initialization */
|
||||
iowrite32(TSI721_DMAC_CTL_INIT, priv->regs + TSI721_DMAC_CTL(chnum));
|
||||
ioread32(priv->regs + TSI721_DMAC_CTL(chnum));
|
||||
iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
|
||||
ioread32(regs + TSI721_DMAC_CTL);
|
||||
udelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tsi721_bdma_ch_free(struct tsi721_device *priv, int chnum)
|
||||
static int tsi721_bdma_maint_free(struct tsi721_device *priv)
|
||||
{
|
||||
u32 ch_stat;
|
||||
struct tsi721_bdma_maint *mdma = &priv->mdma;
|
||||
void __iomem *regs = priv->regs + TSI721_DMAC_BASE(mdma->ch_id);
|
||||
|
||||
if (priv->bdma[chnum].bd_base == NULL)
|
||||
if (mdma->bd_base == NULL)
|
||||
return 0;
|
||||
|
||||
/* Check if DMA channel still running */
|
||||
ch_stat = ioread32(priv->regs + TSI721_DMAC_STS(chnum));
|
||||
ch_stat = ioread32(regs + TSI721_DMAC_STS);
|
||||
if (ch_stat & TSI721_DMAC_STS_RUN)
|
||||
return -EFAULT;
|
||||
|
||||
/* Put DMA channel into init state */
|
||||
iowrite32(TSI721_DMAC_CTL_INIT,
|
||||
priv->regs + TSI721_DMAC_CTL(chnum));
|
||||
iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
|
||||
|
||||
/* Free space allocated for DMA descriptors */
|
||||
dma_free_coherent(&priv->pdev->dev,
|
||||
priv->bdma[chnum].bd_num * sizeof(struct tsi721_dma_desc),
|
||||
priv->bdma[chnum].bd_base, priv->bdma[chnum].bd_phys);
|
||||
priv->bdma[chnum].bd_base = NULL;
|
||||
mdma->bd_num * sizeof(struct tsi721_dma_desc),
|
||||
mdma->bd_base, mdma->bd_phys);
|
||||
mdma->bd_base = NULL;
|
||||
|
||||
/* Free space allocated for status FIFO */
|
||||
dma_free_coherent(&priv->pdev->dev,
|
||||
priv->bdma[chnum].sts_size * sizeof(struct tsi721_dma_sts),
|
||||
priv->bdma[chnum].sts_base, priv->bdma[chnum].sts_phys);
|
||||
priv->bdma[chnum].sts_base = NULL;
|
||||
mdma->sts_size * sizeof(struct tsi721_dma_sts),
|
||||
mdma->sts_base, mdma->sts_phys);
|
||||
mdma->sts_base = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tsi721_bdma_init(struct tsi721_device *priv)
|
||||
{
|
||||
/* Initialize BDMA channel allocated for RapidIO maintenance read/write
|
||||
* request generation
|
||||
*/
|
||||
priv->bdma[TSI721_DMACH_MAINT].bd_num = 2;
|
||||
if (tsi721_bdma_ch_init(priv, TSI721_DMACH_MAINT)) {
|
||||
dev_err(&priv->pdev->dev, "Unable to initialize maintenance DMA"
|
||||
" channel %d, aborting\n", TSI721_DMACH_MAINT);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tsi721_bdma_free(struct tsi721_device *priv)
|
||||
{
|
||||
tsi721_bdma_ch_free(priv, TSI721_DMACH_MAINT);
|
||||
}
|
||||
|
||||
/* Enable Inbound Messaging Interrupts */
|
||||
static void
|
||||
tsi721_imsg_interrupt_enable(struct tsi721_device *priv, int ch,
|
||||
@@ -2035,7 +2081,8 @@ static void tsi721_disable_ints(struct tsi721_device *priv)
|
||||
|
||||
/* Disable all BDMA Channel interrupts */
|
||||
for (ch = 0; ch < TSI721_DMA_MAXCH; ch++)
|
||||
iowrite32(0, priv->regs + TSI721_DMAC_INTE(ch));
|
||||
iowrite32(0,
|
||||
priv->regs + TSI721_DMAC_BASE(ch) + TSI721_DMAC_INTE);
|
||||
|
||||
/* Disable all general BDMA interrupts */
|
||||
iowrite32(0, priv->regs + TSI721_BDMA_INTE);
|
||||
@@ -2104,6 +2151,7 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
|
||||
mport->phy_type = RIO_PHY_SERIAL;
|
||||
mport->priv = (void *)priv;
|
||||
mport->phys_efptr = 0x100;
|
||||
priv->mport = mport;
|
||||
|
||||
INIT_LIST_HEAD(&mport->dbells);
|
||||
|
||||
@@ -2129,17 +2177,21 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
|
||||
if (!err) {
|
||||
tsi721_interrupts_init(priv);
|
||||
ops->pwenable = tsi721_pw_enable;
|
||||
} else
|
||||
} else {
|
||||
dev_err(&pdev->dev, "Unable to get assigned PCI IRQ "
|
||||
"vector %02X err=0x%x\n", pdev->irq, err);
|
||||
goto err_exit;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
tsi721_register_dma(priv);
|
||||
#endif
|
||||
/* Enable SRIO link */
|
||||
iowrite32(ioread32(priv->regs + TSI721_DEVCTL) |
|
||||
TSI721_DEVCTL_SRBOOT_CMPL,
|
||||
priv->regs + TSI721_DEVCTL);
|
||||
|
||||
rio_register_mport(mport);
|
||||
priv->mport = mport;
|
||||
|
||||
if (mport->host_deviceid >= 0)
|
||||
iowrite32(RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER |
|
||||
@@ -2149,6 +2201,11 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
|
||||
iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
|
||||
|
||||
return 0;
|
||||
|
||||
err_exit:
|
||||
kfree(mport);
|
||||
kfree(ops);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __devinit tsi721_probe(struct pci_dev *pdev,
|
||||
@@ -2294,7 +2351,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
|
||||
tsi721_init_pc2sr_mapping(priv);
|
||||
tsi721_init_sr2pc_mapping(priv);
|
||||
|
||||
if (tsi721_bdma_init(priv)) {
|
||||
if (tsi721_bdma_maint_init(priv)) {
|
||||
dev_err(&pdev->dev, "BDMA initialization failed, aborting\n");
|
||||
err = -ENOMEM;
|
||||
goto err_unmap_bars;
|
||||
@@ -2319,7 +2376,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
|
||||
err_free_consistent:
|
||||
tsi721_doorbell_free(priv);
|
||||
err_free_bdma:
|
||||
tsi721_bdma_free(priv);
|
||||
tsi721_bdma_maint_free(priv);
|
||||
err_unmap_bars:
|
||||
if (priv->regs)
|
||||
iounmap(priv->regs);
|
||||
|
||||
@@ -167,6 +167,8 @@
|
||||
#define TSI721_DEV_INTE 0x29840
|
||||
#define TSI721_DEV_INT 0x29844
|
||||
#define TSI721_DEV_INTSET 0x29848
|
||||
#define TSI721_DEV_INT_BDMA_CH 0x00002000
|
||||
#define TSI721_DEV_INT_BDMA_NCH 0x00001000
|
||||
#define TSI721_DEV_INT_SMSG_CH 0x00000800
|
||||
#define TSI721_DEV_INT_SMSG_NCH 0x00000400
|
||||
#define TSI721_DEV_INT_SR2PC_CH 0x00000200
|
||||
@@ -181,6 +183,8 @@
|
||||
#define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x)))
|
||||
#define TSI721_INT_OMSG_CHAN_M 0x0000ff00
|
||||
#define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x)))
|
||||
#define TSI721_INT_BDMA_CHAN_M 0x000000ff
|
||||
#define TSI721_INT_BDMA_CHAN(x) (1 << (x))
|
||||
|
||||
/*
|
||||
* PC2SR block registers
|
||||
@@ -235,14 +239,16 @@
|
||||
* x = 0..7
|
||||
*/
|
||||
|
||||
#define TSI721_DMAC_DWRCNT(x) (0x51000 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DRDCNT(x) (0x51004 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_BASE(x) (0x51000 + (x) * 0x1000)
|
||||
|
||||
#define TSI721_DMAC_CTL(x) (0x51008 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DWRCNT 0x000
|
||||
#define TSI721_DMAC_DRDCNT 0x004
|
||||
|
||||
#define TSI721_DMAC_CTL 0x008
|
||||
#define TSI721_DMAC_CTL_SUSP 0x00000002
|
||||
#define TSI721_DMAC_CTL_INIT 0x00000001
|
||||
|
||||
#define TSI721_DMAC_INT(x) (0x5100c + (x) * 0x1000)
|
||||
#define TSI721_DMAC_INT 0x00c
|
||||
#define TSI721_DMAC_INT_STFULL 0x00000010
|
||||
#define TSI721_DMAC_INT_DONE 0x00000008
|
||||
#define TSI721_DMAC_INT_SUSP 0x00000004
|
||||
@@ -250,34 +256,33 @@
|
||||
#define TSI721_DMAC_INT_IOFDONE 0x00000001
|
||||
#define TSI721_DMAC_INT_ALL 0x0000001f
|
||||
|
||||
#define TSI721_DMAC_INTSET(x) (0x51010 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_INTSET 0x010
|
||||
|
||||
#define TSI721_DMAC_STS(x) (0x51014 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_STS 0x014
|
||||
#define TSI721_DMAC_STS_ABORT 0x00400000
|
||||
#define TSI721_DMAC_STS_RUN 0x00200000
|
||||
#define TSI721_DMAC_STS_CS 0x001f0000
|
||||
|
||||
#define TSI721_DMAC_INTE(x) (0x51018 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_INTE 0x018
|
||||
|
||||
#define TSI721_DMAC_DPTRL(x) (0x51024 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DPTRL 0x024
|
||||
#define TSI721_DMAC_DPTRL_MASK 0xffffffe0
|
||||
|
||||
#define TSI721_DMAC_DPTRH(x) (0x51028 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DPTRH 0x028
|
||||
|
||||
#define TSI721_DMAC_DSBL(x) (0x5102c + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DSBL 0x02c
|
||||
#define TSI721_DMAC_DSBL_MASK 0xffffffc0
|
||||
|
||||
#define TSI721_DMAC_DSBH(x) (0x51030 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DSBH 0x030
|
||||
|
||||
#define TSI721_DMAC_DSSZ(x) (0x51034 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DSSZ 0x034
|
||||
#define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f
|
||||
#define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4)
|
||||
|
||||
|
||||
#define TSI721_DMAC_DSRP(x) (0x51038 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DSRP 0x038
|
||||
#define TSI721_DMAC_DSRP_MASK 0x0007ffff
|
||||
|
||||
#define TSI721_DMAC_DSWP(x) (0x5103c + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DSWP 0x03c
|
||||
#define TSI721_DMAC_DSWP_MASK 0x0007ffff
|
||||
|
||||
#define TSI721_BDMA_INTE 0x5f000
|
||||
@@ -612,6 +617,8 @@ enum dma_rtype {
|
||||
#define TSI721_DMACH_MAINT 0 /* DMA channel for maint requests */
|
||||
#define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */
|
||||
|
||||
#define TSI721_DMACH_DMA 1 /* DMA channel for data transfers */
|
||||
|
||||
#define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0)
|
||||
|
||||
enum tsi721_smsg_int_flag {
|
||||
@@ -626,7 +633,48 @@ enum tsi721_smsg_int_flag {
|
||||
|
||||
/* Structures */
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
|
||||
struct tsi721_tx_desc {
|
||||
struct dma_async_tx_descriptor txd;
|
||||
struct tsi721_dma_desc *hw_desc;
|
||||
u16 destid;
|
||||
/* low 64-bits of 66-bit RIO address */
|
||||
u64 rio_addr;
|
||||
/* upper 2-bits of 66-bit RIO address */
|
||||
u8 rio_addr_u;
|
||||
bool interrupt;
|
||||
struct list_head desc_node;
|
||||
struct list_head tx_list;
|
||||
};
|
||||
|
||||
struct tsi721_bdma_chan {
|
||||
int id;
|
||||
void __iomem *regs;
|
||||
int bd_num; /* number of buffer descriptors */
|
||||
void *bd_base; /* start of DMA descriptors */
|
||||
dma_addr_t bd_phys;
|
||||
void *sts_base; /* start of DMA BD status FIFO */
|
||||
dma_addr_t sts_phys;
|
||||
int sts_size;
|
||||
u32 sts_rdptr;
|
||||
u32 wr_count;
|
||||
u32 wr_count_next;
|
||||
|
||||
struct dma_chan dchan;
|
||||
struct tsi721_tx_desc *tx_desc;
|
||||
spinlock_t lock;
|
||||
struct list_head active_list;
|
||||
struct list_head queue;
|
||||
struct list_head free_list;
|
||||
dma_cookie_t completed_cookie;
|
||||
struct tasklet_struct tasklet;
|
||||
};
|
||||
|
||||
#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
|
||||
|
||||
struct tsi721_bdma_maint {
|
||||
int ch_id; /* BDMA channel number */
|
||||
int bd_num; /* number of buffer descriptors */
|
||||
void *bd_base; /* start of DMA descriptors */
|
||||
dma_addr_t bd_phys;
|
||||
@@ -721,6 +769,24 @@ enum tsi721_msix_vect {
|
||||
TSI721_VECT_IMB1_INT,
|
||||
TSI721_VECT_IMB2_INT,
|
||||
TSI721_VECT_IMB3_INT,
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
TSI721_VECT_DMA0_DONE,
|
||||
TSI721_VECT_DMA1_DONE,
|
||||
TSI721_VECT_DMA2_DONE,
|
||||
TSI721_VECT_DMA3_DONE,
|
||||
TSI721_VECT_DMA4_DONE,
|
||||
TSI721_VECT_DMA5_DONE,
|
||||
TSI721_VECT_DMA6_DONE,
|
||||
TSI721_VECT_DMA7_DONE,
|
||||
TSI721_VECT_DMA0_INT,
|
||||
TSI721_VECT_DMA1_INT,
|
||||
TSI721_VECT_DMA2_INT,
|
||||
TSI721_VECT_DMA3_INT,
|
||||
TSI721_VECT_DMA4_INT,
|
||||
TSI721_VECT_DMA5_INT,
|
||||
TSI721_VECT_DMA6_INT,
|
||||
TSI721_VECT_DMA7_INT,
|
||||
#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
|
||||
TSI721_VECT_MAX
|
||||
};
|
||||
|
||||
@@ -754,7 +820,11 @@ struct tsi721_device {
|
||||
u32 pw_discard_count;
|
||||
|
||||
/* BDMA Engine */
|
||||
struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM];
|
||||
#endif
|
||||
|
||||
/* Inbound Messaging */
|
||||
int imsg_init[TSI721_IMSG_CHNUM];
|
||||
@@ -765,4 +835,9 @@ struct tsi721_device {
|
||||
struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM];
|
||||
};
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
extern void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan);
|
||||
extern int __devinit tsi721_register_dma(struct tsi721_device *priv);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user