Fix misc .c/.h comment typos

Fix various .c/.h typos in comments (no code changes).

Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
This commit is contained in:
Matt LaPlante
2006-11-30 05:24:39 +01:00
committed by Adrian Bunk
parent 3cb2fccc5f
commit 0779bf2d2e
39 changed files with 71 additions and 71 deletions
+3 -3
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@@ -1,7 +1,7 @@
/*!*****************************************************************************
*!
*! Implements an interface for i2c compatible eeproms to run under linux.
*! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustents by
*! Implements an interface for i2c compatible eeproms to run under Linux.
*! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustments by
*! Johan.Adolfsson@axis.com
*!
*! Probing results:
@@ -51,7 +51,7 @@
*! Revision 1.8 2001/06/15 13:24:29 jonashg
*! * Added verification of pointers from userspace in read and write.
*! * Made busy counter volatile.
*! * Added define for inital write delay.
*! * Added define for initial write delay.
*! * Removed warnings by using loff_t instead of unsigned long.
*!
*! Revision 1.7 2001/06/14 15:26:54 jonashg
+1 -1
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@@ -47,7 +47,7 @@
*! Update Port B register and shadow even when running with hardware support
*! to avoid glitches when reading bits
*! Never set direction to out in i2c_inbyte
*! Removed incorrect clock togling at end of i2c_inbyte
*! Removed incorrect clock toggling at end of i2c_inbyte
*!
*! Revision 1.8 2002/08/13 06:31:53 starvik
*! Made SDA and SCL line configurable
+1 -1
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@@ -33,7 +33,7 @@
*!
*! Revision 1.2 2002/11/19 14:35:24 starvik
*! Changes from linux 2.4
*! Changed struct initializer syntax to the currently prefered notation
*! Changed struct initializer syntax to the currently preferred notation
*!
*! Revision 1.1 2001/12/17 13:59:27 bjornw
*! Initial revision
+4 -4
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@@ -75,7 +75,7 @@
** If a device prefetches beyond the end of a valid pdir entry, it will cause
** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should
** disconnect on 4k boundaries and prevent such issues. If the device is
** particularly agressive, this option will keep the entire pdir valid such
** particularly aggressive, this option will keep the entire pdir valid such
** that prefetching will hit a valid address. This could severely impact
** error containment, and is therefore off by default. The page that is
** used for spill-over is poisoned, so that should help debugging somewhat.
@@ -258,10 +258,10 @@ static u64 prefetch_spill_page;
/*
** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
** (or rather not merge) DMA's into managable chunks.
** (or rather not merge) DMAs into manageable chunks.
** On parisc, this is more of the software/tuning constraint
** rather than the HW. I/O MMU allocation alogorithms can be
** faster with smaller size is (to some degree).
** rather than the HW. I/O MMU allocation algorithms can be
** faster with smaller sizes (to some degree).
*/
#define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size)
+1 -1
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@@ -383,7 +383,7 @@ void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs)
/* ======================================================================= */
/*
** Depending on <base> scan the MMU, Data or Instrction side
** Depending on <base> scan the MMU, Data or Instruction side
** looking for a valid mapping matching Eaddr & asid.
** Return -1 if not found or the TLB id entry otherwise.
** Note: it works only for 4k pages!
+1 -1
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@@ -305,7 +305,7 @@ static void clear_lockup (struct atm_vcc *vcc, IADEV *dev) {
** | R | NZ | 5-bit exponent | 9-bit mantissa |
** +----+----+------------------+-------------------------------+
**
** R = reserverd (written as 0)
** R = reserved (written as 0)
** NZ = 0 if 0 cells/sec; 1 otherwise
**
** if NZ = 1, rate = 1.mmmmmmmmm x 2^(eeeee) cells/sec
+1 -1
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@@ -922,7 +922,7 @@ int RIOUnUse(unsigned long iPortP, struct CmdBlk *CmdBlkP)
**
** Packet is an actual packet structure to be filled in with the packet
** information associated with the command. You need to fill in everything,
** as the command processore doesn't process the command packet in any way.
** as the command processor doesn't process the command packet in any way.
**
** The PreFuncP is called before the packet is enqueued on the host rup.
** PreFuncP is called as (*PreFuncP)(PreArg, CmdBlkP);. PreFuncP must
+1 -1
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@@ -222,7 +222,7 @@ int RIOBoardTest(unsigned long paddr, void __iomem *caddr, unsigned char type, i
** which value will be written into memory.
** Call with op set to zero means that the RAM will not be read and checked
** before it is written.
** Call with op not zero, and the RAM will be read and compated with val[op-1]
** Call with op not zero and the RAM will be read and compared with val[op-1]
** to check that the data from the previous phase was retained.
*/
+3 -3
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@@ -87,8 +87,8 @@ static char *_rioparam_c_sccs_ = "@(#)rioparam.c 1.3";
** command bit set onto the port. The command bit is in the len field,
** and gets ORed in with the actual byte count.
**
** When you send a packet with the command bit set, then the first
** data byte ( data[0] ) is interpretted as the command to execute.
** When you send a packet with the command bit set the first
** data byte (data[0]) is interpreted as the command to execute.
** It also governs what data structure overlay should accompany the packet.
** Commands are defined in cirrus/cirrus.h
**
@@ -103,7 +103,7 @@ static char *_rioparam_c_sccs_ = "@(#)rioparam.c 1.3";
**
** Most commands do not use the remaining bytes in the data array. The
** exceptions are OPEN MOPEN and CONFIG. (NB. As with the SI CONFIG and
** OPEN are currently analagous). With these three commands the following
** OPEN are currently analogous). With these three commands the following
** 11 data bytes are all used to pass config information such as baud rate etc.
** The fields are also defined in cirrus.h. Some contain straightforward
** information such as the transmit XON character. Two contain the transmit and
+1 -1
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@@ -1635,7 +1635,7 @@ static int idefloppy_begin_format(ide_drive_t *drive, int __user *arg)
/*
** Get ATAPI_FORMAT_UNIT progress indication.
**
** Userland gives a pointer to an int. The int is set to a progresss
** Userland gives a pointer to an int. The int is set to a progress
** indicator 0-65536, with 65536=100%.
**
** If the drive does not support format progress indication, we just check
+1 -1
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@@ -464,7 +464,7 @@ int diva_4bri_init_card(diva_os_xdi_adapter_t * a)
/*
** Cleanup function will be called for master adapter only
** this is garanteed by design: cleanup callback is set
** this is guaranteed by design: cleanup callback is set
** by master adapter only
*/
static int diva_4bri_cleanup_adapter(diva_os_xdi_adapter_t * a)
+1 -1
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@@ -16,7 +16,7 @@
/*
* include Genero generated HFC-4S/8S header file hfc48scu.h
* for comlete register description. This will define _HFC48SCU_H_
* for complete register description. This will define _HFC48SCU_H_
* to prevent redefinitions
*/
+4 -4
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@@ -500,14 +500,14 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
/* New design (By Emard)
** this rps1 code will copy internal HS event to GPIO3 pin.
** GPIO3 is in budget-patch hardware connectd to port B VSYNC
** GPIO3 is in budget-patch hardware connected to port B VSYNC
** HS is an internal event of 7146, accessible with RPS
** and temporarily raised high every n lines
** (n in defined in the RPS_THRESH1 counter threshold)
** I think HS is raised high on the beginning of the n-th line
** and remains high until this n-th line that triggered
** it is completely received. When the receiption of n-th line
** it is completely received. When the reception of n-th line
** ends, HS is lowered.
** To transmit data over DMA, 7146 needs changing state at
@@ -541,7 +541,7 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
** hardware debug note: a working budget card (including budget patch)
** with vpeirq() interrupt setup in mode "0x90" (every 64K) will
** generate 3 interrupts per 25-Hz DMA frame of 2*188*512 bytes
** and that means 3*25=75 Hz of interrupt freqency, as seen by
** and that means 3*25=75 Hz of interrupt frequency, as seen by
** watch cat /proc/interrupts
**
** If this frequency is 3x lower (and data received in the DMA
@@ -550,7 +550,7 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
** this means VSYNC line is not connected in the hardware.
** (check soldering pcb and pins)
** The same behaviour of missing VSYNC can be duplicated on budget
** cards, by seting DD1_INIT trigger mode 7 in 3rd nibble.
** cards, by setting DD1_INIT trigger mode 7 in 3rd nibble.
*/
// Setup RPS1 "program" (p35)
+1 -1
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@@ -1215,7 +1215,7 @@ static void e100_setup_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb
* the literal in the instruction before the code is loaded, the
* driver can change the algorithm.
*
* INTDELAY - This loads the dead-man timer with its inital value.
* INTDELAY - This loads the dead-man timer with its initial value.
* When this timer expires the interrupt is asserted, and the
* timer is reset each time a new packet is received. (see
* BUNDLEMAX below to set the limit on number of chained packets)
+1 -1
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@@ -3868,7 +3868,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
*
* hw - Struct containing variables accessed by shared code
*
* Sets bit 15 of the MII Control regiser
* Sets bit 15 of the MII Control register
******************************************************************************/
int32_t
e1000_phy_reset(struct e1000_hw *hw)
+1 -1
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@@ -160,7 +160,7 @@ struct s_IOCTL {
/*
** Interim definition of SK_DRV_TIMER placed in this file until
** common modules have boon finallized
** common modules have been finalized
*/
#define SK_DRV_TIMER 11
#define SK_DRV_MODERATION_TIMER 1
+2 -2
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@@ -252,7 +252,7 @@ SkDimEnableModerationIfNeeded(SK_AC *pAC) {
/*******************************************************************************
** Function : SkDimDisplayModerationSettings
** Description : Displays the current settings regaring interrupt moderation
** Description : Displays the current settings regarding interrupt moderation
** Programmer : Ralph Roesler
** Last Modified: 22-mar-03
** Returns : void (!)
@@ -510,7 +510,7 @@ EnableIntMod(SK_AC *pAC) {
/*******************************************************************************
** Function : DisableIntMod()
** Description : Disbles the interrupt moderation independent of what inter-
** Description : Disables the interrupt moderation independent of what inter-
** rupts are running or not
** Programmer : Ralph Roesler
** Last Modified: 23-mar-03
+2 -2
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@@ -6920,8 +6920,8 @@ static int ipw_qos_association(struct ipw_priv *priv,
}
/*
* handling the beaconing responces. if we get different QoS setting
* of the network from the the associated setting adjust the QoS
* handling the beaconing responses. if we get different QoS setting
* off the network from the associated setting, adjust the QoS
* setting
*/
static int ipw_qos_association_resp(struct ipw_priv *priv,
+1 -1
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@@ -486,7 +486,7 @@ typedef unsigned long space_t;
** This bit tells U2 to do R/M/W for partial cachelines. "Streaming"
** data can avoid this if the mapping covers full cache lines.
** o STOP_MOST is needed for atomicity across cachelines.
** Apperently only "some EISA devices" need this.
** Apparently only "some EISA devices" need this.
** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs
** to use this hint iff the EISA devices needs this feature.
** According to the U2 ERS, STOP_MOST enabled pages hurt performance.
+3 -3
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@@ -50,12 +50,12 @@
**
** PA Firmware
** -----------
** PA-RISC platforms have two fundementally different types of firmware.
** PA-RISC platforms have two fundamentally different types of firmware.
** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register
** and BARs similar to a traditional PC BIOS.
** The newer "PAT" firmware supports PDC calls which return tables.
** PAT firmware only initializes PCI Console and Boot interface.
** With these tables, the OS can progam all other PCI devices.
** PAT firmware only initializes the PCI Console and Boot interface.
** With these tables, the OS can program all other PCI devices.
**
** One such PAT PDC call returns the "Interrupt Routing Table" (IRT).
** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC

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