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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (31 commits) ARM: OMAP: Fix export.h or module.h includes ARM: OMAP: omap_device: Include linux/export.h ARM: OMAP2: Fix H4 matrix keyboard warning ARM: OMAP1: Remove unused omap-alsa.h ARM: OMAP1: Fix warnings about enabling 32 KiHz timer ARM: OMAP2+: timer: Remove omap_device_pm_latency ARM: OMAP2+: clock data: Remove redundant timer clkdev ARM: OMAP: Devkit8000: Remove double omap_mux_init_gpio ARM: OMAP: usb: musb: OMAP: Delete unused function MAINTAINERS: Update linux-omap git repository ARM: OMAP: change get_context_loss_count ret value to int ARM: OMAP4: hsmmc: configure SDMMC1_DR0 properly ARM: OMAP4: hsmmc: Fix Pbias configuration on regulator OFF ARM: OMAP3: hwmod: fix variant registration and remove SmartReflex from common list ARM: OMAP: I2C: Fix omap_register_i2c_bus() return value on success ARM: OMAP: dmtimer: Include linux/module.h ARM: OMAP2+: l3-noc: Include linux/module.h ARM: OMAP2+: devices: Fixes for McPDM ARM: OMAP: Fix errors and warnings when building for one board ARM: OMAP3: PM: restrict erratum i443 handling to OMAP3430 only ...
This commit is contained in:
Linus Torvalds
+1
-1
@@ -4673,7 +4673,7 @@ L: linux-omap@vger.kernel.org
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W: http://www.muru.com/linux/omap/
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W: http://linux.omap.com/
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Q: http://patchwork.kernel.org/project/linux-omap/list/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
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S: Maintained
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F: arch/arm/*omap*/
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@@ -42,7 +42,6 @@
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#include <plat/irda.h>
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#include <plat/keypad.h>
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#include <plat/common.h>
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#include <plat/omap-alsa.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/ads7846.h>
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@@ -116,7 +116,7 @@ void omap1_pm_idle(void)
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return;
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}
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#ifdef CONFIG_OMAP_MPU_TIMER
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#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
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#warning Enable 32kHz OS timer in order to allow sleep states in idle
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use_idlect1 = use_idlect1 & ~(1 << 9);
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#else
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@@ -226,7 +226,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
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{
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int ret;
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omap_mux_init_gpio(29, OMAP_PIN_INPUT);
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/* gpio + 0 is "mmc0_cd" (input/IRQ) */
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mmc[0].gpio_cd = gpio + 0;
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omap2_hsmmc_init(mmc);
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@@ -28,6 +28,7 @@
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* XXX: Still needed to boot until the i2c & twl driver is adapted to
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* device-tree
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*/
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#ifdef CONFIG_ARCH_OMAP4
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static struct twl4030_platform_data sdp4430_twldata = {
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.irq_base = TWL6030_IRQ_BASE,
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.irq_end = TWL6030_IRQ_END,
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@@ -37,7 +38,9 @@ static void __init omap4_i2c_init(void)
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{
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omap4_pmic_init("twl6030", &sdp4430_twldata);
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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static struct twl4030_platform_data beagle_twldata = {
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.irq_base = TWL4030_IRQ_BASE,
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.irq_end = TWL4030_IRQ_END,
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@@ -47,6 +50,7 @@ static void __init omap3_i2c_init(void)
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{
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omap3_pmic_init("twl4030", &beagle_twldata);
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}
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#endif
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static struct of_device_id omap_dt_match_table[] __initdata = {
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{ .compatible = "simple-bus", },
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@@ -72,17 +76,21 @@ static void __init omap_generic_init(void)
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of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
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}
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#ifdef CONFIG_ARCH_OMAP4
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static void __init omap4_init(void)
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{
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omap4_i2c_init();
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omap_generic_init();
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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static void __init omap3_init(void)
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{
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omap3_i2c_init();
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omap_generic_init();
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}
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#endif
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#if defined(CONFIG_SOC_OMAP2420)
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static const char *omap242x_boards_compat[] __initdata = {
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@@ -25,6 +25,7 @@
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/input/matrix_keypad.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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@@ -34,7 +35,6 @@
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#include <plat/usb.h>
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#include <plat/board.h>
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#include <plat/common.h>
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#include <plat/keypad.h>
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#include <plat/menelaus.h>
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#include <plat/dma.h>
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#include <plat/gpmc.h>
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@@ -50,10 +50,8 @@
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#define H4_ETHR_GPIO_IRQ 92
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static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
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static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
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static const unsigned int h4_keymap[] = {
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#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
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static const uint32_t board_matrix_keys[] = {
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KEY(0, 0, KEY_LEFT),
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KEY(1, 0, KEY_RIGHT),
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KEY(2, 0, KEY_A),
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@@ -86,6 +84,71 @@ static const unsigned int h4_keymap[] = {
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KEY(4, 5, KEY_ENTER),
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};
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static const struct matrix_keymap_data board_keymap_data = {
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.keymap = board_matrix_keys,
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.keymap_size = ARRAY_SIZE(board_matrix_keys),
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};
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static unsigned int board_keypad_row_gpios[] = {
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88, 89, 124, 11, 6, 96
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};
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static unsigned int board_keypad_col_gpios[] = {
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90, 91, 100, 36, 12, 97, 98
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};
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static struct matrix_keypad_platform_data board_keypad_platform_data = {
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.keymap_data = &board_keymap_data,
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.row_gpios = board_keypad_row_gpios,
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.num_row_gpios = ARRAY_SIZE(board_keypad_row_gpios),
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.col_gpios = board_keypad_col_gpios,
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.num_col_gpios = ARRAY_SIZE(board_keypad_col_gpios),
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.active_low = 1,
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.debounce_ms = 20,
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.col_scan_delay_us = 5,
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};
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static struct platform_device board_keyboard = {
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.name = "matrix-keypad",
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.id = -1,
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.dev = {
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.platform_data = &board_keypad_platform_data,
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},
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};
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static void __init board_mkp_init(void)
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{
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omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);
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omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP);
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omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP);
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omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
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if (omap_has_menelaus()) {
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omap_mux_init_signal("sdrc_a14.gpio0",
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OMAP_PULL_ENA | OMAP_PULL_UP);
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omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
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omap_mux_init_signal("gpio_98", 0);
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board_keypad_row_gpios[5] = 0;
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board_keypad_col_gpios[2] = 15;
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board_keypad_col_gpios[6] = 18;
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} else {
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omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP);
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omap_mux_init_signal("gpio_100", 0);
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omap_mux_init_signal("gpio_98", 0);
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}
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omap_mux_init_signal("gpio_90", 0);
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omap_mux_init_signal("gpio_91", 0);
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omap_mux_init_signal("gpio_36", 0);
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omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
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omap_mux_init_signal("gpio_97", 0);
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platform_device_register(&board_keyboard);
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}
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#else
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static inline void board_mkp_init(void)
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{
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}
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#endif
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static struct mtd_partition h4_partitions[] = {
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/* bootloader (U-Boot, etc) in first sector */
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{
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@@ -137,31 +200,8 @@ static struct platform_device h4_flash_device = {
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.resource = &h4_flash_resource,
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};
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static const struct matrix_keymap_data h4_keymap_data = {
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.keymap = h4_keymap,
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.keymap_size = ARRAY_SIZE(h4_keymap),
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};
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static struct omap_kp_platform_data h4_kp_data = {
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.rows = 6,
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.cols = 7,
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.keymap_data = &h4_keymap_data,
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.rep = true,
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.row_gpios = row_gpios,
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.col_gpios = col_gpios,
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};
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static struct platform_device h4_kp_device = {
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.name = "omap-keypad",
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.id = -1,
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.dev = {
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.platform_data = &h4_kp_data,
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},
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};
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static struct platform_device *h4_devices[] __initdata = {
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&h4_flash_device,
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&h4_kp_device,
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};
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static struct panel_generic_dpi_data h4_panel_data = {
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@@ -336,31 +376,7 @@ static void __init omap_h4_init(void)
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* if not needed.
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*/
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#if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
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omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);
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omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP);
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omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP);
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omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
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if (omap_has_menelaus()) {
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omap_mux_init_signal("sdrc_a14.gpio0",
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OMAP_PULL_ENA | OMAP_PULL_UP);
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omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
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omap_mux_init_signal("gpio_98", 0);
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row_gpios[5] = 0;
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col_gpios[2] = 15;
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col_gpios[6] = 18;
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} else {
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omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP);
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omap_mux_init_signal("gpio_100", 0);
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omap_mux_init_signal("gpio_98", 0);
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}
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omap_mux_init_signal("gpio_90", 0);
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omap_mux_init_signal("gpio_91", 0);
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omap_mux_init_signal("gpio_36", 0);
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omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
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omap_mux_init_signal("gpio_97", 0);
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#endif
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board_mkp_init();
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i2c_register_board_info(1, h4_i2c_board_info,
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ARRAY_SIZE(h4_i2c_board_info));
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@@ -46,10 +46,19 @@
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(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
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/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
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#define DPLL_FINT_BAND1_MIN 750000
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#define DPLL_FINT_BAND1_MAX 2100000
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#define DPLL_FINT_BAND2_MIN 7500000
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#define DPLL_FINT_BAND2_MAX 21000000
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#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
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#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
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#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
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#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
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/*
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* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
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* From device data manual section 4.3 "DPLL and DLL Specifications".
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*/
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#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
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#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
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#define OMAP3PLUS_DPLL_FINT_MIN 32000
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#define OMAP3PLUS_DPLL_FINT_MAX 52000000
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/* _dpll_test_fint() return codes */
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#define DPLL_FINT_UNDERFLOW -1
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@@ -71,33 +80,43 @@
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static int _dpll_test_fint(struct clk *clk, u8 n)
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{
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struct dpll_data *dd;
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long fint;
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long fint, fint_min, fint_max;
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int ret = 0;
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dd = clk->dpll_data;
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/* DPLL divider must result in a valid jitter correction val */
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fint = clk->parent->rate / n;
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if (fint < DPLL_FINT_BAND1_MIN) {
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if (cpu_is_omap24xx()) {
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/* Should not be called for OMAP2, so warn if it is called */
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WARN(1, "No fint limits available for OMAP2!\n");
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return DPLL_FINT_INVALID;
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} else if (cpu_is_omap3430()) {
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fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
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fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
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} else if (dd->flags & DPLL_J_TYPE) {
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fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
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fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
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} else {
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fint_min = OMAP3PLUS_DPLL_FINT_MIN;
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fint_max = OMAP3PLUS_DPLL_FINT_MAX;
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}
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if (fint < fint_min) {
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pr_debug("rejecting n=%d due to Fint failure, "
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"lowering max_divider\n", n);
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dd->max_divider = n;
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ret = DPLL_FINT_UNDERFLOW;
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} else if (fint > DPLL_FINT_BAND1_MAX &&
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fint < DPLL_FINT_BAND2_MIN) {
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pr_debug("rejecting n=%d due to Fint failure\n", n);
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ret = DPLL_FINT_INVALID;
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} else if (fint > DPLL_FINT_BAND2_MAX) {
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} else if (fint > fint_max) {
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pr_debug("rejecting n=%d due to Fint failure, "
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"boosting min_divider\n", n);
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dd->min_divider = n;
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ret = DPLL_FINT_INVALID;
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} else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
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fint < OMAP3430_DPLL_FINT_BAND2_MIN) {
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pr_debug("rejecting n=%d due to Fint failure\n", n);
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ret = DPLL_FINT_INVALID;
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}
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return ret;
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@@ -66,6 +66,8 @@ void omap3_noncore_dpll_disable(struct clk *clk);
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int omap4_dpllmx_gatectrl_read(struct clk *clk);
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void omap4_dpllmx_allow_gatectrl(struct clk *clk);
|
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void omap4_dpllmx_deny_gatectrl(struct clk *clk);
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long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
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unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
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#ifdef CONFIG_OMAP_RESET_CLOCKS
|
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void omap2_clk_disable_unused(struct clk *clk);
|
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@@ -1898,18 +1898,6 @@ static struct omap_clk omap2420_clks[] = {
|
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CLK(NULL, "pka_ick", &pka_ick, CK_242X),
|
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CLK(NULL, "usb_fck", &usb_fck, CK_242X),
|
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CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
|
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CLK("omap_timer.1", "fck", &gpt1_fck, CK_242X),
|
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CLK("omap_timer.2", "fck", &gpt2_fck, CK_242X),
|
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CLK("omap_timer.3", "fck", &gpt3_fck, CK_242X),
|
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CLK("omap_timer.4", "fck", &gpt4_fck, CK_242X),
|
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CLK("omap_timer.5", "fck", &gpt5_fck, CK_242X),
|
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CLK("omap_timer.6", "fck", &gpt6_fck, CK_242X),
|
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CLK("omap_timer.7", "fck", &gpt7_fck, CK_242X),
|
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CLK("omap_timer.8", "fck", &gpt8_fck, CK_242X),
|
||||
CLK("omap_timer.9", "fck", &gpt9_fck, CK_242X),
|
||||
CLK("omap_timer.10", "fck", &gpt10_fck, CK_242X),
|
||||
CLK("omap_timer.11", "fck", &gpt11_fck, CK_242X),
|
||||
CLK("omap_timer.12", "fck", &gpt12_fck, CK_242X),
|
||||
CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),
|
||||
|
||||
@@ -1998,18 +1998,6 @@ static struct omap_clk omap2430_clks[] = {
|
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CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
|
||||
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
|
||||
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
|
||||
CLK("omap_timer.1", "fck", &gpt1_fck, CK_243X),
|
||||
CLK("omap_timer.2", "fck", &gpt2_fck, CK_243X),
|
||||
CLK("omap_timer.3", "fck", &gpt3_fck, CK_243X),
|
||||
CLK("omap_timer.4", "fck", &gpt4_fck, CK_243X),
|
||||
CLK("omap_timer.5", "fck", &gpt5_fck, CK_243X),
|
||||
CLK("omap_timer.6", "fck", &gpt6_fck, CK_243X),
|
||||
CLK("omap_timer.7", "fck", &gpt7_fck, CK_243X),
|
||||
CLK("omap_timer.8", "fck", &gpt8_fck, CK_243X),
|
||||
CLK("omap_timer.9", "fck", &gpt9_fck, CK_243X),
|
||||
CLK("omap_timer.10", "fck", &gpt10_fck, CK_243X),
|
||||
CLK("omap_timer.11", "fck", &gpt11_fck, CK_243X),
|
||||
CLK("omap_timer.12", "fck", &gpt12_fck, CK_243X),
|
||||
CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),
|
||||
|
||||
@@ -3464,18 +3464,6 @@ static struct omap_clk omap3xxx_clks[] = {
|
||||
CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
|
||||
CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
|
||||
CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
|
||||
CLK("omap_timer.1", "fck", &gpt1_fck, CK_3XXX),
|
||||
CLK("omap_timer.2", "fck", &gpt2_fck, CK_3XXX),
|
||||
CLK("omap_timer.3", "fck", &gpt3_fck, CK_3XXX),
|
||||
CLK("omap_timer.4", "fck", &gpt4_fck, CK_3XXX),
|
||||
CLK("omap_timer.5", "fck", &gpt5_fck, CK_3XXX),
|
||||
CLK("omap_timer.6", "fck", &gpt6_fck, CK_3XXX),
|
||||
CLK("omap_timer.7", "fck", &gpt7_fck, CK_3XXX),
|
||||
CLK("omap_timer.8", "fck", &gpt8_fck, CK_3XXX),
|
||||
CLK("omap_timer.9", "fck", &gpt9_fck, CK_3XXX),
|
||||
CLK("omap_timer.10", "fck", &gpt10_fck, CK_3XXX),
|
||||
CLK("omap_timer.11", "fck", &gpt11_fck, CK_3XXX),
|
||||
CLK("omap_timer.12", "fck", &gpt12_fck, CK_3XXX),
|
||||
CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
|
||||
@@ -8,6 +8,13 @@
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
|
||||
|
||||
/*
|
||||
* OMAP4430_REGM4XEN_MULT: If the CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit is
|
||||
* set, then the DPLL's lock frequency is multiplied by 4 (OMAP4430 TRM
|
||||
* vV Section 3.6.3.3.1 "DPLLs Output Clocks Parameters")
|
||||
*/
|
||||
#define OMAP4430_REGM4XEN_MULT 4
|
||||
|
||||
int omap4xxx_clk_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -270,8 +270,8 @@ static struct clk dpll_abe_ck = {
|
||||
.dpll_data = &dpll_abe_dd,
|
||||
.init = &omap2_init_dpll_parent,
|
||||
.ops = &clkops_omap3_noncore_dpll_ops,
|
||||
.recalc = &omap3_dpll_recalc,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
.recalc = &omap4_dpll_regm4xen_recalc,
|
||||
.round_rate = &omap4_dpll_regm4xen_round_rate,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
};
|
||||
|
||||
@@ -1195,11 +1195,25 @@ static struct clk l4_wkup_clk_mux_ck = {
|
||||
.recalc = &omap2_clksel_recalc,
|
||||
};
|
||||
|
||||
static const struct clksel_rate div2_2to1_rates[] = {
|
||||
{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
|
||||
{ .div = 2, .val = 0, .flags = RATE_IN_4430 },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
static const struct clksel ocp_abe_iclk_div[] = {
|
||||
{ .parent = &aess_fclk, .rates = div2_2to1_rates },
|
||||
{ .parent = NULL },
|
||||
};
|
||||
|
||||
static struct clk ocp_abe_iclk = {
|
||||
.name = "ocp_abe_iclk",
|
||||
.parent = &aess_fclk,
|
||||
.clksel = ocp_abe_iclk_div,
|
||||
.clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
|
||||
.clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
|
||||
.ops = &clkops_null,
|
||||
.recalc = &followparent_recalc,
|
||||
.recalc = &omap2_clksel_recalc,
|
||||
};
|
||||
|
||||
static struct clk per_abe_24m_fclk = {
|
||||
@@ -1398,9 +1412,9 @@ static struct clk dss_dss_clk = {
|
||||
};
|
||||
|
||||
static const struct clksel_rate div3_8to32_rates[] = {
|
||||
{ .div = 8, .val = 0, .flags = RATE_IN_44XX },
|
||||
{ .div = 16, .val = 1, .flags = RATE_IN_44XX },
|
||||
{ .div = 32, .val = 2, .flags = RATE_IN_44XX },
|
||||
{ .div = 8, .val = 0, .flags = RATE_IN_4460 },
|
||||
{ .div = 16, .val = 1, .flags = RATE_IN_4460 },
|
||||
{ .div = 32, .val = 2, .flags = RATE_IN_4460 },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
@@ -3363,17 +3377,6 @@ static struct omap_clk omap44xx_clks[] = {
|
||||
CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
|
||||
CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
|
||||
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap_timer.1", "fck", &timer1_fck, CK_443X),
|
||||
CLK("omap_timer.2", "fck", &timer2_fck, CK_443X),
|
||||
CLK("omap_timer.3", "fck", &timer3_fck, CK_443X),
|
||||
CLK("omap_timer.4", "fck", &timer4_fck, CK_443X),
|
||||
CLK("omap_timer.5", "fck", &timer5_fck, CK_443X),
|
||||
CLK("omap_timer.6", "fck", &timer6_fck, CK_443X),
|
||||
CLK("omap_timer.7", "fck", &timer7_fck, CK_443X),
|
||||
CLK("omap_timer.8", "fck", &timer8_fck, CK_443X),
|
||||
CLK("omap_timer.9", "fck", &timer9_fck, CK_443X),
|
||||
CLK("omap_timer.10", "fck", &timer10_fck, CK_443X),
|
||||
CLK("omap_timer.11", "fck", &timer11_fck, CK_443X),
|
||||
CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
@@ -3403,12 +3406,12 @@ int __init omap4xxx_clk_init(void)
|
||||
struct omap_clk *c;
|
||||
u32 cpu_clkflg;
|
||||
|
||||
if (cpu_is_omap44xx()) {
|
||||
if (cpu_is_omap443x()) {
|
||||
cpu_mask = RATE_IN_4430;
|
||||
cpu_clkflg = CK_443X;
|
||||
} else if (cpu_is_omap446x()) {
|
||||
cpu_mask = RATE_IN_4460;
|
||||
cpu_clkflg = CK_446X;
|
||||
cpu_mask = RATE_IN_4460 | RATE_IN_4430;
|
||||
cpu_clkflg = CK_446X | CK_443X;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -318,18 +318,10 @@ static inline void omap_init_audio(void) {}
|
||||
#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
|
||||
defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
|
||||
|
||||
static struct omap_device_pm_latency omap_mcpdm_latency[] = {
|
||||
{
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
static void omap_init_mcpdm(void)
|
||||
{
|
||||
struct omap_hwmod *oh;
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
|
||||
oh = omap_hwmod_lookup("mcpdm");
|
||||
if (!oh) {
|
||||
@@ -337,11 +329,8 @@ static void omap_init_mcpdm(void)
|
||||
return;
|
||||
}
|
||||
|
||||
od = omap_device_build("omap-mcpdm", -1, oh, NULL, 0,
|
||||
omap_mcpdm_latency,
|
||||
ARRAY_SIZE(omap_mcpdm_latency), 0);
|
||||
if (IS_ERR(od))
|
||||
printk(KERN_ERR "Could not build omap_device for omap-mcpdm-dai\n");
|
||||
pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
|
||||
WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
|
||||
}
|
||||
#else
|
||||
static inline void omap_init_mcpdm(void) {}
|
||||
|
||||
@@ -390,7 +390,8 @@ int omap3_noncore_dpll_enable(struct clk *clk)
|
||||
* propagating?
|
||||
*/
|
||||
if (!r)
|
||||
clk->rate = omap2_get_dpll_rate(clk);
|
||||
clk->rate = (clk->recalc) ? clk->recalc(clk) :
|
||||
omap2_get_dpll_rate(clk);
|
||||
|
||||
return r;
|
||||
}
|
||||
@@ -424,6 +425,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
|
||||
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
struct clk *new_parent = NULL;
|
||||
unsigned long hw_rate;
|
||||
u16 freqsel = 0;
|
||||
struct dpll_data *dd;
|
||||
int ret;
|
||||
@@ -435,7 +437,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
|
||||
if (!dd)
|
||||
return -EINVAL;
|
||||
|
||||
if (rate == omap2_get_dpll_rate(clk))
|
||||
hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
|
||||
if (rate == hw_rate)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
@@ -455,7 +458,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
|
||||
new_parent = dd->clk_bypass;
|
||||
} else {
|
||||
if (dd->last_rounded_rate != rate)
|
||||
omap2_dpll_round_rate(clk, rate);
|
||||
rate = clk->round_rate(clk, rate);
|
||||
|
||||
if (dd->last_rounded_rate == 0)
|
||||
return -EINVAL;
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
#include <plat/clock.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "clock44xx.h"
|
||||
#include "cm-regbits-44xx.h"
|
||||
|
||||
/* Supported only on OMAP4 */
|
||||
@@ -82,3 +83,71 @@ const struct clkops clkops_omap4_dpllmx_ops = {
|
||||
.deny_idle = omap4_dpllmx_deny_gatectrl,
|
||||
};
|
||||
|
||||
/**
|
||||
* omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
|
||||
* @clk: struct clk * of the DPLL to compute the rate for
|
||||
*
|
||||
* Compute the output rate for the OMAP4 DPLL represented by @clk.
|
||||
* Takes the REGM4XEN bit into consideration, which is needed for the
|
||||
* OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
|
||||
* upon success, or 0 upon error.
|
||||
*/
|
||||
unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
|
||||
{
|
||||
u32 v;
|
||||
unsigned long rate;
|
||||
struct dpll_data *dd;
|
||||
|
||||
if (!clk || !clk->dpll_data)
|
||||
return 0;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
rate = omap2_get_dpll_rate(clk);
|
||||
|
||||
/* regm4xen adds a multiplier of 4 to DPLL calculations */
|
||||
v = __raw_readl(dd->control_reg);
|
||||
if (v & OMAP4430_DPLL_REGM4XEN_MASK)
|
||||
rate *= OMAP4430_REGM4XEN_MULT;
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
|
||||
* @clk: struct clk * of the DPLL to round a rate for
|
||||
* @target_rate: the desired rate of the DPLL
|
||||
*
|
||||
* Compute the rate that would be programmed into the DPLL hardware
|
||||
* for @clk if set_rate() were to be provided with the rate
|
||||
* @target_rate. Takes the REGM4XEN bit into consideration, which is
|
||||
* needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
|
||||
* M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
|
||||
* ~0 if an error occurred in omap2_dpll_round_rate().
|
||||
*/
|
||||
long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
|
||||
{
|
||||
u32 v;
|
||||
struct dpll_data *dd;
|
||||
long r;
|
||||
|
||||
if (!clk || !clk->dpll_data)
|
||||
return -EINVAL;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
/* regm4xen adds a multiplier of 4 to DPLL calculations */
|
||||
v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK;
|
||||
|
||||
if (v)
|
||||
target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
|
||||
|
||||
r = omap2_dpll_round_rate(clk, target_rate);
|
||||
if (r == ~0)
|
||||
return r;
|
||||
|
||||
if (v)
|
||||
clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
|
||||
|
||||
return clk->dpll_data->last_rounded_rate;
|
||||
}
|
||||
|
||||
@@ -18,6 +18,7 @@
|
||||
* of the OMAP PM core code.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include "cm2xxx_3xxx.h"
|
||||
#include "prm2xxx_3xxx.h"
|
||||
|
||||
@@ -129,15 +129,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
|
||||
* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
|
||||
* card with Vcc regulator (from twl4030 or whatever). OMAP has both
|
||||
* 1.8V and 3.0V modes, controlled by the PBIAS register.
|
||||
*
|
||||
* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
|
||||
* is most naturally TWL VSIM; those pins also use PBIAS.
|
||||
*
|
||||
* FIXME handle VMMC1A as needed ...
|
||||
*/
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK);
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PBIASLITE_VMODE_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
|
||||
@@ -172,12 +168,6 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
|
||||
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
} else {
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PBIASLITE_VMODE_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -489,7 +479,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
|
||||
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
|
||||
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
|
||||
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
|
||||
reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
|
||||
reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
|
||||
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
|
||||
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_mmc1);
|
||||
|
||||
@@ -187,8 +187,11 @@ static void __init omap3_check_features(void)
|
||||
OMAP3_CHECK_FEATURE(status, ISP);
|
||||
if (cpu_is_omap3630())
|
||||
omap_features |= OMAP3_HAS_192MHZ_CLK;
|
||||
if (!cpu_is_omap3505() && !cpu_is_omap3517())
|
||||
if (cpu_is_omap3430() || cpu_is_omap3630())
|
||||
omap_features |= OMAP3_HAS_IO_WAKEUP;
|
||||
if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
|
||||
omap_rev() == OMAP3430_REV_ES3_1_2)
|
||||
omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
|
||||
|
||||
omap_features |= OMAP3_HAS_SDRC;
|
||||
|
||||
|
||||
@@ -941,10 +941,10 @@
|
||||
#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
|
||||
#define OMAP4_DSI1_LANEENABLE_SHIFT 24
|
||||
#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
|
||||
#define OMAP4_DSI1_PIPD_SHIFT 19
|
||||
#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
|
||||
#define OMAP4_DSI2_PIPD_SHIFT 14
|
||||
#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
|
||||
#define OMAP4_DSI2_PIPD_SHIFT 19
|
||||
#define OMAP4_DSI2_PIPD_MASK (0x1f << 19)
|
||||
#define OMAP4_DSI1_PIPD_SHIFT 14
|
||||
#define OMAP4_DSI1_PIPD_MASK (0x1f << 14)
|
||||
|
||||
/* CONTROL_MCBSPLP */
|
||||
#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
|
||||
|
||||
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Reference in New Issue
Block a user