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Merge tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl changes from Linus Walleij:
"Some of this stuff is hitting arch/arm/* and have been ACKed by the
ARM SoC folks, or it's device tree bindings pertaining to the specific
driver.
These are the bulk pinctrl changes for kernel v3.7:
- Add subdrivers for the DB8540 and NHK8815 Nomadik-type ASICs,
provide platform config for the Nomadik.
- Add a driver for the i.MX35.
- Add a driver for the BCM2835, an advanced GPIO expander.
- Various fixes and clean-ups and minor improvements for the core,
Nomadik, pinctr-single, sirf drivers.
- Some platform config for the ux500."
* tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (27 commits)
pinctrl: add bcm2835 driver
pinctrl: clarify idle vs sleep states
pinctrl/nomadik: use irq_find_mapping()
pinctrl: sirf: add lost chained_irq_enter and exit in sirfsoc_gpio_handle_irq
pinctrl: sirf: initialize the irq_chip pointer of pinctrl_gpio_range
pinctrl: sirf: fix spinlock deadlock in sirfsoc_gpio_set_input
pinctrl: sirf: add missing pins to pinctrl list
pinctrl: sirf: fix a typo in sirfsoc_gpio_probe
pinctrl: pinctrl-single: add debugfs pin h/w state info
ARM: ux500: 8500: update I2C sleep states pinctrl
pinctrl: Fix potential memory leak in pinctrl_register_one_pin()
ARM: ux500: tidy up pin sleep modes
ARM: ux500: fix spi2 pin group
pinctrl: imx: remove duplicated const
pinctrl: document semantics vs GPIO
ARM: ux500: 8500: use hsit_a_2 group for HSI
pinctrl: use kasprintf() in pinmux_request_gpio()
pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux
pinctrl/nomadik : add MC1_a_2 pin MC1 function group list
pinctrl: pinctrl-single: Make sure we do not change bits outside of mask
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,74 @@
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Broadcom BCM2835 GPIO (and pinmux) controller
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The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
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controller, and pinmux/control device.
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Required properties:
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- compatible: "brcm,bcm2835-gpio"
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- reg: Should contain the physical address of the GPIO module's registes.
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters:
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- bit 0 specifies polarity (0 for normal, 1 for inverted)
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- interrupts : The interrupt outputs from the controller. One interrupt per
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individual bank followed by the "all banks" interrupt.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells : Should be 2.
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The first cell is the GPIO number.
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The second cell is used to specify flags:
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bits[3:0] trigger type and level flags:
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1 = low-to-high edge triggered.
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2 = high-to-low edge triggered.
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4 = active high level-sensitive.
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8 = active low level-sensitive.
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Valid combinations are 1, 2, 3, 4, 8.
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Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Each pin configuration node lists the pin(s) to which it applies, and one or
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more of the mux function to select on those pin(s), and pull-up/down
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configuration. Each subnode only affects those parameters that are explicitly
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listed. In other words, a subnode that lists only a mux function implies no
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information about any pull configuration. Similarly, a subnode that lists only
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a pul parameter implies no information about the mux function.
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Required subnode-properties:
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- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
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are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
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Optional subnode-properties:
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- brcm,function: Integer, containing the function to mux to the pin(s):
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0: GPIO in
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1: GPIO out
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2: alt5
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3: alt4
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4: alt0
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5: alt1
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6: alt2
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7: alt3
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- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s):
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0: none
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1: down
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2: up
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Each of brcm,function and brcm,pull may contain either a single value which
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will be applied to all pins in brcm,pins, or 1 value for each entry in
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brcm,pins.
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Example:
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gpio: gpio {
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compatible = "brcm,bcm2835-gpio";
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reg = <0x2200000 0xb4>;
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interrupts = <2 17>, <2 19>, <2 18>, <2 20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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File diff suppressed because it is too large
Load Diff
@@ -14,10 +14,12 @@ Optional properties:
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- pinctrl-single,function-off : function off mode for disabled state if
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available and same for all registers; if not specified, disabling of
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pin functions is ignored
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- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
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more than one pin
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This driver assumes that there is only one register for each pin,
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and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt
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document in this directory.
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This driver assumes that there is only one register for each pin (unless the
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pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
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specified in the pinctrl-bindings.txt document in this directory.
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The pin configuration nodes for pinctrl-single are specified as pinctrl
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register offset and value pairs using pinctrl-single,pins. Only the bits
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@@ -31,6 +33,15 @@ device pinctrl register, and 0x118 contains the desired value of the
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pinctrl register. See the device example and static board pins example
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below for more information.
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In case when one register changes more than one pin's mux the
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pinctrl-single,bits need to be used which takes three parameters:
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pinctrl-single,bits = <0xdc 0x18, 0xff>;
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Where 0xdc is the offset from the pinctrl register base address for the
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device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
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be used when applying this change to the register.
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Example:
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/* SoC common file */
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@@ -55,6 +66,15 @@ pmx_wkup: pinmux@4a31e040 {
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pinctrl-single,function-mask = <0xffff>;
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};
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control_devconf0: pinmux@48002274 {
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compatible = "pinctrl-single";
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reg = <0x48002274 4>; /* Single register */
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x5F>;
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};
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/* board specific .dts file */
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@@ -87,6 +107,21 @@ pmx_wkup: pinmux@4a31e040 {
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};
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};
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&control_devconf0 {
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mcbsp1_pins: pinmux_mcbsp1_pins {
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pinctrl-single,bits = <
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0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
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>;
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};
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mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
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pinctrl-single,bits = <
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0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
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>;
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};
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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@@ -289,6 +289,11 @@ Interaction with the GPIO subsystem
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The GPIO drivers may want to perform operations of various types on the same
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physical pins that are also registered as pin controller pins.
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First and foremost, the two subsystems can be used as completely orthogonal,
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see the section named "pin control requests from drivers" and
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"drivers needing both pin control and GPIOs" below for details. But in some
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situations a cross-subsystem mapping between pins and GPIOs is needed.
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Since the pin controller subsystem have its pinspace local to the pin
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controller we need a mapping so that the pin control subsystem can figure out
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which pin controller handles control of a certain GPIO pin. Since a single
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@@ -359,6 +364,7 @@ will get an pin number into its handled number range. Further it is also passed
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the range ID value, so that the pin controller knows which range it should
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deal with.
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PINMUX interfaces
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=================
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@@ -960,8 +966,8 @@ all get selected, and they all get enabled and disable simultaneously by the
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pinmux core.
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Pinmux requests from drivers
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============================
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Pin control requests from drivers
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=================================
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Generally it is discouraged to let individual drivers get and enable pin
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control. So if possible, handle the pin control in platform code or some other
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@@ -969,6 +975,11 @@ place where you have access to all the affected struct device * pointers. In
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some cases where a driver needs to e.g. switch between different mux mappings
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at runtime this is not possible.
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A typical case is if a driver needs to switch bias of pins from normal
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operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
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PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
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current in sleep mode.
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A driver may request a certain control state to be activated, usually just the
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default state like this:
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@@ -1058,6 +1069,51 @@ registered. Thus make sure that the error path in your driver gracefully
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cleans up and is ready to retry the probing later in the startup process.
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Drivers needing both pin control and GPIOs
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==========================================
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Again, it is discouraged to let drivers lookup and select pin control states
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themselves, but again sometimes this is unavoidable.
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So say that your driver is fetching its resources like this:
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#include <linux/pinctrl/consumer.h>
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#include <linux/gpio.h>
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struct pinctrl *pinctrl;
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int gpio;
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pinctrl = devm_pinctrl_get_select_default(&dev);
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gpio = devm_gpio_request(&dev, 14, "foo");
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Here we first request a certain pin state and then request GPIO 14 to be
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used. If you're using the subsystems orthogonally like this, you should
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nominally always get your pinctrl handle and select the desired pinctrl
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state BEFORE requesting the GPIO. This is a semantic convention to avoid
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situations that can be electrically unpleasant, you will certainly want to
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mux in and bias pins in a certain way before the GPIO subsystems starts to
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deal with them.
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The above can be hidden: using pinctrl hogs, the pin control driver may be
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setting up the config and muxing for the pins when it is probing,
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nevertheless orthogonal to the GPIO subsystem.
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But there are also situations where it makes sense for the GPIO subsystem
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to communicate directly with with the pinctrl subsystem, using the latter
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as a back-end. This is when the GPIO driver may call out to the functions
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described in the section "Pin control interaction with the GPIO subsystem"
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above. This only involves per-pin multiplexing, and will be completely
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hidden behind the gpio_*() function namespace. In this case, the driver
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need not interact with the pin control subsystem at all.
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If a pin control driver and a GPIO driver is dealing with the same pins
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and the use cases involve multiplexing, you MUST implement the pin controller
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as a back-end for the GPIO driver like this, unless your hardware design
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is such that the GPIO controller can override the pin controller's
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multiplexing state through hardware without the need to interact with the
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pin control system.
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System pin control hogging
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==========================
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@@ -891,6 +891,7 @@ config ARCH_NOMADIK
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select COMMON_CLK
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select GENERIC_CLOCKEVENTS
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select PINCTRL
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select PINCTRL_STN8815
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select MIGHT_HAVE_CACHE_L2X0
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select ARCH_REQUIRE_GPIOLIB
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help
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@@ -23,6 +23,7 @@
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#include <linux/mtd/partitions.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/pinctrl/machine.h>
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#include <asm/hardware/vic.h>
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#include <asm/sizes.h>
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#include <asm/mach-types.h>
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@@ -33,6 +34,7 @@
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#include <plat/gpio-nomadik.h>
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#include <plat/mtu.h>
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#include <plat/pincfg.h>
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#include <linux/platform_data/mtd-nomadik-nand.h>
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#include <mach/fsmc.h>
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@@ -290,8 +292,42 @@ static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
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},
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};
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static unsigned long out_low[] = { PIN_OUTPUT_LOW };
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static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
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static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
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static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
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static struct pinctrl_map __initdata nhk8815_pinmap[] = {
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PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
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PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
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/* Hog in MMC/SD card mux */
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PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
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/* MCCLK */
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
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/* MCCMD */
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
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/* MCCMDDIR */
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
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/* MCDAT3-0 */
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
|
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
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/* MCDAT0DIR */
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
|
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/* MCDAT31DIR */
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
|
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/* MCMSFBCLK */
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
|
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/* CD input GPIO */
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
|
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/* CD bias drive */
|
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PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
|
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};
|
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static void __init nhk8815_platform_init(void)
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{
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pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
|
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cpu8815_platform_init();
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nhk8815_onenand_init();
|
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platform_add_devices(nhk8815_platform_devices,
|
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|
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@@ -83,6 +83,18 @@ void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
|
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}
|
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}
|
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|
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static inline void
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cpu8815_add_pinctrl(struct device *parent, const char *name)
|
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{
|
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struct platform_device_info pdevinfo = {
|
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.parent = parent,
|
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.name = name,
|
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.id = -1,
|
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};
|
||||
|
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platform_device_register_full(&pdevinfo);
|
||||
}
|
||||
|
||||
static int __init cpu8815_init(void)
|
||||
{
|
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struct nmk_gpio_platform_data pdata = {
|
||||
@@ -91,6 +103,7 @@ static int __init cpu8815_init(void)
|
||||
|
||||
cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
|
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IRQ_GPIO0, &pdata);
|
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cpu8815_add_pinctrl(NULL, "pinctrl-stn8815");
|
||||
amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
|
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amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
|
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return 0;
|
||||
|
||||
@@ -30,16 +30,15 @@ static enum custom_pin_cfg_t pinsfor;
|
||||
#define BIAS(a,b) static unsigned long a[] = { b }
|
||||
|
||||
BIAS(pd, PIN_PULL_DOWN);
|
||||
BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
|
||||
BIAS(in_nopull, PIN_INPUT_NOPULL);
|
||||
BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
|
||||
BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
|
||||
BIAS(in_pu, PIN_INPUT_PULLUP);
|
||||
BIAS(in_pd, PIN_INPUT_PULLDOWN);
|
||||
BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
|
||||
BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
|
||||
BIAS(out_hi, PIN_OUTPUT_HIGH);
|
||||
BIAS(out_lo, PIN_OUTPUT_LOW);
|
||||
BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
|
||||
BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
|
||||
/* These also force them into GPIO mode */
|
||||
BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
|
||||
@@ -48,23 +47,32 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL
|
||||
BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
|
||||
/* Sleep modes */
|
||||
BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
|
||||
BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
|
||||
BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
|
||||
BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
|
||||
BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
|
||||
/* We use these to define hog settings that are always done on boot */
|
||||
#define DB8500_MUX_HOG(group,func) \
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
|
||||
#define DB8500_PIN_HOG(pin,conf) \
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
|
||||
#define DB8500_PIN_SLEEP(pin, conf, dev) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
|
||||
pin, conf)
|
||||
|
||||
/* These are default states associated with device and changed runtime */
|
||||
#define DB8500_MUX(group,func,dev) \
|
||||
PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
|
||||
#define DB8500_PIN(pin,conf,dev) \
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
|
||||
#define DB8500_PIN_SLEEP(pin, conf, dev) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
|
||||
pin, conf)
|
||||
|
||||
#define DB8500_PIN_SLEEP(pin,conf,dev) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
|
||||
@@ -134,40 +142,47 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
|
||||
DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
|
||||
DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
|
||||
/* UART0 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
|
||||
/* MSP1 for ALSA codec */
|
||||
DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
|
||||
DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
/* MSP1 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
/* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
|
||||
DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
|
||||
DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
|
||||
/* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
|
||||
DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
|
||||
/* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
|
||||
/* Mux in i2c0 block, default state */
|
||||
DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
|
||||
DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
|
||||
DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
|
||||
/* i2c0 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
|
||||
/* Mux in i2c1 block, default state */
|
||||
DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
|
||||
DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
|
||||
DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
|
||||
/* i2c1 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
|
||||
/* Mux in i2c2 block, default state */
|
||||
DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
|
||||
DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
|
||||
DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
|
||||
/* i2c2 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
|
||||
/* Mux in i2c3 block, default state */
|
||||
DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
|
||||
DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
|
||||
DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
|
||||
/* i2c3 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
|
||||
/* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
|
||||
DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
|
||||
DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
|
||||
@@ -219,11 +234,15 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
|
||||
DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
|
||||
DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
|
||||
/* Mux in SPI2 pins on the "other C1" altfunction */
|
||||
DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
|
||||
DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
|
||||
DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
|
||||
DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
|
||||
DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
|
||||
DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
|
||||
/* SPI2 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
|
||||
DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
|
||||
DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -410,7 +429,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = {
|
||||
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
|
||||
/* HSI */
|
||||
DB8500_MUX_HOG("hsir_a_1", "hsi"),
|
||||
DB8500_MUX_HOG("hsit_a_1", "hsi"),
|
||||
DB8500_MUX_HOG("hsit_a_2", "hsi"),
|
||||
DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
|
||||
DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
|
||||
DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
|
||||
@@ -418,7 +437,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = {
|
||||
DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
|
||||
DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
|
||||
DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
|
||||
DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
|
||||
DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
|
||||
};
|
||||
|
||||
static struct pinctrl_map __initdata u8500_pinmap[] = {
|
||||
|
||||
@@ -26,11 +26,24 @@ config DEBUG_PINCTRL
|
||||
help
|
||||
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
|
||||
|
||||
config PINCTRL_BCM2835
|
||||
bool
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_IMX
|
||||
bool
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_IMX35
|
||||
bool "IMX35 pinctrl driver"
|
||||
depends on OF
|
||||
depends on SOC_IMX35
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx35 pinctrl driver
|
||||
|
||||
config PINCTRL_IMX51
|
||||
bool "IMX51 pinctrl driver"
|
||||
depends on OF
|
||||
@@ -86,10 +99,18 @@ config PINCTRL_NOMADIK
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_STN8815
|
||||
bool "STN8815 pin controller driver"
|
||||
depends on PINCTRL_NOMADIK && ARCH_NOMADIK
|
||||
|
||||
config PINCTRL_DB8500
|
||||
bool "DB8500 pin controller driver"
|
||||
depends on PINCTRL_NOMADIK && ARCH_U8500
|
||||
|
||||
config PINCTRL_DB8540
|
||||
bool "DB8540 pin controller driver"
|
||||
depends on PINCTRL_NOMADIK && ARCH_U8500
|
||||
|
||||
config PINCTRL_PXA168
|
||||
bool "PXA168 pin controller driver"
|
||||
depends on ARCH_MMP
|
||||
|
||||
@@ -9,7 +9,9 @@ ifeq ($(CONFIG_OF),y)
|
||||
obj-$(CONFIG_PINCTRL) += devicetree.o
|
||||
endif
|
||||
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
|
||||
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
|
||||
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
|
||||
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
|
||||
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
|
||||
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
|
||||
@@ -19,7 +21,9 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
|
||||
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
|
||||
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
|
||||
obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
|
||||
obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
|
||||
obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
|
||||
obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
|
||||
obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
|
||||
obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
|
||||
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
|
||||
|
||||
@@ -230,8 +230,10 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
|
||||
pindesc->name = name;
|
||||
} else {
|
||||
pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", number);
|
||||
if (pindesc->name == NULL)
|
||||
if (pindesc->name == NULL) {
|
||||
kfree(pindesc);
|
||||
return -ENOMEM;
|
||||
}
|
||||
pindesc->dynamic_name = true;
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -432,7 +432,7 @@ static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
|
||||
{
|
||||
unsigned int pin_func_id;
|
||||
int ret, size;
|
||||
const const __be32 *list;
|
||||
const __be32 *list;
|
||||
int i, j;
|
||||
u32 config;
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
+245
-245
@@ -23,251 +23,251 @@
|
||||
#include "pinctrl-imx.h"
|
||||
|
||||
enum imx51_pads {
|
||||
MX51_PAD_EIM_D16 = 1,
|
||||
MX51_PAD_EIM_D17 = 2,
|
||||
MX51_PAD_EIM_D18 = 3,
|
||||
MX51_PAD_EIM_D19 = 4,
|
||||
MX51_PAD_EIM_D20 = 5,
|
||||
MX51_PAD_EIM_D21 = 6,
|
||||
MX51_PAD_EIM_D22 = 7,
|
||||
MX51_PAD_EIM_D23 = 8,
|
||||
MX51_PAD_EIM_D24 = 9,
|
||||
MX51_PAD_EIM_D25 = 10,
|
||||
MX51_PAD_EIM_D26 = 11,
|
||||
MX51_PAD_EIM_D27 = 12,
|
||||
MX51_PAD_EIM_D28 = 13,
|
||||
MX51_PAD_EIM_D29 = 14,
|
||||
MX51_PAD_EIM_D30 = 15,
|
||||
MX51_PAD_EIM_D31 = 16,
|
||||
MX51_PAD_EIM_A16 = 17,
|
||||
MX51_PAD_EIM_A17 = 18,
|
||||
MX51_PAD_EIM_A18 = 19,
|
||||
MX51_PAD_EIM_A19 = 20,
|
||||
MX51_PAD_EIM_A20 = 21,
|
||||
MX51_PAD_EIM_A21 = 22,
|
||||
MX51_PAD_EIM_A22 = 23,
|
||||
MX51_PAD_EIM_A23 = 24,
|
||||
MX51_PAD_EIM_A24 = 25,
|
||||
MX51_PAD_EIM_A25 = 26,
|
||||
MX51_PAD_EIM_A26 = 27,
|
||||
MX51_PAD_EIM_A27 = 28,
|
||||
MX51_PAD_EIM_EB0 = 29,
|
||||
MX51_PAD_EIM_EB1 = 30,
|
||||
MX51_PAD_EIM_EB2 = 31,
|
||||
MX51_PAD_EIM_EB3 = 32,
|
||||
MX51_PAD_EIM_OE = 33,
|
||||
MX51_PAD_EIM_CS0 = 34,
|
||||
MX51_PAD_EIM_CS1 = 35,
|
||||
MX51_PAD_EIM_CS2 = 36,
|
||||
MX51_PAD_EIM_CS3 = 37,
|
||||
MX51_PAD_EIM_CS4 = 38,
|
||||
MX51_PAD_EIM_CS5 = 39,
|
||||
MX51_PAD_EIM_DTACK = 40,
|
||||
MX51_PAD_EIM_LBA = 41,
|
||||
MX51_PAD_EIM_CRE = 42,
|
||||
MX51_PAD_DRAM_CS1 = 43,
|
||||
MX51_PAD_NANDF_WE_B = 44,
|
||||
MX51_PAD_NANDF_RE_B = 45,
|
||||
MX51_PAD_NANDF_ALE = 46,
|
||||
MX51_PAD_NANDF_CLE = 47,
|
||||
MX51_PAD_NANDF_WP_B = 48,
|
||||
MX51_PAD_NANDF_RB0 = 49,
|
||||
MX51_PAD_NANDF_RB1 = 50,
|
||||
MX51_PAD_NANDF_RB2 = 51,
|
||||
MX51_PAD_NANDF_RB3 = 52,
|
||||
MX51_PAD_GPIO_NAND = 53,
|
||||
MX51_PAD_NANDF_CS0 = 54,
|
||||
MX51_PAD_NANDF_CS1 = 55,
|
||||
MX51_PAD_NANDF_CS2 = 56,
|
||||
MX51_PAD_NANDF_CS3 = 57,
|
||||
MX51_PAD_NANDF_CS4 = 58,
|
||||
MX51_PAD_NANDF_CS5 = 59,
|
||||
MX51_PAD_NANDF_CS6 = 60,
|
||||
MX51_PAD_NANDF_CS7 = 61,
|
||||
MX51_PAD_NANDF_RDY_INT = 62,
|
||||
MX51_PAD_NANDF_D15 = 63,
|
||||
MX51_PAD_NANDF_D14 = 64,
|
||||
MX51_PAD_NANDF_D13 = 65,
|
||||
MX51_PAD_NANDF_D12 = 66,
|
||||
MX51_PAD_NANDF_D11 = 67,
|
||||
MX51_PAD_NANDF_D10 = 68,
|
||||
MX51_PAD_NANDF_D9 = 69,
|
||||
MX51_PAD_NANDF_D8 = 70,
|
||||
MX51_PAD_NANDF_D7 = 71,
|
||||
MX51_PAD_NANDF_D6 = 72,
|
||||
MX51_PAD_NANDF_D5 = 73,
|
||||
MX51_PAD_NANDF_D4 = 74,
|
||||
MX51_PAD_NANDF_D3 = 75,
|
||||
MX51_PAD_NANDF_D2 = 76,
|
||||
MX51_PAD_NANDF_D1 = 77,
|
||||
MX51_PAD_NANDF_D0 = 78,
|
||||
MX51_PAD_CSI1_D8 = 79,
|
||||
MX51_PAD_CSI1_D9 = 80,
|
||||
MX51_PAD_CSI1_D10 = 81,
|
||||
MX51_PAD_CSI1_D11 = 82,
|
||||
MX51_PAD_CSI1_D12 = 83,
|
||||
MX51_PAD_CSI1_D13 = 84,
|
||||
MX51_PAD_CSI1_D14 = 85,
|
||||
MX51_PAD_CSI1_D15 = 86,
|
||||
MX51_PAD_CSI1_D16 = 87,
|
||||
MX51_PAD_CSI1_D17 = 88,
|
||||
MX51_PAD_CSI1_D18 = 89,
|
||||
MX51_PAD_CSI1_D19 = 90,
|
||||
MX51_PAD_CSI1_VSYNC = 91,
|
||||
MX51_PAD_CSI1_HSYNC = 92,
|
||||
MX51_PAD_CSI1_PIXCLK = 93,
|
||||
MX51_PAD_CSI1_MCLK = 94,
|
||||
MX51_PAD_CSI2_D12 = 95,
|
||||
MX51_PAD_CSI2_D13 = 96,
|
||||
MX51_PAD_CSI2_D14 = 97,
|
||||
MX51_PAD_CSI2_D15 = 98,
|
||||
MX51_PAD_CSI2_D16 = 99,
|
||||
MX51_PAD_CSI2_D17 = 100,
|
||||
MX51_PAD_CSI2_D18 = 101,
|
||||
MX51_PAD_CSI2_D19 = 102,
|
||||
MX51_PAD_CSI2_VSYNC = 103,
|
||||
MX51_PAD_CSI2_HSYNC = 104,
|
||||
MX51_PAD_CSI2_PIXCLK = 105,
|
||||
MX51_PAD_I2C1_CLK = 106,
|
||||
MX51_PAD_I2C1_DAT = 107,
|
||||
MX51_PAD_AUD3_BB_TXD = 108,
|
||||
MX51_PAD_AUD3_BB_RXD = 109,
|
||||
MX51_PAD_AUD3_BB_CK = 110,
|
||||
MX51_PAD_AUD3_BB_FS = 111,
|
||||
MX51_PAD_CSPI1_MOSI = 112,
|
||||
MX51_PAD_CSPI1_MISO = 113,
|
||||
MX51_PAD_CSPI1_SS0 = 114,
|
||||
MX51_PAD_CSPI1_SS1 = 115,
|
||||
MX51_PAD_CSPI1_RDY = 116,
|
||||
MX51_PAD_CSPI1_SCLK = 117,
|
||||
MX51_PAD_UART1_RXD = 118,
|
||||
MX51_PAD_UART1_TXD = 119,
|
||||
MX51_PAD_UART1_RTS = 120,
|
||||
MX51_PAD_UART1_CTS = 121,
|
||||
MX51_PAD_UART2_RXD = 122,
|
||||
MX51_PAD_UART2_TXD = 123,
|
||||
MX51_PAD_UART3_RXD = 124,
|
||||
MX51_PAD_UART3_TXD = 125,
|
||||
MX51_PAD_OWIRE_LINE = 126,
|
||||
MX51_PAD_KEY_ROW0 = 127,
|
||||
MX51_PAD_KEY_ROW1 = 128,
|
||||
MX51_PAD_KEY_ROW2 = 129,
|
||||
MX51_PAD_KEY_ROW3 = 130,
|
||||
MX51_PAD_KEY_COL0 = 131,
|
||||
MX51_PAD_KEY_COL1 = 132,
|
||||
MX51_PAD_KEY_COL2 = 133,
|
||||
MX51_PAD_KEY_COL3 = 134,
|
||||
MX51_PAD_KEY_COL4 = 135,
|
||||
MX51_PAD_KEY_COL5 = 136,
|
||||
MX51_PAD_USBH1_CLK = 137,
|
||||
MX51_PAD_USBH1_DIR = 138,
|
||||
MX51_PAD_USBH1_STP = 139,
|
||||
MX51_PAD_USBH1_NXT = 140,
|
||||
MX51_PAD_USBH1_DATA0 = 141,
|
||||
MX51_PAD_USBH1_DATA1 = 142,
|
||||
MX51_PAD_USBH1_DATA2 = 143,
|
||||
MX51_PAD_USBH1_DATA3 = 144,
|
||||
MX51_PAD_USBH1_DATA4 = 145,
|
||||
MX51_PAD_USBH1_DATA5 = 146,
|
||||
MX51_PAD_USBH1_DATA6 = 147,
|
||||
MX51_PAD_USBH1_DATA7 = 148,
|
||||
MX51_PAD_DI1_PIN11 = 149,
|
||||
MX51_PAD_DI1_PIN12 = 150,
|
||||
MX51_PAD_DI1_PIN13 = 151,
|
||||
MX51_PAD_DI1_D0_CS = 152,
|
||||
MX51_PAD_DI1_D1_CS = 153,
|
||||
MX51_PAD_DISPB2_SER_DIN = 154,
|
||||
MX51_PAD_DISPB2_SER_DIO = 155,
|
||||
MX51_PAD_DISPB2_SER_CLK = 156,
|
||||
MX51_PAD_DISPB2_SER_RS = 157,
|
||||
MX51_PAD_DISP1_DAT0 = 158,
|
||||
MX51_PAD_DISP1_DAT1 = 159,
|
||||
MX51_PAD_DISP1_DAT2 = 160,
|
||||
MX51_PAD_DISP1_DAT3 = 161,
|
||||
MX51_PAD_DISP1_DAT4 = 162,
|
||||
MX51_PAD_DISP1_DAT5 = 163,
|
||||
MX51_PAD_DISP1_DAT6 = 164,
|
||||
MX51_PAD_DISP1_DAT7 = 165,
|
||||
MX51_PAD_DISP1_DAT8 = 166,
|
||||
MX51_PAD_DISP1_DAT9 = 167,
|
||||
MX51_PAD_DISP1_DAT10 = 168,
|
||||
MX51_PAD_DISP1_DAT11 = 169,
|
||||
MX51_PAD_DISP1_DAT12 = 170,
|
||||
MX51_PAD_DISP1_DAT13 = 171,
|
||||
MX51_PAD_DISP1_DAT14 = 172,
|
||||
MX51_PAD_DISP1_DAT15 = 173,
|
||||
MX51_PAD_DISP1_DAT16 = 174,
|
||||
MX51_PAD_DISP1_DAT17 = 175,
|
||||
MX51_PAD_DISP1_DAT18 = 176,
|
||||
MX51_PAD_DISP1_DAT19 = 177,
|
||||
MX51_PAD_DISP1_DAT20 = 178,
|
||||
MX51_PAD_DISP1_DAT21 = 179,
|
||||
MX51_PAD_DISP1_DAT22 = 180,
|
||||
MX51_PAD_DISP1_DAT23 = 181,
|
||||
MX51_PAD_DI1_PIN3 = 182,
|
||||
MX51_PAD_DI1_PIN2 = 183,
|
||||
MX51_PAD_DI_GP2 = 184,
|
||||
MX51_PAD_DI_GP3 = 185,
|
||||
MX51_PAD_DI2_PIN4 = 186,
|
||||
MX51_PAD_DI2_PIN2 = 187,
|
||||
MX51_PAD_DI2_PIN3 = 188,
|
||||
MX51_PAD_DI2_DISP_CLK = 189,
|
||||
MX51_PAD_DI_GP4 = 190,
|
||||
MX51_PAD_DISP2_DAT0 = 191,
|
||||
MX51_PAD_DISP2_DAT1 = 192,
|
||||
MX51_PAD_DISP2_DAT2 = 193,
|
||||
MX51_PAD_DISP2_DAT3 = 194,
|
||||
MX51_PAD_DISP2_DAT4 = 195,
|
||||
MX51_PAD_DISP2_DAT5 = 196,
|
||||
MX51_PAD_DISP2_DAT6 = 197,
|
||||
MX51_PAD_DISP2_DAT7 = 198,
|
||||
MX51_PAD_DISP2_DAT8 = 199,
|
||||
MX51_PAD_DISP2_DAT9 = 200,
|
||||
MX51_PAD_DISP2_DAT10 = 201,
|
||||
MX51_PAD_DISP2_DAT11 = 202,
|
||||
MX51_PAD_DISP2_DAT12 = 203,
|
||||
MX51_PAD_DISP2_DAT13 = 204,
|
||||
MX51_PAD_DISP2_DAT14 = 205,
|
||||
MX51_PAD_DISP2_DAT15 = 206,
|
||||
MX51_PAD_SD1_CMD = 207,
|
||||
MX51_PAD_SD1_CLK = 208,
|
||||
MX51_PAD_SD1_DATA0 = 209,
|
||||
MX51_PAD_EIM_DA0 = 210,
|
||||
MX51_PAD_EIM_DA1 = 211,
|
||||
MX51_PAD_EIM_DA2 = 212,
|
||||
MX51_PAD_EIM_DA3 = 213,
|
||||
MX51_PAD_SD1_DATA1 = 214,
|
||||
MX51_PAD_EIM_DA4 = 215,
|
||||
MX51_PAD_EIM_DA5 = 216,
|
||||
MX51_PAD_EIM_DA6 = 217,
|
||||
MX51_PAD_EIM_DA7 = 218,
|
||||
MX51_PAD_SD1_DATA2 = 219,
|
||||
MX51_PAD_EIM_DA10 = 220,
|
||||
MX51_PAD_EIM_DA11 = 221,
|
||||
MX51_PAD_EIM_DA8 = 222,
|
||||
MX51_PAD_EIM_DA9 = 223,
|
||||
MX51_PAD_SD1_DATA3 = 224,
|
||||
MX51_PAD_GPIO1_0 = 225,
|
||||
MX51_PAD_GPIO1_1 = 226,
|
||||
MX51_PAD_EIM_DA12 = 227,
|
||||
MX51_PAD_EIM_DA13 = 228,
|
||||
MX51_PAD_EIM_DA14 = 229,
|
||||
MX51_PAD_EIM_DA15 = 230,
|
||||
MX51_PAD_SD2_CMD = 231,
|
||||
MX51_PAD_SD2_CLK = 232,
|
||||
MX51_PAD_SD2_DATA0 = 233,
|
||||
MX51_PAD_SD2_DATA1 = 234,
|
||||
MX51_PAD_SD2_DATA2 = 235,
|
||||
MX51_PAD_SD2_DATA3 = 236,
|
||||
MX51_PAD_GPIO1_2 = 237,
|
||||
MX51_PAD_GPIO1_3 = 238,
|
||||
MX51_PAD_PMIC_INT_REQ = 239,
|
||||
MX51_PAD_GPIO1_4 = 240,
|
||||
MX51_PAD_GPIO1_5 = 241,
|
||||
MX51_PAD_GPIO1_6 = 242,
|
||||
MX51_PAD_GPIO1_7 = 243,
|
||||
MX51_PAD_GPIO1_8 = 244,
|
||||
MX51_PAD_GPIO1_9 = 245,
|
||||
MX51_PAD_EIM_D16 = 0,
|
||||
MX51_PAD_EIM_D17 = 1,
|
||||
MX51_PAD_EIM_D18 = 2,
|
||||
MX51_PAD_EIM_D19 = 3,
|
||||
MX51_PAD_EIM_D20 = 4,
|
||||
MX51_PAD_EIM_D21 = 5,
|
||||
MX51_PAD_EIM_D22 = 6,
|
||||
MX51_PAD_EIM_D23 = 7,
|
||||
MX51_PAD_EIM_D24 = 8,
|
||||
MX51_PAD_EIM_D25 = 9,
|
||||
MX51_PAD_EIM_D26 = 10,
|
||||
MX51_PAD_EIM_D27 = 11,
|
||||
MX51_PAD_EIM_D28 = 12,
|
||||
MX51_PAD_EIM_D29 = 13,
|
||||
MX51_PAD_EIM_D30 = 14,
|
||||
MX51_PAD_EIM_D31 = 15,
|
||||
MX51_PAD_EIM_A16 = 16,
|
||||
MX51_PAD_EIM_A17 = 17,
|
||||
MX51_PAD_EIM_A18 = 18,
|
||||
MX51_PAD_EIM_A19 = 19,
|
||||
MX51_PAD_EIM_A20 = 20,
|
||||
MX51_PAD_EIM_A21 = 21,
|
||||
MX51_PAD_EIM_A22 = 22,
|
||||
MX51_PAD_EIM_A23 = 23,
|
||||
MX51_PAD_EIM_A24 = 24,
|
||||
MX51_PAD_EIM_A25 = 25,
|
||||
MX51_PAD_EIM_A26 = 26,
|
||||
MX51_PAD_EIM_A27 = 27,
|
||||
MX51_PAD_EIM_EB0 = 28,
|
||||
MX51_PAD_EIM_EB1 = 29,
|
||||
MX51_PAD_EIM_EB2 = 30,
|
||||
MX51_PAD_EIM_EB3 = 31,
|
||||
MX51_PAD_EIM_OE = 32,
|
||||
MX51_PAD_EIM_CS0 = 33,
|
||||
MX51_PAD_EIM_CS1 = 34,
|
||||
MX51_PAD_EIM_CS2 = 35,
|
||||
MX51_PAD_EIM_CS3 = 36,
|
||||
MX51_PAD_EIM_CS4 = 37,
|
||||
MX51_PAD_EIM_CS5 = 38,
|
||||
MX51_PAD_EIM_DTACK = 39,
|
||||
MX51_PAD_EIM_LBA = 40,
|
||||
MX51_PAD_EIM_CRE = 41,
|
||||
MX51_PAD_DRAM_CS1 = 42,
|
||||
MX51_PAD_NANDF_WE_B = 43,
|
||||
MX51_PAD_NANDF_RE_B = 44,
|
||||
MX51_PAD_NANDF_ALE = 45,
|
||||
MX51_PAD_NANDF_CLE = 46,
|
||||
MX51_PAD_NANDF_WP_B = 47,
|
||||
MX51_PAD_NANDF_RB0 = 48,
|
||||
MX51_PAD_NANDF_RB1 = 49,
|
||||
MX51_PAD_NANDF_RB2 = 50,
|
||||
MX51_PAD_NANDF_RB3 = 51,
|
||||
MX51_PAD_GPIO_NAND = 52,
|
||||
MX51_PAD_NANDF_CS0 = 53,
|
||||
MX51_PAD_NANDF_CS1 = 54,
|
||||
MX51_PAD_NANDF_CS2 = 55,
|
||||
MX51_PAD_NANDF_CS3 = 56,
|
||||
MX51_PAD_NANDF_CS4 = 57,
|
||||
MX51_PAD_NANDF_CS5 = 58,
|
||||
MX51_PAD_NANDF_CS6 = 59,
|
||||
MX51_PAD_NANDF_CS7 = 60,
|
||||
MX51_PAD_NANDF_RDY_INT = 61,
|
||||
MX51_PAD_NANDF_D15 = 62,
|
||||
MX51_PAD_NANDF_D14 = 63,
|
||||
MX51_PAD_NANDF_D13 = 64,
|
||||
MX51_PAD_NANDF_D12 = 65,
|
||||
MX51_PAD_NANDF_D11 = 66,
|
||||
MX51_PAD_NANDF_D10 = 67,
|
||||
MX51_PAD_NANDF_D9 = 68,
|
||||
MX51_PAD_NANDF_D8 = 69,
|
||||
MX51_PAD_NANDF_D7 = 70,
|
||||
MX51_PAD_NANDF_D6 = 71,
|
||||
MX51_PAD_NANDF_D5 = 72,
|
||||
MX51_PAD_NANDF_D4 = 73,
|
||||
MX51_PAD_NANDF_D3 = 74,
|
||||
MX51_PAD_NANDF_D2 = 75,
|
||||
MX51_PAD_NANDF_D1 = 76,
|
||||
MX51_PAD_NANDF_D0 = 77,
|
||||
MX51_PAD_CSI1_D8 = 78,
|
||||
MX51_PAD_CSI1_D9 = 79,
|
||||
MX51_PAD_CSI1_D10 = 80,
|
||||
MX51_PAD_CSI1_D11 = 81,
|
||||
MX51_PAD_CSI1_D12 = 82,
|
||||
MX51_PAD_CSI1_D13 = 83,
|
||||
MX51_PAD_CSI1_D14 = 84,
|
||||
MX51_PAD_CSI1_D15 = 85,
|
||||
MX51_PAD_CSI1_D16 = 86,
|
||||
MX51_PAD_CSI1_D17 = 87,
|
||||
MX51_PAD_CSI1_D18 = 88,
|
||||
MX51_PAD_CSI1_D19 = 89,
|
||||
MX51_PAD_CSI1_VSYNC = 90,
|
||||
MX51_PAD_CSI1_HSYNC = 91,
|
||||
MX51_PAD_CSI1_PIXCLK = 92,
|
||||
MX51_PAD_CSI1_MCLK = 93,
|
||||
MX51_PAD_CSI2_D12 = 94,
|
||||
MX51_PAD_CSI2_D13 = 95,
|
||||
MX51_PAD_CSI2_D14 = 96,
|
||||
MX51_PAD_CSI2_D15 = 97,
|
||||
MX51_PAD_CSI2_D16 = 98,
|
||||
MX51_PAD_CSI2_D17 = 99,
|
||||
MX51_PAD_CSI2_D18 = 100,
|
||||
MX51_PAD_CSI2_D19 = 101,
|
||||
MX51_PAD_CSI2_VSYNC = 102,
|
||||
MX51_PAD_CSI2_HSYNC = 103,
|
||||
MX51_PAD_CSI2_PIXCLK = 104,
|
||||
MX51_PAD_I2C1_CLK = 105,
|
||||
MX51_PAD_I2C1_DAT = 106,
|
||||
MX51_PAD_AUD3_BB_TXD = 107,
|
||||
MX51_PAD_AUD3_BB_RXD = 108,
|
||||
MX51_PAD_AUD3_BB_CK = 109,
|
||||
MX51_PAD_AUD3_BB_FS = 110,
|
||||
MX51_PAD_CSPI1_MOSI = 111,
|
||||
MX51_PAD_CSPI1_MISO = 112,
|
||||
MX51_PAD_CSPI1_SS0 = 113,
|
||||
MX51_PAD_CSPI1_SS1 = 114,
|
||||
MX51_PAD_CSPI1_RDY = 115,
|
||||
MX51_PAD_CSPI1_SCLK = 116,
|
||||
MX51_PAD_UART1_RXD = 117,
|
||||
MX51_PAD_UART1_TXD = 118,
|
||||
MX51_PAD_UART1_RTS = 119,
|
||||
MX51_PAD_UART1_CTS = 120,
|
||||
MX51_PAD_UART2_RXD = 121,
|
||||
MX51_PAD_UART2_TXD = 122,
|
||||
MX51_PAD_UART3_RXD = 123,
|
||||
MX51_PAD_UART3_TXD = 124,
|
||||
MX51_PAD_OWIRE_LINE = 125,
|
||||
MX51_PAD_KEY_ROW0 = 126,
|
||||
MX51_PAD_KEY_ROW1 = 127,
|
||||
MX51_PAD_KEY_ROW2 = 128,
|
||||
MX51_PAD_KEY_ROW3 = 129,
|
||||
MX51_PAD_KEY_COL0 = 130,
|
||||
MX51_PAD_KEY_COL1 = 131,
|
||||
MX51_PAD_KEY_COL2 = 132,
|
||||
MX51_PAD_KEY_COL3 = 133,
|
||||
MX51_PAD_KEY_COL4 = 134,
|
||||
MX51_PAD_KEY_COL5 = 135,
|
||||
MX51_PAD_USBH1_CLK = 136,
|
||||
MX51_PAD_USBH1_DIR = 137,
|
||||
MX51_PAD_USBH1_STP = 138,
|
||||
MX51_PAD_USBH1_NXT = 139,
|
||||
MX51_PAD_USBH1_DATA0 = 140,
|
||||
MX51_PAD_USBH1_DATA1 = 141,
|
||||
MX51_PAD_USBH1_DATA2 = 142,
|
||||
MX51_PAD_USBH1_DATA3 = 143,
|
||||
MX51_PAD_USBH1_DATA4 = 144,
|
||||
MX51_PAD_USBH1_DATA5 = 145,
|
||||
MX51_PAD_USBH1_DATA6 = 146,
|
||||
MX51_PAD_USBH1_DATA7 = 147,
|
||||
MX51_PAD_DI1_PIN11 = 148,
|
||||
MX51_PAD_DI1_PIN12 = 149,
|
||||
MX51_PAD_DI1_PIN13 = 150,
|
||||
MX51_PAD_DI1_D0_CS = 151,
|
||||
MX51_PAD_DI1_D1_CS = 152,
|
||||
MX51_PAD_DISPB2_SER_DIN = 153,
|
||||
MX51_PAD_DISPB2_SER_DIO = 154,
|
||||
MX51_PAD_DISPB2_SER_CLK = 155,
|
||||
MX51_PAD_DISPB2_SER_RS = 156,
|
||||
MX51_PAD_DISP1_DAT0 = 157,
|
||||
MX51_PAD_DISP1_DAT1 = 158,
|
||||
MX51_PAD_DISP1_DAT2 = 159,
|
||||
MX51_PAD_DISP1_DAT3 = 160,
|
||||
MX51_PAD_DISP1_DAT4 = 161,
|
||||
MX51_PAD_DISP1_DAT5 = 162,
|
||||
MX51_PAD_DISP1_DAT6 = 163,
|
||||
MX51_PAD_DISP1_DAT7 = 164,
|
||||
MX51_PAD_DISP1_DAT8 = 165,
|
||||
MX51_PAD_DISP1_DAT9 = 166,
|
||||
MX51_PAD_DISP1_DAT10 = 167,
|
||||
MX51_PAD_DISP1_DAT11 = 168,
|
||||
MX51_PAD_DISP1_DAT12 = 169,
|
||||
MX51_PAD_DISP1_DAT13 = 170,
|
||||
MX51_PAD_DISP1_DAT14 = 171,
|
||||
MX51_PAD_DISP1_DAT15 = 172,
|
||||
MX51_PAD_DISP1_DAT16 = 173,
|
||||
MX51_PAD_DISP1_DAT17 = 174,
|
||||
MX51_PAD_DISP1_DAT18 = 175,
|
||||
MX51_PAD_DISP1_DAT19 = 176,
|
||||
MX51_PAD_DISP1_DAT20 = 177,
|
||||
MX51_PAD_DISP1_DAT21 = 178,
|
||||
MX51_PAD_DISP1_DAT22 = 179,
|
||||
MX51_PAD_DISP1_DAT23 = 180,
|
||||
MX51_PAD_DI1_PIN3 = 181,
|
||||
MX51_PAD_DI1_PIN2 = 182,
|
||||
MX51_PAD_DI_GP2 = 183,
|
||||
MX51_PAD_DI_GP3 = 184,
|
||||
MX51_PAD_DI2_PIN4 = 185,
|
||||
MX51_PAD_DI2_PIN2 = 186,
|
||||
MX51_PAD_DI2_PIN3 = 187,
|
||||
MX51_PAD_DI2_DISP_CLK = 188,
|
||||
MX51_PAD_DI_GP4 = 189,
|
||||
MX51_PAD_DISP2_DAT0 = 190,
|
||||
MX51_PAD_DISP2_DAT1 = 191,
|
||||
MX51_PAD_DISP2_DAT2 = 192,
|
||||
MX51_PAD_DISP2_DAT3 = 193,
|
||||
MX51_PAD_DISP2_DAT4 = 194,
|
||||
MX51_PAD_DISP2_DAT5 = 195,
|
||||
MX51_PAD_DISP2_DAT6 = 196,
|
||||
MX51_PAD_DISP2_DAT7 = 197,
|
||||
MX51_PAD_DISP2_DAT8 = 198,
|
||||
MX51_PAD_DISP2_DAT9 = 199,
|
||||
MX51_PAD_DISP2_DAT10 = 200,
|
||||
MX51_PAD_DISP2_DAT11 = 201,
|
||||
MX51_PAD_DISP2_DAT12 = 202,
|
||||
MX51_PAD_DISP2_DAT13 = 203,
|
||||
MX51_PAD_DISP2_DAT14 = 204,
|
||||
MX51_PAD_DISP2_DAT15 = 205,
|
||||
MX51_PAD_SD1_CMD = 206,
|
||||
MX51_PAD_SD1_CLK = 207,
|
||||
MX51_PAD_SD1_DATA0 = 208,
|
||||
MX51_PAD_EIM_DA0 = 209,
|
||||
MX51_PAD_EIM_DA1 = 210,
|
||||
MX51_PAD_EIM_DA2 = 211,
|
||||
MX51_PAD_EIM_DA3 = 212,
|
||||
MX51_PAD_SD1_DATA1 = 213,
|
||||
MX51_PAD_EIM_DA4 = 214,
|
||||
MX51_PAD_EIM_DA5 = 215,
|
||||
MX51_PAD_EIM_DA6 = 216,
|
||||
MX51_PAD_EIM_DA7 = 217,
|
||||
MX51_PAD_SD1_DATA2 = 218,
|
||||
MX51_PAD_EIM_DA10 = 219,
|
||||
MX51_PAD_EIM_DA11 = 220,
|
||||
MX51_PAD_EIM_DA8 = 221,
|
||||
MX51_PAD_EIM_DA9 = 222,
|
||||
MX51_PAD_SD1_DATA3 = 223,
|
||||
MX51_PAD_GPIO1_0 = 224,
|
||||
MX51_PAD_GPIO1_1 = 225,
|
||||
MX51_PAD_EIM_DA12 = 226,
|
||||
MX51_PAD_EIM_DA13 = 227,
|
||||
MX51_PAD_EIM_DA14 = 228,
|
||||
MX51_PAD_EIM_DA15 = 229,
|
||||
MX51_PAD_SD2_CMD = 230,
|
||||
MX51_PAD_SD2_CLK = 231,
|
||||
MX51_PAD_SD2_DATA0 = 232,
|
||||
MX51_PAD_SD2_DATA1 = 233,
|
||||
MX51_PAD_SD2_DATA2 = 234,
|
||||
MX51_PAD_SD2_DATA3 = 235,
|
||||
MX51_PAD_GPIO1_2 = 236,
|
||||
MX51_PAD_GPIO1_3 = 237,
|
||||
MX51_PAD_PMIC_INT_REQ = 238,
|
||||
MX51_PAD_GPIO1_4 = 239,
|
||||
MX51_PAD_GPIO1_5 = 240,
|
||||
MX51_PAD_GPIO1_6 = 241,
|
||||
MX51_PAD_GPIO1_7 = 242,
|
||||
MX51_PAD_GPIO1_8 = 243,
|
||||
MX51_PAD_GPIO1_9 = 244,
|
||||
};
|
||||
|
||||
/* imx51 register maps */
|
||||
|
||||
+201
-201
@@ -23,207 +23,207 @@
|
||||
#include "pinctrl-imx.h"
|
||||
|
||||
enum imx53_pads {
|
||||
MX53_PAD_GPIO_19 = 1,
|
||||
MX53_PAD_KEY_COL0 = 2,
|
||||
MX53_PAD_KEY_ROW0 = 3,
|
||||
MX53_PAD_KEY_COL1 = 4,
|
||||
MX53_PAD_KEY_ROW1 = 5,
|
||||
MX53_PAD_KEY_COL2 = 6,
|
||||
MX53_PAD_KEY_ROW2 = 7,
|
||||
MX53_PAD_KEY_COL3 = 8,
|
||||
MX53_PAD_KEY_ROW3 = 9,
|
||||
MX53_PAD_KEY_COL4 = 10,
|
||||
MX53_PAD_KEY_ROW4 = 11,
|
||||
MX53_PAD_DI0_DISP_CLK = 12,
|
||||
MX53_PAD_DI0_PIN15 = 13,
|
||||
MX53_PAD_DI0_PIN2 = 14,
|
||||
MX53_PAD_DI0_PIN3 = 15,
|
||||
MX53_PAD_DI0_PIN4 = 16,
|
||||
MX53_PAD_DISP0_DAT0 = 17,
|
||||
MX53_PAD_DISP0_DAT1 = 18,
|
||||
MX53_PAD_DISP0_DAT2 = 19,
|
||||
MX53_PAD_DISP0_DAT3 = 20,
|
||||
MX53_PAD_DISP0_DAT4 = 21,
|
||||
MX53_PAD_DISP0_DAT5 = 22,
|
||||
MX53_PAD_DISP0_DAT6 = 23,
|
||||
MX53_PAD_DISP0_DAT7 = 24,
|
||||
MX53_PAD_DISP0_DAT8 = 25,
|
||||
MX53_PAD_DISP0_DAT9 = 26,
|
||||
MX53_PAD_DISP0_DAT10 = 27,
|
||||
MX53_PAD_DISP0_DAT11 = 28,
|
||||
MX53_PAD_DISP0_DAT12 = 29,
|
||||
MX53_PAD_DISP0_DAT13 = 30,
|
||||
MX53_PAD_DISP0_DAT14 = 31,
|
||||
MX53_PAD_DISP0_DAT15 = 32,
|
||||
MX53_PAD_DISP0_DAT16 = 33,
|
||||
MX53_PAD_DISP0_DAT17 = 34,
|
||||
MX53_PAD_DISP0_DAT18 = 35,
|
||||
MX53_PAD_DISP0_DAT19 = 36,
|
||||
MX53_PAD_DISP0_DAT20 = 37,
|
||||
MX53_PAD_DISP0_DAT21 = 38,
|
||||
MX53_PAD_DISP0_DAT22 = 39,
|
||||
MX53_PAD_DISP0_DAT23 = 40,
|
||||
MX53_PAD_CSI0_PIXCLK = 41,
|
||||
MX53_PAD_CSI0_MCLK = 42,
|
||||
MX53_PAD_CSI0_DATA_EN = 43,
|
||||
MX53_PAD_CSI0_VSYNC = 44,
|
||||
MX53_PAD_CSI0_DAT4 = 45,
|
||||
MX53_PAD_CSI0_DAT5 = 46,
|
||||
MX53_PAD_CSI0_DAT6 = 47,
|
||||
MX53_PAD_CSI0_DAT7 = 48,
|
||||
MX53_PAD_CSI0_DAT8 = 49,
|
||||
MX53_PAD_CSI0_DAT9 = 50,
|
||||
MX53_PAD_CSI0_DAT10 = 51,
|
||||
MX53_PAD_CSI0_DAT11 = 52,
|
||||
MX53_PAD_CSI0_DAT12 = 53,
|
||||
MX53_PAD_CSI0_DAT13 = 54,
|
||||
MX53_PAD_CSI0_DAT14 = 55,
|
||||
MX53_PAD_CSI0_DAT15 = 56,
|
||||
MX53_PAD_CSI0_DAT16 = 57,
|
||||
MX53_PAD_CSI0_DAT17 = 58,
|
||||
MX53_PAD_CSI0_DAT18 = 59,
|
||||
MX53_PAD_CSI0_DAT19 = 60,
|
||||
MX53_PAD_EIM_A25 = 61,
|
||||
MX53_PAD_EIM_EB2 = 62,
|
||||
MX53_PAD_EIM_D16 = 63,
|
||||
MX53_PAD_EIM_D17 = 64,
|
||||
MX53_PAD_EIM_D18 = 65,
|
||||
MX53_PAD_EIM_D19 = 66,
|
||||
MX53_PAD_EIM_D20 = 67,
|
||||
MX53_PAD_EIM_D21 = 68,
|
||||
MX53_PAD_EIM_D22 = 69,
|
||||
MX53_PAD_EIM_D23 = 70,
|
||||
MX53_PAD_EIM_EB3 = 71,
|
||||
MX53_PAD_EIM_D24 = 72,
|
||||
MX53_PAD_EIM_D25 = 73,
|
||||
MX53_PAD_EIM_D26 = 74,
|
||||
MX53_PAD_EIM_D27 = 75,
|
||||
MX53_PAD_EIM_D28 = 76,
|
||||
MX53_PAD_EIM_D29 = 77,
|
||||
MX53_PAD_EIM_D30 = 78,
|
||||
MX53_PAD_EIM_D31 = 79,
|
||||
MX53_PAD_EIM_A24 = 80,
|
||||
MX53_PAD_EIM_A23 = 81,
|
||||
MX53_PAD_EIM_A22 = 82,
|
||||
MX53_PAD_EIM_A21 = 83,
|
||||
MX53_PAD_EIM_A20 = 84,
|
||||
MX53_PAD_EIM_A19 = 85,
|
||||
MX53_PAD_EIM_A18 = 86,
|
||||
MX53_PAD_EIM_A17 = 87,
|
||||
MX53_PAD_EIM_A16 = 88,
|
||||
MX53_PAD_EIM_CS0 = 89,
|
||||
MX53_PAD_EIM_CS1 = 90,
|
||||
MX53_PAD_EIM_OE = 91,
|
||||
MX53_PAD_EIM_RW = 92,
|
||||
MX53_PAD_EIM_LBA = 93,
|
||||
MX53_PAD_EIM_EB0 = 94,
|
||||
MX53_PAD_EIM_EB1 = 95,
|
||||
MX53_PAD_EIM_DA0 = 96,
|
||||
MX53_PAD_EIM_DA1 = 97,
|
||||
MX53_PAD_EIM_DA2 = 98,
|
||||
MX53_PAD_EIM_DA3 = 99,
|
||||
MX53_PAD_EIM_DA4 = 100,
|
||||
MX53_PAD_EIM_DA5 = 101,
|
||||
MX53_PAD_EIM_DA6 = 102,
|
||||
MX53_PAD_EIM_DA7 = 103,
|
||||
MX53_PAD_EIM_DA8 = 104,
|
||||
MX53_PAD_EIM_DA9 = 105,
|
||||
MX53_PAD_EIM_DA10 = 106,
|
||||
MX53_PAD_EIM_DA11 = 107,
|
||||
MX53_PAD_EIM_DA12 = 108,
|
||||
MX53_PAD_EIM_DA13 = 109,
|
||||
MX53_PAD_EIM_DA14 = 110,
|
||||
MX53_PAD_EIM_DA15 = 111,
|
||||
MX53_PAD_NANDF_WE_B = 112,
|
||||
MX53_PAD_NANDF_RE_B = 113,
|
||||
MX53_PAD_EIM_WAIT = 114,
|
||||
MX53_PAD_LVDS1_TX3_P = 115,
|
||||
MX53_PAD_LVDS1_TX2_P = 116,
|
||||
MX53_PAD_LVDS1_CLK_P = 117,
|
||||
MX53_PAD_LVDS1_TX1_P = 118,
|
||||
MX53_PAD_LVDS1_TX0_P = 119,
|
||||
MX53_PAD_LVDS0_TX3_P = 120,
|
||||
MX53_PAD_LVDS0_CLK_P = 121,
|
||||
MX53_PAD_LVDS0_TX2_P = 122,
|
||||
MX53_PAD_LVDS0_TX1_P = 123,
|
||||
MX53_PAD_LVDS0_TX0_P = 124,
|
||||
MX53_PAD_GPIO_10 = 125,
|
||||
MX53_PAD_GPIO_11 = 126,
|
||||
MX53_PAD_GPIO_12 = 127,
|
||||
MX53_PAD_GPIO_13 = 128,
|
||||
MX53_PAD_GPIO_14 = 129,
|
||||
MX53_PAD_NANDF_CLE = 130,
|
||||
MX53_PAD_NANDF_ALE = 131,
|
||||
MX53_PAD_NANDF_WP_B = 132,
|
||||
MX53_PAD_NANDF_RB0 = 133,
|
||||
MX53_PAD_NANDF_CS0 = 134,
|
||||
MX53_PAD_NANDF_CS1 = 135,
|
||||
MX53_PAD_NANDF_CS2 = 136,
|
||||
MX53_PAD_NANDF_CS3 = 137,
|
||||
MX53_PAD_FEC_MDIO = 138,
|
||||
MX53_PAD_FEC_REF_CLK = 139,
|
||||
MX53_PAD_FEC_RX_ER = 140,
|
||||
MX53_PAD_FEC_CRS_DV = 141,
|
||||
MX53_PAD_FEC_RXD1 = 142,
|
||||
MX53_PAD_FEC_RXD0 = 143,
|
||||
MX53_PAD_FEC_TX_EN = 144,
|
||||
MX53_PAD_FEC_TXD1 = 145,
|
||||
MX53_PAD_FEC_TXD0 = 146,
|
||||
MX53_PAD_FEC_MDC = 147,
|
||||
MX53_PAD_PATA_DIOW = 148,
|
||||
MX53_PAD_PATA_DMACK = 149,
|
||||
MX53_PAD_PATA_DMARQ = 150,
|
||||
MX53_PAD_PATA_BUFFER_EN = 151,
|
||||
MX53_PAD_PATA_INTRQ = 152,
|
||||
MX53_PAD_PATA_DIOR = 153,
|
||||
MX53_PAD_PATA_RESET_B = 154,
|
||||
MX53_PAD_PATA_IORDY = 155,
|
||||
MX53_PAD_PATA_DA_0 = 156,
|
||||
MX53_PAD_PATA_DA_1 = 157,
|
||||
MX53_PAD_PATA_DA_2 = 158,
|
||||
MX53_PAD_PATA_CS_0 = 159,
|
||||
MX53_PAD_PATA_CS_1 = 160,
|
||||
MX53_PAD_PATA_DATA0 = 161,
|
||||
MX53_PAD_PATA_DATA1 = 162,
|
||||
MX53_PAD_PATA_DATA2 = 163,
|
||||
MX53_PAD_PATA_DATA3 = 164,
|
||||
MX53_PAD_PATA_DATA4 = 165,
|
||||
MX53_PAD_PATA_DATA5 = 166,
|
||||
MX53_PAD_PATA_DATA6 = 167,
|
||||
MX53_PAD_PATA_DATA7 = 168,
|
||||
MX53_PAD_PATA_DATA8 = 169,
|
||||
MX53_PAD_PATA_DATA9 = 170,
|
||||
MX53_PAD_PATA_DATA10 = 171,
|
||||
MX53_PAD_PATA_DATA11 = 172,
|
||||
MX53_PAD_PATA_DATA12 = 173,
|
||||
MX53_PAD_PATA_DATA13 = 174,
|
||||
MX53_PAD_PATA_DATA14 = 175,
|
||||
MX53_PAD_PATA_DATA15 = 176,
|
||||
MX53_PAD_SD1_DATA0 = 177,
|
||||
MX53_PAD_SD1_DATA1 = 178,
|
||||
MX53_PAD_SD1_CMD = 179,
|
||||
MX53_PAD_SD1_DATA2 = 180,
|
||||
MX53_PAD_SD1_CLK = 181,
|
||||
MX53_PAD_SD1_DATA3 = 182,
|
||||
MX53_PAD_SD2_CLK = 183,
|
||||
MX53_PAD_SD2_CMD = 184,
|
||||
MX53_PAD_SD2_DATA3 = 185,
|
||||
MX53_PAD_SD2_DATA2 = 186,
|
||||
MX53_PAD_SD2_DATA1 = 187,
|
||||
MX53_PAD_SD2_DATA0 = 188,
|
||||
MX53_PAD_GPIO_0 = 189,
|
||||
MX53_PAD_GPIO_1 = 190,
|
||||
MX53_PAD_GPIO_9 = 191,
|
||||
MX53_PAD_GPIO_3 = 192,
|
||||
MX53_PAD_GPIO_6 = 193,
|
||||
MX53_PAD_GPIO_2 = 194,
|
||||
MX53_PAD_GPIO_4 = 195,
|
||||
MX53_PAD_GPIO_5 = 196,
|
||||
MX53_PAD_GPIO_7 = 197,
|
||||
MX53_PAD_GPIO_8 = 198,
|
||||
MX53_PAD_GPIO_16 = 199,
|
||||
MX53_PAD_GPIO_17 = 200,
|
||||
MX53_PAD_GPIO_18 = 201,
|
||||
MX53_PAD_GPIO_19 = 0,
|
||||
MX53_PAD_KEY_COL0 = 1,
|
||||
MX53_PAD_KEY_ROW0 = 2,
|
||||
MX53_PAD_KEY_COL1 = 3,
|
||||
MX53_PAD_KEY_ROW1 = 4,
|
||||
MX53_PAD_KEY_COL2 = 5,
|
||||
MX53_PAD_KEY_ROW2 = 6,
|
||||
MX53_PAD_KEY_COL3 = 7,
|
||||
MX53_PAD_KEY_ROW3 = 8,
|
||||
MX53_PAD_KEY_COL4 = 9,
|
||||
MX53_PAD_KEY_ROW4 = 10,
|
||||
MX53_PAD_DI0_DISP_CLK = 11,
|
||||
MX53_PAD_DI0_PIN15 = 12,
|
||||
MX53_PAD_DI0_PIN2 = 13,
|
||||
MX53_PAD_DI0_PIN3 = 14,
|
||||
MX53_PAD_DI0_PIN4 = 15,
|
||||
MX53_PAD_DISP0_DAT0 = 16,
|
||||
MX53_PAD_DISP0_DAT1 = 17,
|
||||
MX53_PAD_DISP0_DAT2 = 18,
|
||||
MX53_PAD_DISP0_DAT3 = 19,
|
||||
MX53_PAD_DISP0_DAT4 = 20,
|
||||
MX53_PAD_DISP0_DAT5 = 21,
|
||||
MX53_PAD_DISP0_DAT6 = 22,
|
||||
MX53_PAD_DISP0_DAT7 = 23,
|
||||
MX53_PAD_DISP0_DAT8 = 24,
|
||||
MX53_PAD_DISP0_DAT9 = 25,
|
||||
MX53_PAD_DISP0_DAT10 = 26,
|
||||
MX53_PAD_DISP0_DAT11 = 27,
|
||||
MX53_PAD_DISP0_DAT12 = 28,
|
||||
MX53_PAD_DISP0_DAT13 = 29,
|
||||
MX53_PAD_DISP0_DAT14 = 30,
|
||||
MX53_PAD_DISP0_DAT15 = 31,
|
||||
MX53_PAD_DISP0_DAT16 = 32,
|
||||
MX53_PAD_DISP0_DAT17 = 33,
|
||||
MX53_PAD_DISP0_DAT18 = 34,
|
||||
MX53_PAD_DISP0_DAT19 = 35,
|
||||
MX53_PAD_DISP0_DAT20 = 36,
|
||||
MX53_PAD_DISP0_DAT21 = 37,
|
||||
MX53_PAD_DISP0_DAT22 = 38,
|
||||
MX53_PAD_DISP0_DAT23 = 39,
|
||||
MX53_PAD_CSI0_PIXCLK = 40,
|
||||
MX53_PAD_CSI0_MCLK = 41,
|
||||
MX53_PAD_CSI0_DATA_EN = 42,
|
||||
MX53_PAD_CSI0_VSYNC = 43,
|
||||
MX53_PAD_CSI0_DAT4 = 44,
|
||||
MX53_PAD_CSI0_DAT5 = 45,
|
||||
MX53_PAD_CSI0_DAT6 = 46,
|
||||
MX53_PAD_CSI0_DAT7 = 47,
|
||||
MX53_PAD_CSI0_DAT8 = 48,
|
||||
MX53_PAD_CSI0_DAT9 = 49,
|
||||
MX53_PAD_CSI0_DAT10 = 50,
|
||||
MX53_PAD_CSI0_DAT11 = 51,
|
||||
MX53_PAD_CSI0_DAT12 = 52,
|
||||
MX53_PAD_CSI0_DAT13 = 53,
|
||||
MX53_PAD_CSI0_DAT14 = 54,
|
||||
MX53_PAD_CSI0_DAT15 = 55,
|
||||
MX53_PAD_CSI0_DAT16 = 56,
|
||||
MX53_PAD_CSI0_DAT17 = 57,
|
||||
MX53_PAD_CSI0_DAT18 = 58,
|
||||
MX53_PAD_CSI0_DAT19 = 59,
|
||||
MX53_PAD_EIM_A25 = 60,
|
||||
MX53_PAD_EIM_EB2 = 61,
|
||||
MX53_PAD_EIM_D16 = 62,
|
||||
MX53_PAD_EIM_D17 = 63,
|
||||
MX53_PAD_EIM_D18 = 64,
|
||||
MX53_PAD_EIM_D19 = 65,
|
||||
MX53_PAD_EIM_D20 = 66,
|
||||
MX53_PAD_EIM_D21 = 67,
|
||||
MX53_PAD_EIM_D22 = 68,
|
||||
MX53_PAD_EIM_D23 = 69,
|
||||
MX53_PAD_EIM_EB3 = 70,
|
||||
MX53_PAD_EIM_D24 = 71,
|
||||
MX53_PAD_EIM_D25 = 72,
|
||||
MX53_PAD_EIM_D26 = 73,
|
||||
MX53_PAD_EIM_D27 = 74,
|
||||
MX53_PAD_EIM_D28 = 75,
|
||||
MX53_PAD_EIM_D29 = 76,
|
||||
MX53_PAD_EIM_D30 = 77,
|
||||
MX53_PAD_EIM_D31 = 78,
|
||||
MX53_PAD_EIM_A24 = 79,
|
||||
MX53_PAD_EIM_A23 = 80,
|
||||
MX53_PAD_EIM_A22 = 81,
|
||||
MX53_PAD_EIM_A21 = 82,
|
||||
MX53_PAD_EIM_A20 = 83,
|
||||
MX53_PAD_EIM_A19 = 84,
|
||||
MX53_PAD_EIM_A18 = 85,
|
||||
MX53_PAD_EIM_A17 = 86,
|
||||
MX53_PAD_EIM_A16 = 87,
|
||||
MX53_PAD_EIM_CS0 = 88,
|
||||
MX53_PAD_EIM_CS1 = 89,
|
||||
MX53_PAD_EIM_OE = 90,
|
||||
MX53_PAD_EIM_RW = 91,
|
||||
MX53_PAD_EIM_LBA = 92,
|
||||
MX53_PAD_EIM_EB0 = 93,
|
||||
MX53_PAD_EIM_EB1 = 94,
|
||||
MX53_PAD_EIM_DA0 = 95,
|
||||
MX53_PAD_EIM_DA1 = 96,
|
||||
MX53_PAD_EIM_DA2 = 97,
|
||||
MX53_PAD_EIM_DA3 = 98,
|
||||
MX53_PAD_EIM_DA4 = 99,
|
||||
MX53_PAD_EIM_DA5 = 100,
|
||||
MX53_PAD_EIM_DA6 = 101,
|
||||
MX53_PAD_EIM_DA7 = 102,
|
||||
MX53_PAD_EIM_DA8 = 103,
|
||||
MX53_PAD_EIM_DA9 = 104,
|
||||
MX53_PAD_EIM_DA10 = 105,
|
||||
MX53_PAD_EIM_DA11 = 106,
|
||||
MX53_PAD_EIM_DA12 = 107,
|
||||
MX53_PAD_EIM_DA13 = 108,
|
||||
MX53_PAD_EIM_DA14 = 109,
|
||||
MX53_PAD_EIM_DA15 = 110,
|
||||
MX53_PAD_NANDF_WE_B = 111,
|
||||
MX53_PAD_NANDF_RE_B = 112,
|
||||
MX53_PAD_EIM_WAIT = 113,
|
||||
MX53_PAD_LVDS1_TX3_P = 114,
|
||||
MX53_PAD_LVDS1_TX2_P = 115,
|
||||
MX53_PAD_LVDS1_CLK_P = 116,
|
||||
MX53_PAD_LVDS1_TX1_P = 117,
|
||||
MX53_PAD_LVDS1_TX0_P = 118,
|
||||
MX53_PAD_LVDS0_TX3_P = 119,
|
||||
MX53_PAD_LVDS0_CLK_P = 120,
|
||||
MX53_PAD_LVDS0_TX2_P = 121,
|
||||
MX53_PAD_LVDS0_TX1_P = 122,
|
||||
MX53_PAD_LVDS0_TX0_P = 123,
|
||||
MX53_PAD_GPIO_10 = 124,
|
||||
MX53_PAD_GPIO_11 = 125,
|
||||
MX53_PAD_GPIO_12 = 126,
|
||||
MX53_PAD_GPIO_13 = 127,
|
||||
MX53_PAD_GPIO_14 = 128,
|
||||
MX53_PAD_NANDF_CLE = 129,
|
||||
MX53_PAD_NANDF_ALE = 130,
|
||||
MX53_PAD_NANDF_WP_B = 131,
|
||||
MX53_PAD_NANDF_RB0 = 132,
|
||||
MX53_PAD_NANDF_CS0 = 133,
|
||||
MX53_PAD_NANDF_CS1 = 134,
|
||||
MX53_PAD_NANDF_CS2 = 135,
|
||||
MX53_PAD_NANDF_CS3 = 136,
|
||||
MX53_PAD_FEC_MDIO = 137,
|
||||
MX53_PAD_FEC_REF_CLK = 138,
|
||||
MX53_PAD_FEC_RX_ER = 139,
|
||||
MX53_PAD_FEC_CRS_DV = 140,
|
||||
MX53_PAD_FEC_RXD1 = 141,
|
||||
MX53_PAD_FEC_RXD0 = 142,
|
||||
MX53_PAD_FEC_TX_EN = 143,
|
||||
MX53_PAD_FEC_TXD1 = 144,
|
||||
MX53_PAD_FEC_TXD0 = 145,
|
||||
MX53_PAD_FEC_MDC = 146,
|
||||
MX53_PAD_PATA_DIOW = 147,
|
||||
MX53_PAD_PATA_DMACK = 148,
|
||||
MX53_PAD_PATA_DMARQ = 149,
|
||||
MX53_PAD_PATA_BUFFER_EN = 150,
|
||||
MX53_PAD_PATA_INTRQ = 151,
|
||||
MX53_PAD_PATA_DIOR = 152,
|
||||
MX53_PAD_PATA_RESET_B = 153,
|
||||
MX53_PAD_PATA_IORDY = 154,
|
||||
MX53_PAD_PATA_DA_0 = 155,
|
||||
MX53_PAD_PATA_DA_1 = 156,
|
||||
MX53_PAD_PATA_DA_2 = 157,
|
||||
MX53_PAD_PATA_CS_0 = 158,
|
||||
MX53_PAD_PATA_CS_1 = 159,
|
||||
MX53_PAD_PATA_DATA0 = 160,
|
||||
MX53_PAD_PATA_DATA1 = 161,
|
||||
MX53_PAD_PATA_DATA2 = 162,
|
||||
MX53_PAD_PATA_DATA3 = 163,
|
||||
MX53_PAD_PATA_DATA4 = 164,
|
||||
MX53_PAD_PATA_DATA5 = 165,
|
||||
MX53_PAD_PATA_DATA6 = 166,
|
||||
MX53_PAD_PATA_DATA7 = 167,
|
||||
MX53_PAD_PATA_DATA8 = 168,
|
||||
MX53_PAD_PATA_DATA9 = 169,
|
||||
MX53_PAD_PATA_DATA10 = 170,
|
||||
MX53_PAD_PATA_DATA11 = 171,
|
||||
MX53_PAD_PATA_DATA12 = 172,
|
||||
MX53_PAD_PATA_DATA13 = 173,
|
||||
MX53_PAD_PATA_DATA14 = 174,
|
||||
MX53_PAD_PATA_DATA15 = 175,
|
||||
MX53_PAD_SD1_DATA0 = 176,
|
||||
MX53_PAD_SD1_DATA1 = 177,
|
||||
MX53_PAD_SD1_CMD = 178,
|
||||
MX53_PAD_SD1_DATA2 = 179,
|
||||
MX53_PAD_SD1_CLK = 180,
|
||||
MX53_PAD_SD1_DATA3 = 181,
|
||||
MX53_PAD_SD2_CLK = 182,
|
||||
MX53_PAD_SD2_CMD = 183,
|
||||
MX53_PAD_SD2_DATA3 = 184,
|
||||
MX53_PAD_SD2_DATA2 = 185,
|
||||
MX53_PAD_SD2_DATA1 = 186,
|
||||
MX53_PAD_SD2_DATA0 = 187,
|
||||
MX53_PAD_GPIO_0 = 188,
|
||||
MX53_PAD_GPIO_1 = 189,
|
||||
MX53_PAD_GPIO_9 = 190,
|
||||
MX53_PAD_GPIO_3 = 191,
|
||||
MX53_PAD_GPIO_6 = 192,
|
||||
MX53_PAD_GPIO_2 = 193,
|
||||
MX53_PAD_GPIO_4 = 194,
|
||||
MX53_PAD_GPIO_5 = 195,
|
||||
MX53_PAD_GPIO_7 = 196,
|
||||
MX53_PAD_GPIO_8 = 197,
|
||||
MX53_PAD_GPIO_16 = 198,
|
||||
MX53_PAD_GPIO_17 = 199,
|
||||
MX53_PAD_GPIO_18 = 200,
|
||||
};
|
||||
|
||||
/* imx53 register maps */
|
||||
|
||||
@@ -465,6 +465,8 @@ static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
|
||||
static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
|
||||
DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
|
||||
DB8500_PIN_AH15 };
|
||||
static const unsigned mc1_a_2_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AJ15,
|
||||
DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,DB8500_PIN_AH15 };
|
||||
static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
|
||||
DB8500_PIN_AH12, DB8500_PIN_AH11 };
|
||||
static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10,
|
||||
@@ -641,6 +643,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
|
||||
DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
|
||||
@@ -768,7 +771,7 @@ DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
|
||||
/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
|
||||
DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
|
||||
DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
|
||||
DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1");
|
||||
DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2", "mc1dir_a_1");
|
||||
DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
|
||||
DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
|
||||
DB8500_FUNC_GROUPS(usb, "usb_a_1");
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,357 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include "pinctrl-nomadik.h"
|
||||
|
||||
/* All the pins that can be used for GPIO and some other functions */
|
||||
#define _GPIO(offset) (offset)
|
||||
|
||||
#define STN8815_PIN_B4 _GPIO(0)
|
||||
#define STN8815_PIN_D5 _GPIO(1)
|
||||
#define STN8815_PIN_C5 _GPIO(2)
|
||||
#define STN8815_PIN_A4 _GPIO(3)
|
||||
#define STN8815_PIN_B5 _GPIO(4)
|
||||
#define STN8815_PIN_D6 _GPIO(5)
|
||||
#define STN8815_PIN_C6 _GPIO(6)
|
||||
#define STN8815_PIN_B6 _GPIO(7)
|
||||
#define STN8815_PIN_B10 _GPIO(8)
|
||||
#define STN8815_PIN_A10 _GPIO(9)
|
||||
#define STN8815_PIN_C11 _GPIO(10)
|
||||
#define STN8815_PIN_B11 _GPIO(11)
|
||||
#define STN8815_PIN_A11 _GPIO(12)
|
||||
#define STN8815_PIN_C12 _GPIO(13)
|
||||
#define STN8815_PIN_B12 _GPIO(14)
|
||||
#define STN8815_PIN_A12 _GPIO(15)
|
||||
#define STN8815_PIN_C13 _GPIO(16)
|
||||
#define STN8815_PIN_B13 _GPIO(17)
|
||||
#define STN8815_PIN_A13 _GPIO(18)
|
||||
#define STN8815_PIN_D13 _GPIO(19)
|
||||
#define STN8815_PIN_C14 _GPIO(20)
|
||||
#define STN8815_PIN_B14 _GPIO(21)
|
||||
#define STN8815_PIN_A14 _GPIO(22)
|
||||
#define STN8815_PIN_D15 _GPIO(23)
|
||||
#define STN8815_PIN_C15 _GPIO(24)
|
||||
#define STN8815_PIN_B15 _GPIO(25)
|
||||
#define STN8815_PIN_A15 _GPIO(26)
|
||||
#define STN8815_PIN_C16 _GPIO(27)
|
||||
#define STN8815_PIN_B16 _GPIO(28)
|
||||
#define STN8815_PIN_A16 _GPIO(29)
|
||||
#define STN8815_PIN_D17 _GPIO(30)
|
||||
#define STN8815_PIN_C17 _GPIO(31)
|
||||
#define STN8815_PIN_AB6 _GPIO(32)
|
||||
#define STN8815_PIN_AA6 _GPIO(33)
|
||||
#define STN8815_PIN_Y6 _GPIO(34)
|
||||
#define STN8815_PIN_Y5 _GPIO(35)
|
||||
#define STN8815_PIN_AA5 _GPIO(36)
|
||||
#define STN8815_PIN_AB5 _GPIO(37)
|
||||
#define STN8815_PIN_AB4 _GPIO(38)
|
||||
#define STN8815_PIN_Y4 _GPIO(39)
|
||||
#define STN8815_PIN_R1 _GPIO(40)
|
||||
#define STN8815_PIN_R2 _GPIO(41)
|
||||
#define STN8815_PIN_R3 _GPIO(42)
|
||||
#define STN8815_PIN_P1 _GPIO(43)
|
||||
#define STN8815_PIN_P2 _GPIO(44)
|
||||
#define STN8815_PIN_P3 _GPIO(45)
|
||||
#define STN8815_PIN_N1 _GPIO(46)
|
||||
#define STN8815_PIN_N2 _GPIO(47)
|
||||
#define STN8815_PIN_N3 _GPIO(48)
|
||||
#define STN8815_PIN_M1 _GPIO(49)
|
||||
#define STN8815_PIN_M3 _GPIO(50)
|
||||
#define STN8815_PIN_M2 _GPIO(51)
|
||||
#define STN8815_PIN_L1 _GPIO(52)
|
||||
#define STN8815_PIN_L4 _GPIO(53)
|
||||
#define STN8815_PIN_L3 _GPIO(54)
|
||||
#define STN8815_PIN_L2 _GPIO(55)
|
||||
#define STN8815_PIN_F3 _GPIO(56)
|
||||
#define STN8815_PIN_F2 _GPIO(57)
|
||||
#define STN8815_PIN_E1 _GPIO(58)
|
||||
#define STN8815_PIN_E3 _GPIO(59)
|
||||
#define STN8815_PIN_E2 _GPIO(60)
|
||||
#define STN8815_PIN_E4 _GPIO(61)
|
||||
#define STN8815_PIN_D3 _GPIO(62)
|
||||
#define STN8815_PIN_D2 _GPIO(63)
|
||||
#define STN8815_PIN_F21 _GPIO(64)
|
||||
#define STN8815_PIN_F20 _GPIO(65)
|
||||
#define STN8815_PIN_E22 _GPIO(66)
|
||||
#define STN8815_PIN_D22 _GPIO(67)
|
||||
#define STN8815_PIN_E21 _GPIO(68)
|
||||
#define STN8815_PIN_E20 _GPIO(69)
|
||||
#define STN8815_PIN_C22 _GPIO(70)
|
||||
#define STN8815_PIN_D21 _GPIO(71)
|
||||
#define STN8815_PIN_D20 _GPIO(72)
|
||||
#define STN8815_PIN_C21 _GPIO(73)
|
||||
#define STN8815_PIN_C20 _GPIO(74)
|
||||
#define STN8815_PIN_C19 _GPIO(75)
|
||||
#define STN8815_PIN_B20 _GPIO(76)
|
||||
#define STN8815_PIN_B8 _GPIO(77)
|
||||
#define STN8815_PIN_A8 _GPIO(78)
|
||||
#define STN8815_PIN_C9 _GPIO(79)
|
||||
#define STN8815_PIN_B9 _GPIO(80)
|
||||
#define STN8815_PIN_A9 _GPIO(81)
|
||||
#define STN8815_PIN_C10 _GPIO(82)
|
||||
#define STN8815_PIN_K1 _GPIO(83)
|
||||
#define STN8815_PIN_K3 _GPIO(84)
|
||||
#define STN8815_PIN_K2 _GPIO(85)
|
||||
#define STN8815_PIN_J1 _GPIO(86)
|
||||
#define STN8815_PIN_J3 _GPIO(87)
|
||||
#define STN8815_PIN_J2 _GPIO(88)
|
||||
#define STN8815_PIN_H1 _GPIO(89)
|
||||
#define STN8815_PIN_H3 _GPIO(90)
|
||||
#define STN8815_PIN_H2 _GPIO(91)
|
||||
#define STN8815_PIN_G1 _GPIO(92)
|
||||
#define STN8815_PIN_G3 _GPIO(93)
|
||||
#define STN8815_PIN_G2 _GPIO(94)
|
||||
#define STN8815_PIN_F1 _GPIO(95)
|
||||
#define STN8815_PIN_T20 _GPIO(96)
|
||||
#define STN8815_PIN_R21 _GPIO(97)
|
||||
#define STN8815_PIN_R20 _GPIO(98)
|
||||
#define STN8815_PIN_U22 _GPIO(99)
|
||||
#define STN8815_PIN_N21 _GPIO(100)
|
||||
#define STN8815_PIN_N20 _GPIO(101)
|
||||
#define STN8815_PIN_P22 _GPIO(102)
|
||||
#define STN8815_PIN_N22 _GPIO(103)
|
||||
#define STN8815_PIN_V22 _GPIO(104)
|
||||
#define STN8815_PIN_V21 _GPIO(105)
|
||||
#define STN8815_PIN_K22 _GPIO(106)
|
||||
#define STN8815_PIN_K21 _GPIO(107)
|
||||
#define STN8815_PIN_H20 _GPIO(108)
|
||||
#define STN8815_PIN_G20 _GPIO(109)
|
||||
#define STN8815_PIN_L21 _GPIO(110)
|
||||
#define STN8815_PIN_H21 _GPIO(111)
|
||||
#define STN8815_PIN_J21 _GPIO(112)
|
||||
#define STN8815_PIN_H22 _GPIO(113)
|
||||
#define STN8815_PIN_K20 _GPIO(114)
|
||||
#define STN8815_PIN_L22 _GPIO(115)
|
||||
#define STN8815_PIN_G21 _GPIO(116)
|
||||
#define STN8815_PIN_J20 _GPIO(117)
|
||||
#define STN8815_PIN_G22 _GPIO(118)
|
||||
#define STN8815_PIN_U19 _GPIO(119)
|
||||
#define STN8815_PIN_G19 _GPIO(120)
|
||||
#define STN8815_PIN_M22 _GPIO(121)
|
||||
#define STN8815_PIN_M19 _GPIO(122)
|
||||
#define STN8815_PIN_J22 _GPIO(123)
|
||||
/* GPIOs 124-127 not routed to pins */
|
||||
|
||||
/*
|
||||
* The names of the pins are denoted by GPIO number and ball name, even
|
||||
* though they can be used for other things than GPIO, this is the first
|
||||
* column in the table of the data sheet and often used on schematics and
|
||||
* such.
|
||||
*/
|
||||
static const struct pinctrl_pin_desc nmk_stn8815_pins[] = {
|
||||
PINCTRL_PIN(STN8815_PIN_B4, "GPIO0_B4"),
|
||||
PINCTRL_PIN(STN8815_PIN_D5, "GPIO1_D5"),
|
||||
PINCTRL_PIN(STN8815_PIN_C5, "GPIO2_C5"),
|
||||
PINCTRL_PIN(STN8815_PIN_A4, "GPIO3_A4"),
|
||||
PINCTRL_PIN(STN8815_PIN_B5, "GPIO4_B5"),
|
||||
PINCTRL_PIN(STN8815_PIN_D6, "GPIO5_D6"),
|
||||
PINCTRL_PIN(STN8815_PIN_C6, "GPIO6_C6"),
|
||||
PINCTRL_PIN(STN8815_PIN_B6, "GPIO7_B6"),
|
||||
PINCTRL_PIN(STN8815_PIN_B10, "GPIO8_B10"),
|
||||
PINCTRL_PIN(STN8815_PIN_A10, "GPIO9_A10"),
|
||||
PINCTRL_PIN(STN8815_PIN_C11, "GPIO10_C11"),
|
||||
PINCTRL_PIN(STN8815_PIN_B11, "GPIO11_B11"),
|
||||
PINCTRL_PIN(STN8815_PIN_A11, "GPIO12_A11"),
|
||||
PINCTRL_PIN(STN8815_PIN_C12, "GPIO13_C12"),
|
||||
PINCTRL_PIN(STN8815_PIN_B12, "GPIO14_B12"),
|
||||
PINCTRL_PIN(STN8815_PIN_A12, "GPIO15_A12"),
|
||||
PINCTRL_PIN(STN8815_PIN_C13, "GPIO16_C13"),
|
||||
PINCTRL_PIN(STN8815_PIN_B13, "GPIO17_B13"),
|
||||
PINCTRL_PIN(STN8815_PIN_A13, "GPIO18_A13"),
|
||||
PINCTRL_PIN(STN8815_PIN_D13, "GPIO19_D13"),
|
||||
PINCTRL_PIN(STN8815_PIN_C14, "GPIO20_C14"),
|
||||
PINCTRL_PIN(STN8815_PIN_B14, "GPIO21_B14"),
|
||||
PINCTRL_PIN(STN8815_PIN_A14, "GPIO22_A14"),
|
||||
PINCTRL_PIN(STN8815_PIN_D15, "GPIO23_D15"),
|
||||
PINCTRL_PIN(STN8815_PIN_C15, "GPIO24_C15"),
|
||||
PINCTRL_PIN(STN8815_PIN_B15, "GPIO25_B15"),
|
||||
PINCTRL_PIN(STN8815_PIN_A15, "GPIO26_A15"),
|
||||
PINCTRL_PIN(STN8815_PIN_C16, "GPIO27_C16"),
|
||||
PINCTRL_PIN(STN8815_PIN_B16, "GPIO28_B16"),
|
||||
PINCTRL_PIN(STN8815_PIN_A16, "GPIO29_A16"),
|
||||
PINCTRL_PIN(STN8815_PIN_D17, "GPIO30_D17"),
|
||||
PINCTRL_PIN(STN8815_PIN_C17, "GPIO31_C17"),
|
||||
PINCTRL_PIN(STN8815_PIN_AB6, "GPIO32_AB6"),
|
||||
PINCTRL_PIN(STN8815_PIN_AA6, "GPIO33_AA6"),
|
||||
PINCTRL_PIN(STN8815_PIN_Y6, "GPIO34_Y6"),
|
||||
PINCTRL_PIN(STN8815_PIN_Y5, "GPIO35_Y5"),
|
||||
PINCTRL_PIN(STN8815_PIN_AA5, "GPIO36_AA5"),
|
||||
PINCTRL_PIN(STN8815_PIN_AB5, "GPIO37_AB5"),
|
||||
PINCTRL_PIN(STN8815_PIN_AB4, "GPIO38_AB4"),
|
||||
PINCTRL_PIN(STN8815_PIN_Y4, "GPIO39_Y4"),
|
||||
PINCTRL_PIN(STN8815_PIN_R1, "GPIO40_R1"),
|
||||
PINCTRL_PIN(STN8815_PIN_R2, "GPIO41_R2"),
|
||||
PINCTRL_PIN(STN8815_PIN_R3, "GPIO42_R3"),
|
||||
PINCTRL_PIN(STN8815_PIN_P1, "GPIO43_P1"),
|
||||
PINCTRL_PIN(STN8815_PIN_P2, "GPIO44_P2"),
|
||||
PINCTRL_PIN(STN8815_PIN_P3, "GPIO45_P3"),
|
||||
PINCTRL_PIN(STN8815_PIN_N1, "GPIO46_N1"),
|
||||
PINCTRL_PIN(STN8815_PIN_N2, "GPIO47_N2"),
|
||||
PINCTRL_PIN(STN8815_PIN_N3, "GPIO48_N3"),
|
||||
PINCTRL_PIN(STN8815_PIN_M1, "GPIO49_M1"),
|
||||
PINCTRL_PIN(STN8815_PIN_M3, "GPIO50_M3"),
|
||||
PINCTRL_PIN(STN8815_PIN_M2, "GPIO51_M2"),
|
||||
PINCTRL_PIN(STN8815_PIN_L1, "GPIO52_L1"),
|
||||
PINCTRL_PIN(STN8815_PIN_L4, "GPIO53_L4"),
|
||||
PINCTRL_PIN(STN8815_PIN_L3, "GPIO54_L3"),
|
||||
PINCTRL_PIN(STN8815_PIN_L2, "GPIO55_L2"),
|
||||
PINCTRL_PIN(STN8815_PIN_F3, "GPIO56_F3"),
|
||||
PINCTRL_PIN(STN8815_PIN_F2, "GPIO57_F2"),
|
||||
PINCTRL_PIN(STN8815_PIN_E1, "GPIO58_E1"),
|
||||
PINCTRL_PIN(STN8815_PIN_E3, "GPIO59_E3"),
|
||||
PINCTRL_PIN(STN8815_PIN_E2, "GPIO60_E2"),
|
||||
PINCTRL_PIN(STN8815_PIN_E4, "GPIO61_E4"),
|
||||
PINCTRL_PIN(STN8815_PIN_D3, "GPIO62_D3"),
|
||||
PINCTRL_PIN(STN8815_PIN_D2, "GPIO63_D2"),
|
||||
PINCTRL_PIN(STN8815_PIN_F21, "GPIO64_F21"),
|
||||
PINCTRL_PIN(STN8815_PIN_F20, "GPIO65_F20"),
|
||||
PINCTRL_PIN(STN8815_PIN_E22, "GPIO66_E22"),
|
||||
PINCTRL_PIN(STN8815_PIN_D22, "GPIO67_D22"),
|
||||
PINCTRL_PIN(STN8815_PIN_E21, "GPIO68_E21"),
|
||||
PINCTRL_PIN(STN8815_PIN_E20, "GPIO69_E20"),
|
||||
PINCTRL_PIN(STN8815_PIN_C22, "GPIO70_C22"),
|
||||
PINCTRL_PIN(STN8815_PIN_D21, "GPIO71_D21"),
|
||||
PINCTRL_PIN(STN8815_PIN_D20, "GPIO72_D20"),
|
||||
PINCTRL_PIN(STN8815_PIN_C21, "GPIO73_C21"),
|
||||
PINCTRL_PIN(STN8815_PIN_C20, "GPIO74_C20"),
|
||||
PINCTRL_PIN(STN8815_PIN_C19, "GPIO75_C19"),
|
||||
PINCTRL_PIN(STN8815_PIN_B20, "GPIO76_B20"),
|
||||
PINCTRL_PIN(STN8815_PIN_B8, "GPIO77_B8"),
|
||||
PINCTRL_PIN(STN8815_PIN_A8, "GPIO78_A8"),
|
||||
PINCTRL_PIN(STN8815_PIN_C9, "GPIO79_C9"),
|
||||
PINCTRL_PIN(STN8815_PIN_B9, "GPIO80_B9"),
|
||||
PINCTRL_PIN(STN8815_PIN_A9, "GPIO81_A9"),
|
||||
PINCTRL_PIN(STN8815_PIN_C10, "GPIO82_C10"),
|
||||
PINCTRL_PIN(STN8815_PIN_K1, "GPIO83_K1"),
|
||||
PINCTRL_PIN(STN8815_PIN_K3, "GPIO84_K3"),
|
||||
PINCTRL_PIN(STN8815_PIN_K2, "GPIO85_K2"),
|
||||
PINCTRL_PIN(STN8815_PIN_J1, "GPIO86_J1"),
|
||||
PINCTRL_PIN(STN8815_PIN_J3, "GPIO87_J3"),
|
||||
PINCTRL_PIN(STN8815_PIN_J2, "GPIO88_J2"),
|
||||
PINCTRL_PIN(STN8815_PIN_H1, "GPIO89_H1"),
|
||||
PINCTRL_PIN(STN8815_PIN_H3, "GPIO90_H3"),
|
||||
PINCTRL_PIN(STN8815_PIN_H2, "GPIO91_H2"),
|
||||
PINCTRL_PIN(STN8815_PIN_G1, "GPIO92_G1"),
|
||||
PINCTRL_PIN(STN8815_PIN_G3, "GPIO93_G3"),
|
||||
PINCTRL_PIN(STN8815_PIN_G2, "GPIO94_G2"),
|
||||
PINCTRL_PIN(STN8815_PIN_F1, "GPIO95_F1"),
|
||||
PINCTRL_PIN(STN8815_PIN_T20, "GPIO96_T20"),
|
||||
PINCTRL_PIN(STN8815_PIN_R21, "GPIO97_R21"),
|
||||
PINCTRL_PIN(STN8815_PIN_R20, "GPIO98_R20"),
|
||||
PINCTRL_PIN(STN8815_PIN_U22, "GPIO99_U22"),
|
||||
PINCTRL_PIN(STN8815_PIN_N21, "GPIO100_N21"),
|
||||
PINCTRL_PIN(STN8815_PIN_N20, "GPIO101_N20"),
|
||||
PINCTRL_PIN(STN8815_PIN_P22, "GPIO102_P22"),
|
||||
PINCTRL_PIN(STN8815_PIN_N22, "GPIO103_N22"),
|
||||
PINCTRL_PIN(STN8815_PIN_V22, "GPIO104_V22"),
|
||||
PINCTRL_PIN(STN8815_PIN_V21, "GPIO105_V21"),
|
||||
PINCTRL_PIN(STN8815_PIN_K22, "GPIO106_K22"),
|
||||
PINCTRL_PIN(STN8815_PIN_K21, "GPIO107_K21"),
|
||||
PINCTRL_PIN(STN8815_PIN_H20, "GPIO108_H20"),
|
||||
PINCTRL_PIN(STN8815_PIN_G20, "GPIO109_G20"),
|
||||
PINCTRL_PIN(STN8815_PIN_L21, "GPIO110_L21"),
|
||||
PINCTRL_PIN(STN8815_PIN_H21, "GPIO111_H21"),
|
||||
PINCTRL_PIN(STN8815_PIN_J21, "GPIO112_J21"),
|
||||
PINCTRL_PIN(STN8815_PIN_H22, "GPIO113_H22"),
|
||||
PINCTRL_PIN(STN8815_PIN_K20, "GPIO114_K20"),
|
||||
PINCTRL_PIN(STN8815_PIN_L22, "GPIO115_L22"),
|
||||
PINCTRL_PIN(STN8815_PIN_G21, "GPIO116_G21"),
|
||||
PINCTRL_PIN(STN8815_PIN_J20, "GPIO117_J20"),
|
||||
PINCTRL_PIN(STN8815_PIN_G22, "GPIO118_G22"),
|
||||
PINCTRL_PIN(STN8815_PIN_U19, "GPIO119_U19"),
|
||||
PINCTRL_PIN(STN8815_PIN_G19, "GPIO120_G19"),
|
||||
PINCTRL_PIN(STN8815_PIN_M22, "GPIO121_M22"),
|
||||
PINCTRL_PIN(STN8815_PIN_M19, "GPIO122_M19"),
|
||||
PINCTRL_PIN(STN8815_PIN_J22, "GPIO123_J22"),
|
||||
};
|
||||
|
||||
#define STN8815_GPIO_RANGE(a, b, c) { .name = "STN8815", .id = a, .base = b, \
|
||||
.pin_base = b, .npins = c }
|
||||
|
||||
/*
|
||||
* This matches the 32-pin gpio chips registered by the GPIO portion. This
|
||||
* cannot be const since we assign the struct gpio_chip * pointer at runtime.
|
||||
*/
|
||||
static struct pinctrl_gpio_range nmk_stn8815_ranges[] = {
|
||||
STN8815_GPIO_RANGE(0, 0, 32),
|
||||
STN8815_GPIO_RANGE(1, 32, 32),
|
||||
STN8815_GPIO_RANGE(2, 64, 32),
|
||||
STN8815_GPIO_RANGE(3, 96, 28),
|
||||
};
|
||||
|
||||
/*
|
||||
* Read the pin group names like this:
|
||||
* u0_a_1 = first groups of pins for uart0 on alt function a
|
||||
* i2c2_b_2 = second group of pins for i2c2 on alt function b
|
||||
*/
|
||||
|
||||
/* Altfunction A */
|
||||
static const unsigned u0_a_1_pins[] = { STN8815_PIN_B4, STN8815_PIN_D5,
|
||||
STN8815_PIN_C5, STN8815_PIN_A4, STN8815_PIN_B5, STN8815_PIN_D6,
|
||||
STN8815_PIN_C6, STN8815_PIN_B6 };
|
||||
static const unsigned mmcsd_a_1_pins[] = { STN8815_PIN_B10, STN8815_PIN_A10,
|
||||
STN8815_PIN_C11, STN8815_PIN_B11, STN8815_PIN_A11, STN8815_PIN_C12,
|
||||
STN8815_PIN_B12, STN8815_PIN_A12, STN8815_PIN_C13, STN8815_PIN_C15 };
|
||||
static const unsigned u1_a_1_pins[] = { STN8815_PIN_M2, STN8815_PIN_L1,
|
||||
STN8815_PIN_F3, STN8815_PIN_F2 };
|
||||
static const unsigned i2c1_a_1_pins[] = { STN8815_PIN_L4, STN8815_PIN_L3 };
|
||||
static const unsigned i2c0_a_1_pins[] = { STN8815_PIN_D3, STN8815_PIN_D2 };
|
||||
/* Altfunction B */
|
||||
static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 };
|
||||
static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
|
||||
|
||||
#define STN8815_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \
|
||||
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
|
||||
|
||||
static const struct nmk_pingroup nmk_stn8815_groups[] = {
|
||||
STN8815_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
|
||||
STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
|
||||
STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
|
||||
STN8815_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A),
|
||||
STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
|
||||
STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
|
||||
STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
|
||||
};
|
||||
|
||||
/* We use this macro to define the groups applicable to a function */
|
||||
#define STN8815_FUNC_GROUPS(a, b...) \
|
||||
static const char * const a##_groups[] = { b };
|
||||
|
||||
STN8815_FUNC_GROUPS(u0, "u0_a_1");
|
||||
STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1");
|
||||
STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1");
|
||||
STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
|
||||
STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
|
||||
STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1");
|
||||
|
||||
#define FUNCTION(fname) \
|
||||
{ \
|
||||
.name = #fname, \
|
||||
.groups = fname##_groups, \
|
||||
.ngroups = ARRAY_SIZE(fname##_groups), \
|
||||
}
|
||||
|
||||
static const struct nmk_function nmk_stn8815_functions[] = {
|
||||
FUNCTION(u0),
|
||||
FUNCTION(mmcsd),
|
||||
FUNCTION(u1),
|
||||
FUNCTION(i2c1),
|
||||
FUNCTION(i2c0),
|
||||
FUNCTION(i2cusb),
|
||||
};
|
||||
|
||||
static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
|
||||
.gpio_ranges = nmk_stn8815_ranges,
|
||||
.gpio_num_ranges = ARRAY_SIZE(nmk_stn8815_ranges),
|
||||
.pins = nmk_stn8815_pins,
|
||||
.npins = ARRAY_SIZE(nmk_stn8815_pins),
|
||||
.functions = nmk_stn8815_functions,
|
||||
.nfunctions = ARRAY_SIZE(nmk_stn8815_functions),
|
||||
.groups = nmk_stn8815_groups,
|
||||
.ngroups = ARRAY_SIZE(nmk_stn8815_groups),
|
||||
};
|
||||
|
||||
void __devinit
|
||||
nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
|
||||
{
|
||||
*soc = &nmk_stn8815_soc;
|
||||
}
|
||||
@@ -819,6 +819,7 @@ static struct irq_chip nmk_gpio_irq_chip = {
|
||||
.irq_set_wake = nmk_gpio_irq_set_wake,
|
||||
.irq_startup = nmk_gpio_irq_startup,
|
||||
.irq_shutdown = nmk_gpio_irq_shutdown,
|
||||
.flags = IRQCHIP_MASK_ON_SUSPEND,
|
||||
};
|
||||
|
||||
static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
|
||||
@@ -826,16 +827,14 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
|
||||
{
|
||||
struct nmk_gpio_chip *nmk_chip;
|
||||
struct irq_chip *host_chip = irq_get_chip(irq);
|
||||
unsigned int first_irq;
|
||||
|
||||
chained_irq_enter(host_chip, desc);
|
||||
|
||||
nmk_chip = irq_get_handler_data(irq);
|
||||
first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
|
||||
while (status) {
|
||||
int bit = __ffs(status);
|
||||
|
||||
generic_handle_irq(first_irq + bit);
|
||||
generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
|
||||
status &= ~BIT(bit);
|
||||
}
|
||||
|
||||
@@ -1720,8 +1719,12 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
|
||||
of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
|
||||
|
||||
/* Poke in other ASIC variants here */
|
||||
if (version == PINCTRL_NMK_STN8815)
|
||||
nmk_pinctrl_stn8815_init(&npct->soc);
|
||||
if (version == PINCTRL_NMK_DB8500)
|
||||
nmk_pinctrl_db8500_init(&npct->soc);
|
||||
if (version == PINCTRL_NMK_DB8540)
|
||||
nmk_pinctrl_db8540_init(&npct->soc);
|
||||
|
||||
/*
|
||||
* We need all the GPIO drivers to probe FIRST, or we will not be able
|
||||
@@ -1772,6 +1775,7 @@ static struct platform_driver nmk_gpio_driver = {
|
||||
static const struct platform_device_id nmk_pinctrl_id[] = {
|
||||
{ "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
|
||||
{ "pinctrl-db8500", PINCTRL_NMK_DB8500 },
|
||||
{ "pinctrl-db8540", PINCTRL_NMK_DB8540 },
|
||||
};
|
||||
|
||||
static struct platform_driver nmk_pinctrl_driver = {
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user