2005-04-16 15:20:36 -07:00
|
|
|
/*
|
2012-07-20 11:15:04 +02:00
|
|
|
* Copyright IBM Corp. 1999, 2010
|
2005-11-07 00:59:12 -08:00
|
|
|
*
|
|
|
|
|
* Author(s): Hartmut Penner <hp@de.ibm.com>
|
|
|
|
|
* Martin Schwidefsky <schwidefsky@de.ibm.com>
|
|
|
|
|
* Rob van der Heij <rvdhei@iae.nl>
|
|
|
|
|
* Heiko Carstens <heiko.carstens@de.ibm.com>
|
2005-04-16 15:20:36 -07:00
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
|
2010-02-26 22:37:53 +01:00
|
|
|
#include <linux/init.h>
|
2011-07-24 10:48:19 +02:00
|
|
|
#include <linux/linkage.h>
|
2010-02-26 22:37:53 +01:00
|
|
|
#include <asm/asm-offsets.h>
|
|
|
|
|
#include <asm/thread_info.h>
|
|
|
|
|
#include <asm/page.h>
|
2006-06-29 14:58:17 +02:00
|
|
|
|
2010-02-26 22:37:53 +01:00
|
|
|
__HEAD
|
2011-07-24 10:48:19 +02:00
|
|
|
ENTRY(startup_continue)
|
2010-02-26 22:37:53 +01:00
|
|
|
larl %r1,sched_clock_base_cc
|
|
|
|
|
mvc 0(8,%r1),__LC_LAST_UPDATE_CLOCK
|
|
|
|
|
larl %r13,.LPG1 # get base
|
2006-09-28 16:56:37 +02:00
|
|
|
lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
|
|
|
|
|
lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
|
|
|
|
|
# move IPL device to lowcore
|
2008-12-31 15:11:42 +01:00
|
|
|
lghi %r0,__LC_PASTE
|
|
|
|
|
stg %r0,__LC_VDSO_PER_CPU
|
2006-09-20 15:59:15 +02:00
|
|
|
#
|
|
|
|
|
# Setup stack
|
|
|
|
|
#
|
2006-09-28 16:56:37 +02:00
|
|
|
larl %r15,init_thread_union
|
2009-09-11 10:28:58 +02:00
|
|
|
stg %r15,__LC_THREAD_INFO # cache thread info in lowcore
|
2006-09-28 16:56:37 +02:00
|
|
|
lg %r14,__TI_task(%r15) # cache current in lowcore
|
|
|
|
|
stg %r14,__LC_CURRENT
|
|
|
|
|
aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
|
|
|
|
|
stg %r15,__LC_KERNEL_STACK # set end of kernel stack
|
|
|
|
|
aghi %r15,-160
|
2005-04-16 15:20:36 -07:00
|
|
|
#
|
2007-02-05 21:18:24 +01:00
|
|
|
# Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
|
|
|
|
|
# and create a kernel NSS if the SAVESYS= parm is defined
|
2005-04-16 15:20:36 -07:00
|
|
|
#
|
2007-02-05 21:18:24 +01:00
|
|
|
brasl %r14,startup_init
|
2006-09-28 16:56:37 +02:00
|
|
|
lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
|
|
|
|
|
# virtual and never return ...
|
|
|
|
|
.align 16
|
2010-02-26 22:37:53 +01:00
|
|
|
.LPG1:
|
2006-09-28 16:56:37 +02:00
|
|
|
.Lentry:.quad 0x0000000180000000,_stext
|
2011-07-24 10:48:29 +02:00
|
|
|
.Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space
|
2006-09-28 16:56:37 +02:00
|
|
|
.quad 0 # cr1: primary space segment table
|
|
|
|
|
.quad .Lduct # cr2: dispatchable unit control table
|
|
|
|
|
.quad 0 # cr3: instruction authorization
|
|
|
|
|
.quad 0 # cr4: instruction authorization
|
2007-03-05 23:35:54 +01:00
|
|
|
.quad .Lduct # cr5: primary-aste origin
|
2006-09-28 16:56:37 +02:00
|
|
|
.quad 0 # cr6: I/O interrupts
|
|
|
|
|
.quad 0 # cr7: secondary space segment table
|
|
|
|
|
.quad 0 # cr8: access registers translation
|
|
|
|
|
.quad 0 # cr9: tracing off
|
|
|
|
|
.quad 0 # cr10: tracing off
|
|
|
|
|
.quad 0 # cr11: tracing off
|
|
|
|
|
.quad 0 # cr12: tracing off
|
|
|
|
|
.quad 0 # cr13: home space segment table
|
|
|
|
|
.quad 0xc0000000 # cr14: machine check handling off
|
|
|
|
|
.quad 0 # cr15: linkage stack operations
|
|
|
|
|
.Lpcmsk:.quad 0x0000000180000000
|
2005-04-16 15:20:36 -07:00
|
|
|
.L4malign:.quad 0xffffffffffc00000
|
2006-09-28 16:56:37 +02:00
|
|
|
.Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
|
|
|
|
|
.Lnop: .long 0x07000700
|
2006-06-29 14:58:17 +02:00
|
|
|
.Lparmaddr:
|
|
|
|
|
.quad PARMAREA
|
2007-03-05 23:35:54 +01:00
|
|
|
.align 64
|
|
|
|
|
.Lduct: .long 0,0,0,0,.Lduald,0,0,0
|
|
|
|
|
.long 0,0,0,0,0,0,0,0
|
|
|
|
|
.align 128
|
|
|
|
|
.Lduald:.rept 8
|
|
|
|
|
.long 0x80000000,0,0,0 # invalid access-list entries
|
|
|
|
|
.endr
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2011-07-24 10:48:19 +02:00
|
|
|
ENTRY(_ehead)
|
2010-02-26 22:37:53 +01:00
|
|
|
|
2010-05-12 09:32:13 +02:00
|
|
|
.org 0x100000 - 0x11000 # head.o ends at 0x11000
|
2005-04-16 15:20:36 -07:00
|
|
|
#
|
2006-06-29 14:58:17 +02:00
|
|
|
# startup-code, running in absolute addressing mode
|
2005-04-16 15:20:36 -07:00
|
|
|
#
|
2011-07-24 10:48:19 +02:00
|
|
|
ENTRY(_stext)
|
|
|
|
|
basr %r13,0 # get base
|
2005-10-30 15:00:11 -08:00
|
|
|
.LPG3:
|
2005-04-16 15:20:36 -07:00
|
|
|
# check control registers
|
2006-09-28 16:56:37 +02:00
|
|
|
stctg %c0,%c15,0(%r15)
|
2011-10-30 15:16:58 +01:00
|
|
|
oi 6(%r15),0x60 # enable sigp emergency & external call
|
2006-09-28 16:56:37 +02:00
|
|
|
oi 4(%r15),0x10 # switch on low address proctection
|
|
|
|
|
lctlg %c0,%c15,0(%r15)
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2006-09-28 16:56:37 +02:00
|
|
|
lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess
|
|
|
|
|
brasl %r14,start_kernel # go to C code
|
2005-04-16 15:20:36 -07:00
|
|
|
#
|
|
|
|
|
# We returned from start_kernel ?!? PANIK
|
|
|
|
|
#
|
2006-09-28 16:56:37 +02:00
|
|
|
basr %r13,0
|
|
|
|
|
lpswe .Ldw-.(%r13) # load disabled wait psw
|
2006-09-20 15:59:15 +02:00
|
|
|
|
2006-09-28 16:56:37 +02:00
|
|
|
.align 8
|
|
|
|
|
.Ldw: .quad 0x0002000180000000,0x0000000000000000
|
|
|
|
|
.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
|
