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yoshiask/step

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• ad47a4cba5 Fix bug in branch main Pdawg11239 2025-03-09 01:52:21 -05:00
• 9076731272 Add reset logic Pdawg11239 2025-03-04 23:08:18 -05:00
• b4ba47fac4 Test branching arith, needs verified Pdawg11239 2025-03-04 08:27:09 -05:00
• 9fc9e26248 Move B/BL Pdawg11239 2025-03-03 22:45:52 -05:00
• 07b80db290 Implement branching + MRS Pdawg11239 2025-03-03 21:43:37 -05:00
• e124f0bb53 Remove unneeded masks Pdawg11239 2025-02-22 11:37:54 -05:00
• 90fdd53148 Update error in comment Pdawg11239 2025-02-22 03:50:45 -05:00
• 88ab4378be Tons of optimization to math helpers Pdawg11239 2025-02-22 03:39:10 -05:00
• a67f937c22 Implement CLZ Pdawg11239 2025-02-21 22:36:17 -05:00
• 874320dd1c Decode misc instructions Pdawg11239 2025-02-21 22:26:09 -05:00
• 12f4dbb945 Add LDM/STM to decoder Pdawg11239 2025-02-21 19:52:21 -05:00
• 600e573fbe Implement LDM/STM Pdawg11239 2025-02-21 19:50:56 -05:00
• 8d78c015fe Move to function ptr based decoder Pdawg11239 2025-02-21 19:50:43 -05:00
• 1be82080de [WIP] Start LDM Pdawg11239 2025-02-21 14:19:24 -05:00
• 8f5f20e595 Merge 'step' branch into main; redundant branch Pdawg 2025-02-21 13:08:27 -05:00
• 051e8200e4 don't need that anymore yoshiask/step Joshua "Yoshi" Askharoun 2025-02-21 02:07:36 -06:00
• d9a34b80ce Implement CMP, CMN Joshua "Yoshi" Askharoun 2025-02-21 02:07:18 -06:00
• 37f16c3eab Implement SUB, RSB, SBC, RSC Joshua "Yoshi" Askharoun 2025-02-21 02:02:59 -06:00
• c6fd0ed3b2 Implement ADD and ADC Joshua "Yoshi" Askharoun 2025-02-21 01:46:56 -06:00
• 386c18c67a Use FlagResult extensions Joshua "Yoshi" Askharoun 2025-02-21 01:46:46 -06:00
• 3d0c216036 Rename CarryResult to FlagResult Joshua "Yoshi" Askharoun 2025-02-21 01:44:38 -06:00
• 83c434df31 [WIP] Start implementing ADD and ADC Yoshi Askharoun 2025-02-19 17:01:15 -06:00
• a4b3fef39c [WIP] Decode extra l/s & mult instructions Pdawg11239 2025-02-19 16:07:54 -05:00
• 987d3e166a Implement logic and move DP instructions Joshua "Yoshi" Askharoun 2025-02-19 02:40:23 -06:00
• b85790a146 Add blank cases for all data processing opcodes Joshua "Yoshi" Askharoun 2025-02-19 02:16:24 -06:00
• 643285913d Implement BIC instruction Joshua "Yoshi" Askharoun 2025-02-19 02:10:05 -06:00
• 7612721e62 Implement all data processing shifts Joshua "Yoshi" Askharoun 2025-02-19 01:54:37 -06:00
• 4afcb775c7 [WIP] Small work on decoder Pdawg11239 2025-02-18 22:42:34 -05:00
• ca7d2ca40a [WIP] More DP instruction work Joshua "Yoshi" Askharoun 2025-02-18 20:34:07 -06:00
• 76573dc113 Add LSL helpers Joshua "Yoshi" Askharoun 2025-02-18 20:33:56 -06:00
• a50fac9658 Add RegisterSet[uint] overload Joshua "Yoshi" Askharoun 2025-02-18 14:18:53 -06:00
• d4c86a1d39 Fix CPSR/SPSR banking logic Pdawg11239 2025-02-17 22:04:37 -05:00
• afe250a0a9 Use PC field Joshua "Yoshi" Askharoun 2025-02-17 15:46:41 -06:00
• b6da5c397a [WIP] Give the decoder some structure Pdawg11239 2025-02-17 16:36:25 -05:00
• 044220f532 [WIP] Begin implementing instructions Joshua "Yoshi" Askharoun 2025-02-17 05:45:31 -06:00
• 76f0970198 Generate ExecuteInstruction stubs Joshua "Yoshi" Askharoun 2025-02-17 02:23:51 -06:00
• e62af4ab21 [WIP] Add first pass instruction decoding Joshua "Yoshi" Askharoun 2025-02-17 02:22:11 -06:00
• 75c1caf0a1 Add memory to ARM11Core Joshua "Yoshi" Askharoun 2025-02-17 02:21:45 -06:00
• d045ae9cb7 Remove bound checks on register set Pdawg11239 2025-02-16 20:55:47 -05:00
• 75c9cac814 Actually finish banked registers Pdawg11239 2025-02-16 05:45:38 -05:00
• 1a597a933c Swap to new register banking system Pdawg11239 2025-02-15 12:29:26 -05:00
• 2fa26bb3ba Upload source Pdawg11239 2025-02-15 04:25:03 -05:00
• 23210ab4d3 Initial commit Pdawg11239 2025-02-15 02:45:47 -05:00