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5082893e5d
There is no way to tell in spirv_compiler_emit_load_reg() if the write mask is 64-bit. All loads are 32-bit except for IMMCONST64 and SSA, and the latter ignores the mask, so the only issue lies with IMMCONST64.
60 lines
906 B
Plaintext
60 lines
906 B
Plaintext
[require]
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shader model >= 5.0
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[uav 1]
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format r32 float
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size (buffer, 4)
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0.1 0.2 0.3 0.4
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[pixel shader todo]
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RWByteAddressBuffer u : register(u1);
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float4 main() : sv_target
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{
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u.Store(0, 10);
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u.Store(4, 11.1f);
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return 0;
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}
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[test]
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todo(sm<6) draw quad
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probe uav 1 (0) ri (10)
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if(sm<6) probe uav 1 (1) ri (11)
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if(sm>=6) probe uav 1 (1) r (11.1)
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[pixel shader todo]
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RWByteAddressBuffer u : register(u1);
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float4 main() : sv_target
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{
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u.Store(0, (double)12.2);
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return 0;
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}
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[test]
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todo(sm<6) draw quad
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if(sm<6) probe uav 1 (0) ri (12)
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if(sm>=6) probe uav 1 (0) rd (12.2)
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% SM 6 add support for templated Store<>().
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[require]
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shader model >= 6.0
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[pixel shader]
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RWByteAddressBuffer u : register(u1);
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float4 main() : sv_target
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{
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u.Store<int64_t>(0, (int64_t)-12);
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u.Store<double>(8, 13.3);
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return 0;
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}
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[test]
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draw quad
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probe uav 1 (0) ri64 (-12)
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probe uav 1 (1) rd (13.3)
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