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2449 Commits

Author SHA1 Message Date
Francisco Casas
7b07d77396 ci: Update the DXC version used on the CI to 1.8.2502. 2025-05-06 18:39:02 +02:00
Henri Verbeet
cb4b5641ea vkd3d: Handle multiple fence NULL event waits in d3d12_device_SetEventOnMultipleFenceCompletion(). 2025-05-06 18:29:06 +02:00
Henri Verbeet
3fabac3f70 vkd3d: Handle multiple fence ANY waits in d3d12_device_SetEventOnMultipleFenceCompletion(). 2025-05-06 18:29:06 +02:00
Henri Verbeet
9222f5e5b1 vkd3d: Handle multiple fence ALL waits in d3d12_device_SetEventOnMultipleFenceCompletion(). 2025-05-06 18:29:06 +02:00
Henri Verbeet
52b947a005 vkd3d: Handle single fence waits in d3d12_device_SetEventOnMultipleFenceCompletion(). 
By forwarding to ID3D12Fence_SetEventOnCompletion().
 2025-05-06 18:29:06 +02:00
Henri Verbeet
3ea84156c7 vkd3d: Validate the fence count in d3d12_device_SetEventOnMultipleFenceCompletion(). 2025-05-06 18:29:06 +02:00
Henri Verbeet
75ce9cef92 tests/d3d12: Test ID3D12Device1_SetEventOnMultipleFenceCompletion(). 2025-05-06 18:29:06 +02:00
Shaun Ren
5b06fe83df vkd3d-shader/hlsl: Generate vsir instructions for stream output operations. 2025-05-05 14:54:07 +02:00
Shaun Ren
c8c1e270e0 vkd3d-shader/hlsl: Validate maximum output size in geometry shaders. 2025-05-05 14:43:53 +02:00
Francisco Casas
e6db0ab614 tests: Add tests for DeviceMemoryBarrierWithGroupSync(). 2025-05-05 14:27:35 +02:00
Francisco Casas
b89f0bc730 vkd3d-shader/hlsl: Generate vsir for HLSL_IR_SYNC operations. 
The following table shows how each intrinsic maps to d3d assembly and the
flags that appear in the tpf bytecode, in binary.

    GroupMemoryBarrier()                   sync_g               0010
    GroupMemoryBarrierWithGroupSync()      sync_g_t             0011
    DeviceMemoryBarrier()                  sync_uglobal         1000
    DeviceMemoryBarrierWithGroupSync()     sync_uglobal_t       1001
    AllMemoryBarrier()                     sync_uglobal_g       1010
    AllMemoryBarrierWithGroupSync()        sync_uglobal_g_t     1011
 2025-05-05 14:17:47 +02:00
Francisco Casas
758a4bef09 vkd3d-shader/hlsl: Parse barriers. 
And introduce hlsl_ir_sync to represent them.
 2025-05-05 14:15:14 +02:00
Conor McCarthy
4c8c31fa2e tests/hlsl: Add a shader model 5.1 test to srv-byteaddressbuffer.shader_test. 
Some code paths for TPF handling are not tested if no 5.1 shaders are
compiled.
 2025-04-23 18:11:42 +02:00
Shaun Ren
5d29554fed tests/hlsl: Add geometry shader stream output syntax tests. 2025-04-23 18:03:59 +02:00
Giovanni Mascellani
6ca9395368 tests/d3d12: Skip testing NULL VBVs on NVIDIA on Windows. 
It seems that the NVIDIA drivers leaves VBVs bindings untouched
when they are NULL (or the GPU buffer address is NULL), instead of
setting them to a null binding.

Differently from other cases of inconsistent behaviour between AMD
and NVIDIA, here I'm explicitly marking the NVIDIA behaviour as
broken, because the expected behaviour is spelled out explicitly
(at least for the D3D12 specification standards).
 2025-04-21 14:43:59 +02:00
Giovanni Mascellani
bc637f2633 tests/d3d12: Do not validate the semantic of uint-clearing R11G11B10_FLOAT resources. 
Implementations have no consistent behaviour.
 2025-04-21 14:43:27 +02:00
Giovanni Mascellani
c1d04b84c7 tests/d3d12: Do not test out-of-bound UAV uint clears. 
The behaviour is not uniform: AMD truncates, NVIDIA saturates.
 2025-04-21 14:40:44 +02:00
Giovanni Mascellani
f890db872a tests/d3d12: Do not allow texture creation to fail when testing UAV uint clears. 
If the format is supported texture creation should always succeed.
 2025-04-21 14:40:31 +02:00
Giovanni Mascellani
f932af7f18 tests/d3d12: Check that B5G6R5_UNORM and B5G5R5A1_UNORM are supported before testing them. 
They are not always available on NVIDIA GPUs.
 2025-04-21 14:36:39 +02:00
Giovanni Mascellani
4324817c68 tests/d3d12: Set the descriptor heap when clearing UAVs. 2025-04-21 14:32:58 +02:00
Giovanni Mascellani
a189a4cfb7 tests/hlsl: Do not test the implicit passthrough control point phase for SM6. 2025-04-16 16:43:45 +02:00
Giovanni Mascellani
dbd1938ce4 tests/hlsl: Fix the precision for a 16-bit arithmetic test. 2025-04-16 16:42:20 +02:00
Giovanni Mascellani
3186d66596 tests/hlsl: Do not test dst() on integer arguments with SM6. 
That seems to hit a DXC bug we're not interested into.
 2025-04-16 16:36:58 +02:00
Giovanni Mascellani
9db9f3bdaf tests/hlsl: Do not test 16-bit out-of-bound varyings. 2025-04-16 16:35:23 +02:00
Giovanni Mascellani
26656808e6 tests/hlsl: Remove a test in which a function reads an "out" argument. 
The code doesn't make sense in the first place, even if it's
accepted by the compiler, so it makes sense that the behaviour
is undefined. And indeed the behaviour is different on AMD (4 is
returned), NVIDIA (QNaN is returned) and WARP (device is removed).
 2025-04-16 16:30:19 +02:00