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vkd3d-shader/hlsl: Add missing src1 and src2 constants to sincos on SM2.
The sincos instruction expects two specific constants on 2.0 and 2.1 profiles. Consider the following shader: uniform float u; float4 main() : sv_target { return sin(u); } On native, with ps_2_0, this compiles as: ps_2_0 def c3, 0.159154937, 0.5, 6.28318548, -3.14159274 def c1, -1.55009923e-006, -2.17013894e-005, 0.00260416674, 0.00026041668 def c2, -0.020833334, -0.125, 1, 0.5 mov r0.xy, c3 mad r0.x, c0.x, r0.x, r0.y frc r0.x, r0.x mad r0.x, r0.x, c3.z, c3.w sincos r1.y, r0.x, c1, c2 mov r0, r1.y mov oC0, r0 We are not emitting the src1 and src2 constant arguments before this patch.
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Notes:
Henri Verbeet
2024-07-31 22:42:18 +02:00
Approved-by: Giovanni Mascellani (@giomasce) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/961
@ -2374,12 +2374,40 @@ static void d3dbc_write_per_component_unary_op(struct d3dbc_compiler *d3dbc,
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static void d3dbc_write_sincos(struct d3dbc_compiler *d3dbc, enum hlsl_ir_expr_op op,
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const struct hlsl_reg *dst, const struct hlsl_reg *src)
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{
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struct sm1_instruction instr =
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{
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.opcode = D3DSIO_SINCOS,
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.dst.type = VKD3DSPR_TEMP,
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.dst.writemask = dst->writemask,
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.dst.reg = dst->id,
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.has_dst = 1,
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.srcs[0].type = VKD3DSPR_TEMP,
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.srcs[0].swizzle = hlsl_swizzle_from_writemask(src->writemask),
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.srcs[0].reg = src->id,
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.src_count = 1,
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};
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if (op == HLSL_OP1_COS_REDUCED)
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VKD3D_ASSERT(dst->writemask == VKD3DSP_WRITEMASK_0);
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else /* HLSL_OP1_SIN_REDUCED */
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VKD3D_ASSERT(dst->writemask == VKD3DSP_WRITEMASK_1);
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d3dbc_write_unary_op(d3dbc, D3DSIO_SINCOS, dst, src, 0, 0);
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if (d3dbc->ctx->profile->major_version < 3)
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{
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instr.src_count = 3;
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instr.srcs[1].type = VKD3DSPR_CONST;
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instr.srcs[1].swizzle = hlsl_swizzle_from_writemask(VKD3DSP_WRITEMASK_ALL);
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instr.srcs[1].reg = d3dbc->ctx->d3dsincosconst1.id;
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instr.srcs[2].type = VKD3DSPR_CONST;
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instr.srcs[2].swizzle = hlsl_swizzle_from_writemask(VKD3DSP_WRITEMASK_ALL);
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instr.srcs[2].reg = d3dbc->ctx->d3dsincosconst2.id;
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}
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d3dbc_write_instruction(d3dbc, &instr);
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}
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static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_node *instr)
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@ -1001,6 +1001,8 @@ struct hlsl_ctx
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} *regs;
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size_t count, size;
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} constant_defs;
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/* 'c' registers where the constants expected by SM2 sincos are stored. */
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struct hlsl_reg d3dsincosconst1, d3dsincosconst2;
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/* Number of temp. registers required for the shader to run, i.e. the largest temp register
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* index that will be used in the output bytecode (+1). */
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uint32_t temp_count;
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@ -4845,6 +4845,43 @@ static void sort_uniforms_by_numeric_bind_count(struct hlsl_ctx *ctx)
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list_move_tail(&ctx->extern_vars, &sorted);
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}
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/* In SM2, 'sincos' expects specific constants as src1 and src2 arguments.
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* These have to be referenced directly, i.e. as 'c' not 'r'. */
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static void allocate_sincos_const_registers(struct hlsl_ctx *ctx, struct hlsl_block *block,
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struct register_allocator *allocator)
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{
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const struct hlsl_ir_node *instr;
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struct hlsl_type *type;
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if (ctx->profile->major_version >= 3)
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return;
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LIST_FOR_EACH_ENTRY(instr, &block->instrs, struct hlsl_ir_node, entry)
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{
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if (instr->type == HLSL_IR_EXPR && (hlsl_ir_expr(instr)->op == HLSL_OP1_SIN_REDUCED
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|| hlsl_ir_expr(instr)->op == HLSL_OP1_COS_REDUCED))
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{
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type = hlsl_get_vector_type(ctx, HLSL_TYPE_FLOAT, 4);
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ctx->d3dsincosconst1 = allocate_numeric_registers_for_type(ctx, allocator, 1, UINT_MAX, type);
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TRACE("Allocated D3DSINCOSCONST1 to %s.\n", debug_register('c', ctx->d3dsincosconst1, type));
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record_constant(ctx, ctx->d3dsincosconst1.id * 4 + 0, -1.55009923e-06f);
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record_constant(ctx, ctx->d3dsincosconst1.id * 4 + 1, -2.17013894e-05f);
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record_constant(ctx, ctx->d3dsincosconst1.id * 4 + 2, 2.60416674e-03f);
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record_constant(ctx, ctx->d3dsincosconst1.id * 4 + 3, 2.60416680e-04f);
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ctx->d3dsincosconst2 = allocate_numeric_registers_for_type(ctx, allocator, 1, UINT_MAX, type);
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TRACE("Allocated D3DSINCOSCONST2 to %s.\n", debug_register('c', ctx->d3dsincosconst2, type));
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record_constant(ctx, ctx->d3dsincosconst2.id * 4 + 0, -2.08333340e-02f);
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record_constant(ctx, ctx->d3dsincosconst2.id * 4 + 1, -1.25000000e-01f);
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record_constant(ctx, ctx->d3dsincosconst2.id * 4 + 2, 1.00000000e+00f);
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record_constant(ctx, ctx->d3dsincosconst2.id * 4 + 3, 5.00000000e-01f);
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return;
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}
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}
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}
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static void allocate_const_registers(struct hlsl_ctx *ctx, struct hlsl_ir_function_decl *entry_func)
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{
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struct register_allocator allocator_used = {0};
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@ -4909,6 +4946,8 @@ static void allocate_const_registers(struct hlsl_ctx *ctx, struct hlsl_ir_functi
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allocate_const_registers_recurse(ctx, &entry_func->body, &allocator);
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allocate_sincos_const_registers(ctx, &entry_func->body, &allocator);
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vkd3d_free(allocator.allocations);
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}
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