From d9d2a00ef3d0f442d96b7c31d14d97558b616192 Mon Sep 17 00:00:00 2001 From: Henri Verbeet Date: Mon, 22 Sep 2025 17:33:42 +0200 Subject: [PATCH] vkd3d-shader/msl: Implement VSIR_OP_ASIN. --- libs/vkd3d-shader/msl.c | 3 +++ tests/hlsl/inverse-trig.shader_test | 21 ++++++++++----------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/libs/vkd3d-shader/msl.c b/libs/vkd3d-shader/msl.c index 10ed99283..9444334b6 100644 --- a/libs/vkd3d-shader/msl.c +++ b/libs/vkd3d-shader/msl.c @@ -1470,6 +1470,9 @@ static void msl_handle_instruction(struct msl_generator *gen, const struct vkd3d case VSIR_OP_AND: msl_binop(gen, ins, "&"); break; + case VSIR_OP_ASIN: + msl_intrinsic(gen, ins, "asin"); + break; case VSIR_OP_BREAK: msl_break(gen); break; diff --git a/tests/hlsl/inverse-trig.shader_test b/tests/hlsl/inverse-trig.shader_test index 3474e1b45..dd05cc0d0 100644 --- a/tests/hlsl/inverse-trig.shader_test +++ b/tests/hlsl/inverse-trig.shader_test @@ -44,8 +44,8 @@ float4 main() : sv_target [test] uniform 0 float4 -1.0 0.0 0.0 0.0 -todo(msl & sm>=6) draw quad -probe (0, 0) rgba (-31416.0, 0.0, 0.0, 0.0) +draw quad +probe (0, 0) f32(-31416.0, 0.0, 0.0, 0.0) [require] shader model < 6.0 @@ -72,25 +72,24 @@ shader model >= 6.0 % RADV are a bit lower than these, hence the large max ulp difference. [test] uniform 0 float4 -0.5 0.0 0.0 0.0 -todo(msl & sm>=6) draw quad -probe (0, 0) rgba (-10472.0, 0.0, 0.0, 0.0) 4096 +draw quad +probe (0, 0) f32(-10472.0, 0.0, 0.0, 0.0) 4096 uniform 0 float4 0.0 0.0 0.0 0.0 -todo(msl & sm>=6) draw quad -probe (0, 0) rgba (0.0, 0.0, 0.0, 0.0) +draw quad +probe (0, 0) f32(0.0, 0.0, 0.0, 0.0) uniform 0 float4 0.5 0.0 0.0 0.0 -todo(msl & sm>=6) draw quad -probe (0, 0) rgba (10472.0, 0.0, 0.0, 0.0) 4096 +draw quad +probe (0, 0) f32(10472.0, 0.0, 0.0, 0.0) 4096 [require] % reset requirements [test] uniform 0 float4 1.0 0.0 0.0 0.0 -todo(msl & sm>=6) draw quad -probe (0, 0) rgba (31416.0, 0.0, 0.0, 0.0) - +draw quad +probe (0, 0) f32(31416.0, 0.0, 0.0, 0.0) [pixel shader] uniform float4 a;