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vkd3d-shader/dxil: Implement DX instruction StoreOutput.
This commit is contained in:
Conor McCarthy
Alexandre Julliard
parent
bf49a1a95b
commit
d27b8eb2c0
Notes:
Alexandre Julliard
2023-08-30 23:19:25 +02:00
Approved-by: Giovanni Mascellani (@giomasce) Approved-by: Henri Verbeet (@hverbeet) Approved-by: Alexandre Julliard (@julliard) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/283
@ -139,6 +139,11 @@ enum bitcode_value_symtab_code
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VST_CODE_BBENTRY = 2,
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};
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enum dx_intrinsic_opcode
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{
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DX_STORE_OUTPUT = 5,
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};
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struct sm6_pointer_info
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{
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const struct sm6_type *type;
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@ -1269,6 +1274,16 @@ static inline bool sm6_type_is_integer(const struct sm6_type *type)
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return type->class == TYPE_CLASS_INTEGER;
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}
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static inline bool sm6_type_is_i8(const struct sm6_type *type)
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{
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return type->class == TYPE_CLASS_INTEGER && type->u.width == 8;
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}
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static inline bool sm6_type_is_i32(const struct sm6_type *type)
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{
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return type->class == TYPE_CLASS_INTEGER && type->u.width == 32;
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}
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static inline bool sm6_type_is_floating_point(const struct sm6_type *type)
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{
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return type->class == TYPE_CLASS_FLOAT;
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@ -1520,6 +1535,50 @@ static inline bool sm6_value_is_constant(const struct sm6_value *value)
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return sm6_value_is_register(value) && register_is_constant(&value->u.reg);
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}
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static inline bool sm6_value_is_undef(const struct sm6_value *value)
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{
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return sm6_value_is_register(value) && value->u.reg.type == VKD3DSPR_UNDEF;
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}
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static inline unsigned int sm6_value_get_constant_uint(const struct sm6_value *value)
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{
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if (!sm6_value_is_constant(value))
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return UINT_MAX;
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return register_get_uint_value(&value->u.reg);
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}
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static struct vkd3d_shader_src_param *instruction_src_params_alloc(struct vkd3d_shader_instruction *ins,
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unsigned int count, struct sm6_parser *sm6)
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{
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struct vkd3d_shader_src_param *params = shader_parser_get_src_params(&sm6->p, count);
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if (!params)
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{
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ERR("Failed to allocate src params.\n");
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_OUT_OF_MEMORY,
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"Out of memory allocating instruction src paramaters.");
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return NULL;
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}
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ins->src = params;
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ins->src_count = count;
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return params;
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}
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static struct vkd3d_shader_dst_param *instruction_dst_params_alloc(struct vkd3d_shader_instruction *ins,
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unsigned int count, struct sm6_parser *sm6)
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{
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struct vkd3d_shader_dst_param *params = shader_parser_get_dst_params(&sm6->p, count);
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if (!params)
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{
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ERR("Failed to allocate dst params.\n");
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_OUT_OF_MEMORY,
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"Out of memory allocating instruction dst paramaters.");
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return NULL;
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}
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ins->dst = params;
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ins->dst_count = count;
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return params;
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}
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static enum vkd3d_data_type vkd3d_data_type_from_sm6_type(const struct sm6_type *type)
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{
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if (type->class == TYPE_CLASS_INTEGER)
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@ -1553,6 +1612,47 @@ static enum vkd3d_data_type vkd3d_data_type_from_sm6_type(const struct sm6_type
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return VKD3D_DATA_UINT;
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}
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static inline void dst_param_init_scalar(struct vkd3d_shader_dst_param *param, unsigned int component_idx)
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{
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param->write_mask = 1u << component_idx;
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param->modifiers = 0;
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param->shift = 0;
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}
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static inline void src_param_init(struct vkd3d_shader_src_param *param)
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{
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param->swizzle = VKD3D_SHADER_SWIZZLE(X, X, X, X);
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param->modifiers = VKD3DSPSM_NONE;
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}
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static void src_param_init_from_value(struct vkd3d_shader_src_param *param, const struct sm6_value *src)
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{
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src_param_init(param);
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param->reg = src->u.reg;
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}
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static void register_address_init(struct vkd3d_shader_register *reg, const struct sm6_value *address,
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unsigned int idx, struct sm6_parser *sm6)
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{
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assert(idx < ARRAY_SIZE(reg->idx));
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if (sm6_value_is_constant(address))
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{
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reg->idx[idx].offset = sm6_value_get_constant_uint(address);
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}
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else if (sm6_value_is_undef(address))
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{
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reg->idx[idx].offset = 0;
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}
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else
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{
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struct vkd3d_shader_src_param *rel_addr = shader_parser_get_src_params(&sm6->p, 1);
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if (rel_addr)
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src_param_init_from_value(rel_addr, address);
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reg->idx[idx].offset = 0;
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reg->idx[idx].rel_addr = rel_addr;
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}
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}
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/* Recurse through the block tree while maintaining a current value count. The current
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* count is the sum of the global count plus all declarations within the current function.
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* Store into value_capacity the highest count seen. */
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@ -2050,6 +2150,137 @@ static struct sm6_block *sm6_block_create()
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return block;
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}
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static void sm6_parser_emit_dx_store_output(struct sm6_parser *sm6, struct sm6_block *code_block,
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enum dx_intrinsic_opcode op, const struct sm6_value **operands, struct vkd3d_shader_instruction *ins)
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{
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struct vkd3d_shader_src_param *src_param;
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struct vkd3d_shader_dst_param *dst_param;
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const struct shader_signature *signature;
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unsigned int row_index, column_index;
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const struct signature_element *e;
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const struct sm6_value *value;
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row_index = sm6_value_get_constant_uint(operands[0]);
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column_index = sm6_value_get_constant_uint(operands[2]);
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signature = &sm6->p.shader_desc.output_signature;
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if (row_index >= signature->element_count)
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{
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WARN("Invalid row index %u.\n", row_index);
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND,
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"Invalid output row index %u.", row_index);
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return;
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}
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e = &signature->elements[row_index];
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if (column_index >= VKD3D_VEC4_SIZE)
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{
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WARN("Invalid column index %u.\n", column_index);
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND,
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"Invalid output column index %u.", column_index);
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return;
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}
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value = operands[3];
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if (!sm6_value_is_register(value))
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{
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WARN("Source value is not a register.\n");
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND,
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"Expected store operation source to be a register.");
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return;
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}
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shader_instruction_init(ins, VKD3DSIH_MOV);
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if (!(dst_param = instruction_dst_params_alloc(ins, 1, sm6)))
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return;
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dst_param_init_scalar(dst_param, column_index);
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dst_param->reg = sm6->output_params[row_index].reg;
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if (e->register_count > 1)
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register_address_init(&dst_param->reg, operands[1], 0, sm6);
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if ((src_param = instruction_src_params_alloc(ins, 1, sm6)))
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src_param_init_from_value(src_param, value);
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}
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struct sm6_dx_opcode_info
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{
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const char ret_type;
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const char *operand_info;
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void (*handler)(struct sm6_parser *, struct sm6_block *, enum dx_intrinsic_opcode,
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const struct sm6_value **, struct vkd3d_shader_instruction *);
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};
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/*
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8 -> int8
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i -> int32
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v -> void
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o -> overloaded
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*/
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static const struct sm6_dx_opcode_info sm6_dx_op_table[] =
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{
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[DX_STORE_OUTPUT ] = {'v', "ii8o", sm6_parser_emit_dx_store_output},
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};
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static bool sm6_parser_validate_operand_type(struct sm6_parser *sm6, const struct sm6_type *type, char info_type)
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{
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switch (info_type)
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{
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case 0:
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FIXME("Invalid operand count.\n");
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return false;
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case '8':
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return sm6_type_is_i8(type);
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case 'i':
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return sm6_type_is_i32(type);
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case 'v':
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return !type;
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case 'o':
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/* TODO: some type checking may be possible */
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return true;
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default:
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FIXME("Unhandled operand code '%c'.\n", info_type);
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return false;
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}
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}
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static bool sm6_parser_validate_dx_op(struct sm6_parser *sm6, enum dx_intrinsic_opcode op, const char *name,
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const struct sm6_value **operands, unsigned int operand_count, struct sm6_value *dst)
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{
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const struct sm6_dx_opcode_info *info;
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unsigned int i;
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info = &sm6_dx_op_table[op];
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if (!sm6_parser_validate_operand_type(sm6, dst->type, info->ret_type))
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{
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WARN("Failed to validate return type for dx intrinsic id %u, '%s'.\n", op, name);
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/* Return type validation failure is not so critical. We only need to set
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* a data type for the SSA result. */
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}
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for (i = 0; i < operand_count; ++i)
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{
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const struct sm6_value *value = operands[i];
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if (!sm6_value_is_register(value) || !sm6_parser_validate_operand_type(sm6, value->type, info->operand_info[i]))
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{
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WARN("Failed to validate operand %u for dx intrinsic id %u, '%s'.\n", i + 1, op, name);
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND,
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"Operand %u for call to dx intrinsic function '%s' is invalid.", i + 1, name);
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return false;
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}
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}
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if (info->operand_info[operand_count])
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{
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WARN("Missing operands for dx intrinsic id %u, '%s'.\n", op, name);
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vkd3d_shader_parser_error(&sm6->p, VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND_COUNT,
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"Call to dx intrinsic function '%s' has missing operands.", name);
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return false;
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}
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return true;
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}
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static void sm6_parser_emit_unhandled(struct sm6_parser *sm6, struct vkd3d_shader_instruction *ins,
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struct sm6_value *dst)
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{
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@ -2065,14 +2296,23 @@ static void sm6_parser_emit_unhandled(struct sm6_parser *sm6, struct vkd3d_shade
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/* dst->is_undefined is not set here because it flags only explicitly undefined values. */
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}
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static void sm6_parser_decode_dx_op(struct sm6_parser *sm6, struct sm6_block *code_block, unsigned int op,
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static void sm6_parser_decode_dx_op(struct sm6_parser *sm6, struct sm6_block *code_block, enum dx_intrinsic_opcode op,
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const char *name, const struct sm6_value **operands, unsigned int operand_count,
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struct vkd3d_shader_instruction *ins, struct sm6_value *dst)
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{
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FIXME("Unhandled dx intrinsic function id %u, '%s'.\n", op, name);
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vkd3d_shader_parser_warning(&sm6->p, VKD3D_SHADER_WARNING_DXIL_UNHANDLED_INTRINSIC,
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"Call to intrinsic function %s is unhandled.", name);
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sm6_parser_emit_unhandled(sm6, ins, dst);
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if (op >= ARRAY_SIZE(sm6_dx_op_table) || !sm6_dx_op_table[op].operand_info)
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{
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FIXME("Unhandled dx intrinsic function id %u, '%s'.\n", op, name);
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vkd3d_shader_parser_warning(&sm6->p, VKD3D_SHADER_WARNING_DXIL_UNHANDLED_INTRINSIC,
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"Call to intrinsic function %s is unhandled.", name);
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sm6_parser_emit_unhandled(sm6, ins, dst);
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return;
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}
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if (sm6_parser_validate_dx_op(sm6, op, name, operands, operand_count, dst))
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sm6_dx_op_table[op].handler(sm6, code_block, op, operands, ins);
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else
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sm6_parser_emit_unhandled(sm6, ins, dst);
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}
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static void sm6_parser_emit_call(struct sm6_parser *sm6, const struct dxil_record *record,
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