From c1d9e776e250de9330e6acece4d3551197a029fe Mon Sep 17 00:00:00 2001 From: Francisco Casas Date: Mon, 4 Sep 2023 18:58:11 -0300 Subject: [PATCH] vkd3d-shader/tpf: Use vsir_register_init() in shader_sm4_read_param(). --- libs/vkd3d-shader/tpf.c | 35 ++++++++++------------------------- 1 file changed, 10 insertions(+), 25 deletions(-) diff --git a/libs/vkd3d-shader/tpf.c b/libs/vkd3d-shader/tpf.c index 58b7f030..d7f2c0f4 100644 --- a/libs/vkd3d-shader/tpf.c +++ b/libs/vkd3d-shader/tpf.c @@ -1713,6 +1713,7 @@ static bool shader_sm4_read_param(struct vkd3d_shader_sm4_parser *priv, const ui enum vkd3d_data_type data_type, struct vkd3d_shader_register *param, enum vkd3d_shader_src_modifier *modifier) { const struct vkd3d_sm4_register_type_info *register_type_info; + enum vkd3d_shader_register_type vsir_register_type; enum vkd3d_sm4_register_precision precision; enum vkd3d_sm4_register_type register_type; enum vkd3d_sm4_extended_operand_type type; @@ -1731,15 +1732,18 @@ static bool shader_sm4_read_param(struct vkd3d_shader_sm4_parser *priv, const ui if (!register_type_info) { FIXME("Unhandled register type %#x.\n", register_type); - param->type = VKD3DSPR_TEMP; + vsir_register_type = VKD3DSPR_TEMP; } else { - param->type = register_type_info->vkd3d_type; + vsir_register_type = register_type_info->vkd3d_type; } + + order = (token & VKD3D_SM4_REGISTER_ORDER_MASK) >> VKD3D_SM4_REGISTER_ORDER_SHIFT; + + vsir_register_init(param, vsir_register_type, data_type, order); param->precision = VKD3D_SHADER_REGISTER_PRECISION_DEFAULT; param->non_uniform = false; - param->data_type = data_type; *modifier = VKD3DSPSM_NONE; if (token & VKD3D_SM4_EXTENDED_OPERAND) @@ -1809,14 +1813,7 @@ static bool shader_sm4_read_param(struct vkd3d_shader_sm4_parser *priv, const ui } } - order = (token & VKD3D_SM4_REGISTER_ORDER_MASK) >> VKD3D_SM4_REGISTER_ORDER_SHIFT; - - if (order < 1) - { - param->idx[0].offset = ~0u; - param->idx[0].rel_addr = NULL; - } - else + if (order >= 1) { DWORD addressing = (token & VKD3D_SM4_ADDRESSING_MASK0) >> VKD3D_SM4_ADDRESSING_SHIFT0; if (!(shader_sm4_read_reg_idx(priv, ptr, end, addressing, ¶m->idx[0]))) @@ -1826,12 +1823,7 @@ static bool shader_sm4_read_param(struct vkd3d_shader_sm4_parser *priv, const ui } } - if (order < 2) - { - param->idx[1].offset = ~0u; - param->idx[1].rel_addr = NULL; - } - else + if (order >= 2) { DWORD addressing = (token & VKD3D_SM4_ADDRESSING_MASK1) >> VKD3D_SM4_ADDRESSING_SHIFT1; if (!(shader_sm4_read_reg_idx(priv, ptr, end, addressing, ¶m->idx[1]))) @@ -1841,12 +1833,7 @@ static bool shader_sm4_read_param(struct vkd3d_shader_sm4_parser *priv, const ui } } - if (order < 3) - { - param->idx[2].offset = ~0u; - param->idx[2].rel_addr = NULL; - } - else + if (order >= 3) { DWORD addressing = (token & VKD3D_SM4_ADDRESSING_MASK2) >> VKD3D_SM4_ADDRESSING_SHIFT2; if (!(shader_sm4_read_reg_idx(priv, ptr, end, addressing, ¶m->idx[2]))) @@ -1862,8 +1849,6 @@ static bool shader_sm4_read_param(struct vkd3d_shader_sm4_parser *priv, const ui return false; } - param->idx_count = order; - if (register_type == VKD3D_SM4_RT_IMMCONST || register_type == VKD3D_SM4_RT_IMMCONST64) { enum vkd3d_sm4_dimension dimension = (token & VKD3D_SM4_DIMENSION_MASK) >> VKD3D_SM4_DIMENSION_SHIFT;