vkd3d-shader: Add basic support for dcl_index_range.

We can address SPIR-V arrays dynamically.

Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
This commit is contained in:
Józef Kucia 2019-02-20 13:42:53 +01:00 committed by Alexandre Julliard
parent a248aced81
commit b6de566e3a
4 changed files with 76 additions and 10 deletions

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@ -619,8 +619,8 @@ static void shader_sm4_read_dcl_index_range(struct vkd3d_shader_instruction *ins
struct vkd3d_sm4_data *priv) struct vkd3d_sm4_data *priv)
{ {
shader_sm4_read_dst_param(priv, &tokens, &tokens[token_count], VKD3D_DATA_OPAQUE, shader_sm4_read_dst_param(priv, &tokens, &tokens[token_count], VKD3D_DATA_OPAQUE,
&ins->declaration.index_range.first_register); &ins->declaration.index_range.dst);
ins->declaration.index_range.last_register = *tokens; ins->declaration.index_range.register_count = *tokens;
} }
static void shader_sm4_read_dcl_output_topology(struct vkd3d_shader_instruction *ins, static void shader_sm4_read_dcl_output_topology(struct vkd3d_shader_instruction *ins,

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@ -2568,14 +2568,17 @@ static void vkd3d_dxbc_compiler_emit_dereference_register(struct vkd3d_dxbc_comp
} }
else if (register_info->is_aggregate) else if (register_info->is_aggregate)
{ {
if (reg->idx[0].rel_addr || reg->idx[1].rel_addr) if (reg->idx[1].rel_addr)
FIXME("Relative addressing not implemented.\n"); FIXME("Relative addressing not implemented.\n");
indexes[index_count++] = vkd3d_dxbc_compiler_get_constant_uint(compiler, register_info->member_idx); if (reg->idx[0].rel_addr)
indexes[index_count++] = vkd3d_dxbc_compiler_emit_register_addressing(compiler, &reg->idx[0]);
else
indexes[index_count++] = vkd3d_dxbc_compiler_get_constant_uint(compiler, register_info->member_idx);
} }
else else
{ {
if (reg->idx[1].rel_addr) if (reg->idx[1].rel_addr || (reg->idx[1].offset == ~0u && reg->idx[0].rel_addr))
FIXME("Relative addressing not implemented.\n"); FIXME("Relative addressing not implemented.\n");
/* Handle arrayed registers, e.g. v[3][0]. */ /* Handle arrayed registers, e.g. v[3][0]. */
@ -4754,6 +4757,64 @@ static void vkd3d_dxbc_compiler_emit_dcl_output_siv(struct vkd3d_dxbc_compiler *
vkd3d_dxbc_compiler_emit_output(compiler, dst, sysval); vkd3d_dxbc_compiler_emit_output(compiler, dst, sysval);
} }
static bool vkd3d_dxbc_compiler_check_index_range(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_index_range *range)
{
const struct vkd3d_shader_register *reg = &range->dst.reg;
struct vkd3d_shader_register_info reg_info;
struct vkd3d_shader_register current_reg;
struct vkd3d_symbol reg_symbol;
unsigned int i;
uint32_t id;
current_reg = *reg;
vkd3d_symbol_make_register(&reg_symbol, &current_reg);
if (!vkd3d_dxbc_compiler_get_register_info(compiler, &current_reg, &reg_info))
{
ERR("Failed to get register info.\n");
return false;
}
/* FIXME: We should check if it's an array. */
if (!reg_info.is_aggregate)
{
FIXME("Unhandled register %#x.\n", reg->type);
return false;
}
id = reg_info.id;
for (i = reg->idx[0].offset; i < reg->idx[0].offset + range->register_count; ++i)
{
current_reg.idx[0].offset = i;
vkd3d_symbol_make_register(&reg_symbol, &current_reg);
if (range->dst.write_mask != reg_info.write_mask
|| vkd3d_write_mask_component_count(reg_info.write_mask) != 1)
{
FIXME("Unhandled index range write mask %#x (%#x).\n",
range->dst.write_mask, reg_info.write_mask);
return false;
}
if (reg_info.id != id)
{
FIXME("Unhandled index range %#x, %u.\n", reg->type, i);
return false;
}
}
return true;
}
static void vkd3d_dxbc_compiler_emit_dcl_index_range(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
const struct vkd3d_shader_index_range *range = &instruction->declaration.index_range;
if (!vkd3d_dxbc_compiler_check_index_range(compiler, range))
FIXME("Ignoring dcl_index_range %#x %u.\n", range->dst.reg.type, range->register_count);
}
static void vkd3d_dxbc_compiler_emit_dcl_stream(struct vkd3d_dxbc_compiler *compiler, static void vkd3d_dxbc_compiler_emit_dcl_stream(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction) const struct vkd3d_shader_instruction *instruction)
{ {
@ -7388,6 +7449,9 @@ int vkd3d_dxbc_compiler_handle_instruction(struct vkd3d_dxbc_compiler *compiler,
case VKD3DSIH_DCL_OUTPUT_SIV: case VKD3DSIH_DCL_OUTPUT_SIV:
vkd3d_dxbc_compiler_emit_dcl_output_siv(compiler, instruction); vkd3d_dxbc_compiler_emit_dcl_output_siv(compiler, instruction);
break; break;
case VKD3DSIH_DCL_INDEX_RANGE:
vkd3d_dxbc_compiler_emit_dcl_index_range(compiler, instruction);
break;
case VKD3DSIH_DCL_STREAM: case VKD3DSIH_DCL_STREAM:
vkd3d_dxbc_compiler_emit_dcl_stream(compiler, instruction); vkd3d_dxbc_compiler_emit_dcl_stream(compiler, instruction);
break; break;
@ -7730,7 +7794,6 @@ static void vkd3d_dxbc_compiler_emit_shader_epilogue_function(struct vkd3d_dxbc_
vkd3d_spirv_build_op_function(builder, void_id, function_id, vkd3d_spirv_build_op_function(builder, void_id, function_id,
SpvFunctionControlMaskNone, function_type_id); SpvFunctionControlMaskNone, function_type_id);
vkd3d_spirv_build_op_name(builder, function_id, "epilogue");
for (i = 0; i < ARRAY_SIZE(compiler->private_output_variable); ++i) for (i = 0; i < ARRAY_SIZE(compiler->private_output_variable); ++i)
{ {
@ -7789,7 +7852,10 @@ int vkd3d_dxbc_compiler_generate_spirv(struct vkd3d_dxbc_compiler *compiler,
} }
if (compiler->epilogue_function_id) if (compiler->epilogue_function_id)
{
vkd3d_spirv_build_op_name(builder, compiler->epilogue_function_id, "epilogue");
vkd3d_dxbc_compiler_emit_shader_epilogue_function(compiler); vkd3d_dxbc_compiler_emit_shader_epilogue_function(compiler);
}
if (compiler->options & VKD3D_SHADER_STRIP_DEBUG) if (compiler->options & VKD3D_SHADER_STRIP_DEBUG)
vkd3d_spirv_stream_clear(&builder->debug_stream); vkd3d_spirv_stream_clear(&builder->debug_stream);

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@ -1389,8 +1389,8 @@ static void shader_dump_instruction(struct vkd3d_string_buffer *buffer,
case VKD3DSIH_DCL_INDEX_RANGE: case VKD3DSIH_DCL_INDEX_RANGE:
shader_addline(buffer, "%s ", shader_opcode_names[ins->handler_idx]); shader_addline(buffer, "%s ", shader_opcode_names[ins->handler_idx]);
shader_dump_dst_param(buffer, &ins->declaration.index_range.first_register, shader_version); shader_dump_dst_param(buffer, &ins->declaration.index_range.dst, shader_version);
shader_addline(buffer, " %u", ins->declaration.index_range.last_register); shader_addline(buffer, " %u", ins->declaration.index_range.register_count);
break; break;
case VKD3DSIH_DCL_INDEXABLE_TEMP: case VKD3DSIH_DCL_INDEXABLE_TEMP:

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@ -584,8 +584,8 @@ struct vkd3d_shader_src_param
struct vkd3d_shader_index_range struct vkd3d_shader_index_range
{ {
struct vkd3d_shader_dst_param first_register; struct vkd3d_shader_dst_param dst;
unsigned int last_register; unsigned int register_count;
}; };
enum vkd3d_decl_usage enum vkd3d_decl_usage